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https://github.com/tianocore/edk2
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CryptoPkg: Add AARCH64-PE Target to OpenSSL Gen
CLANGPDB does not support the same asm syntax as GCC/CLANGDWARF. As a result, the autogenerated ASM files in CryptoPkg need a new flavor for CLANGPDB, which is supported by OpenSSL. This adds support to the autogeneration script to support the new flavor, as well as running the script and checking in the generated asm files. To reflect the intention better than toolchain name (as AARCH64-GCC is already out of date), the directories are renamed to AARCH64-ELF (the former AARCH64-GCC) and AARCH64-PE (what CLANGPDB uses). In order to support this, a new PCD is introduced in CryptoPkg, gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe which instructs the build system to include the PE target asm files or the ELF target asm files. GCC and CLANGDWARF will use the ELF target files and CLANGPDB uses the PE target files. This matches the X64 behavior to toggle between the asm files. Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
This commit is contained in:
Oliver Smith-Denny
mergify[bot]
parent
1f33246fe9
commit
3f677aa69e
36 changed files with 37128 additions and 33 deletions
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@ -85,6 +85,15 @@
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# @Prompt Use NASM assembly source files for optimized version of OpensslLib for IA32/X64
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gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStyleNasm|FALSE|BOOLEAN|0x00000003
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[PcdsFeatureFlag.AARCH64]
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## Enable the use of PE target assembly source files when building an optimized
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# version of OpensslLib from generated assembly source files for AARCH64.
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# The generated PE target assembly source files only work with the CLANGPDB toolchain.
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# GCC and CLANGDWARF must use the ELF target assembly source files.
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# The default setting is to not use the PE target assembly source files.
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# @Prompt Use PE target assembly source files for optimized version of OpensslLib for AARCH64
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gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe|FALSE|BOOLEAN|0x00000004
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[PcdsFixedAtBuild]
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## Enable/Disable the families and individual services produced by the
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# EDK II Crypto Protocols/PPIs. The default is all services disabled.
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@ -22,3 +22,13 @@ gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStyleNasm|TRUE
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!if $(HOST_BASED_UNIT_TESTING_ENABLED) AND $(WIN_HOST_BUILD)
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gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStyleNasm|TRUE
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!endif
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[PcdsFeatureFlag.AARCH64]
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#
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# Use the PE target assembly source files when building with the CLANGPDB
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# toolchain.
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# GCC and CLANGDWARF use the default PCD value of ELF target assembly source files.
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#
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!if "$(TOOL_CHAIN_TAG)" == "CLANGPDB"
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gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe|TRUE
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!endif
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File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -0,0 +1,310 @@
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#include "arm_arch.h"
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.text
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.arch armv8-a+crypto
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.align 5
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.globl _armv7_neon_probe
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.def _armv7_neon_probe
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.type 32
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.endef
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_armv7_neon_probe:
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AARCH64_VALID_CALL_TARGET
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orr v15.16b, v15.16b, v15.16b
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ret
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.globl _armv7_tick
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.def _armv7_tick
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.type 32
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.endef
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_armv7_tick:
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AARCH64_VALID_CALL_TARGET
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#ifdef __APPLE__
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mrs x0, CNTPCT_EL0
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#else
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mrs x0, CNTVCT_EL0
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#endif
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ret
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.globl _armv8_aes_probe
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.def _armv8_aes_probe
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.type 32
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.endef
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_armv8_aes_probe:
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AARCH64_VALID_CALL_TARGET
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aese v0.16b, v0.16b
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ret
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.globl _armv8_sha1_probe
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.def _armv8_sha1_probe
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.type 32
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.endef
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_armv8_sha1_probe:
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AARCH64_VALID_CALL_TARGET
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sha1h s0, s0
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ret
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.globl _armv8_sha256_probe
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.def _armv8_sha256_probe
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.type 32
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.endef
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_armv8_sha256_probe:
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AARCH64_VALID_CALL_TARGET
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sha256su0 v0.4s, v0.4s
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ret
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.globl _armv8_pmull_probe
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.def _armv8_pmull_probe
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.type 32
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.endef
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_armv8_pmull_probe:
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AARCH64_VALID_CALL_TARGET
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pmull v0.1q, v0.1d, v0.1d
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ret
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.globl _armv8_sm4_probe
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.def _armv8_sm4_probe
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.type 32
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.endef
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_armv8_sm4_probe:
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AARCH64_VALID_CALL_TARGET
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.long 0xcec08400 // sm4e v0.4s, v0.4s
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ret
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.globl _armv8_sha512_probe
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.def _armv8_sha512_probe
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.type 32
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.endef
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_armv8_sha512_probe:
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AARCH64_VALID_CALL_TARGET
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.long 0xcec08000 // sha512su0 v0.2d,v0.2d
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ret
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.globl _armv8_eor3_probe
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.def _armv8_eor3_probe
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.type 32
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.endef
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_armv8_eor3_probe:
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AARCH64_VALID_CALL_TARGET
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.long 0xce010800 // eor3 v0.16b, v0.16b, v1.16b, v2.16b
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ret
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.globl _armv8_sve_probe
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.def _armv8_sve_probe
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.type 32
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.endef
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_armv8_sve_probe:
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AARCH64_VALID_CALL_TARGET
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.long 0x04a03000 // eor z0.d,z0.d,z0.d
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ret
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.globl _armv8_sve2_probe
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.def _armv8_sve2_probe
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.type 32
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.endef
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_armv8_sve2_probe:
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AARCH64_VALID_CALL_TARGET
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.long 0x04e03400 // xar z0.d,z0.d,z0.d
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ret
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.globl _armv8_cpuid_probe
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.def _armv8_cpuid_probe
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.type 32
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.endef
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_armv8_cpuid_probe:
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AARCH64_VALID_CALL_TARGET
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mrs x0, midr_el1
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ret
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.globl _armv8_sm3_probe
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.def _armv8_sm3_probe
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.type 32
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.endef
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_armv8_sm3_probe:
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AARCH64_VALID_CALL_TARGET
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.long 0xce63c004 // sm3partw1 v4.4s, v0.4s, v3.4s
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ret
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.globl OPENSSL_cleanse
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.def OPENSSL_cleanse
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.type 32
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.endef
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.align 5
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OPENSSL_cleanse:
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AARCH64_VALID_CALL_TARGET
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cbz x1,Lret // len==0?
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cmp x1,#15
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b.hi Lot // len>15
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nop
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Little:
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strb wzr,[x0],#1 // store byte-by-byte
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subs x1,x1,#1
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b.ne Little
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Lret: ret
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.align 4
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Lot: tst x0,#7
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b.eq Laligned // inp is aligned
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strb wzr,[x0],#1 // store byte-by-byte
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sub x1,x1,#1
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b Lot
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.align 4
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Laligned:
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str xzr,[x0],#8 // store word-by-word
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sub x1,x1,#8
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tst x1,#-8
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b.ne Laligned // len>=8
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cbnz x1,Little // len!=0?
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ret
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.globl CRYPTO_memcmp
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.def CRYPTO_memcmp
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.type 32
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.endef
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.align 4
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CRYPTO_memcmp:
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AARCH64_VALID_CALL_TARGET
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eor w3,w3,w3
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cbz x2,Lno_data // len==0?
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cmp x2,#16
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b.ne Loop_cmp
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ldp x8,x9,[x0]
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ldp x10,x11,[x1]
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eor x8,x8,x10
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eor x9,x9,x11
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orr x8,x8,x9
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mov x0,#1
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cmp x8,#0
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csel x0,xzr,x0,eq
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ret
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.align 4
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Loop_cmp:
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ldrb w4,[x0],#1
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ldrb w5,[x1],#1
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eor w4,w4,w5
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orr w3,w3,w4
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subs x2,x2,#1
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b.ne Loop_cmp
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Lno_data:
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neg w0,w3
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lsr w0,w0,#31
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ret
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.globl _armv8_rng_probe
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.def _armv8_rng_probe
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.type 32
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.endef
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_armv8_rng_probe:
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AARCH64_VALID_CALL_TARGET
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mrs x0, s3_3_c2_c4_0 // rndr
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mrs x0, s3_3_c2_c4_1 // rndrrs
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ret
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// Fill buffer with Randomly Generated Bytes
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// inputs: char * in x0 - Pointer to buffer
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// size_t in x1 - Number of bytes to write to buffer
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// outputs: size_t in x0 - Number of bytes successfully written to buffer
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.globl OPENSSL_rndr_asm
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.def OPENSSL_rndr_asm
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.type 32
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.endef
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.align 4
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OPENSSL_rndr_asm:
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AARCH64_VALID_CALL_TARGET
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mov x2,xzr
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mov x3,xzr
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.align 4
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Loop_rndr:
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cmp x1,#0
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b.eq .rndr_done
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mov x3,xzr
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mrs x3,s3_3_c2_c4_0
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b.eq .rndr_done
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cmp x1,#8
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b.lt Loop_single_byte_rndr
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str x3,[x0]
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add x0,x0,#8
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add x2,x2,#8
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subs x1,x1,#8
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b.ge Loop_rndr
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.align 4
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Loop_single_byte_rndr:
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strb w3,[x0]
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lsr x3,x3,#8
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add x2,x2,#1
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add x0,x0,#1
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subs x1,x1,#1
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b.gt Loop_single_byte_rndr
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.align 4
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.rndr_done:
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mov x0,x2
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ret
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// Fill buffer with Randomly Generated Bytes
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// inputs: char * in x0 - Pointer to buffer
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// size_t in x1 - Number of bytes to write to buffer
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// outputs: size_t in x0 - Number of bytes successfully written to buffer
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.globl OPENSSL_rndrrs_asm
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.def OPENSSL_rndrrs_asm
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.type 32
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.endef
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.align 4
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OPENSSL_rndrrs_asm:
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AARCH64_VALID_CALL_TARGET
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mov x2,xzr
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mov x3,xzr
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.align 4
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Loop_rndrrs:
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cmp x1,#0
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b.eq .rndrrs_done
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mov x3,xzr
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mrs x3,s3_3_c2_c4_1
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b.eq .rndrrs_done
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cmp x1,#8
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b.lt Loop_single_byte_rndrrs
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str x3,[x0]
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add x0,x0,#8
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add x2,x2,#8
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subs x1,x1,#8
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b.ge Loop_rndrrs
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.align 4
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Loop_single_byte_rndrrs:
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strb w3,[x0]
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lsr x3,x3,#8
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add x2,x2,#1
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add x0,x0,#1
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subs x1,x1,#1
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b.gt Loop_single_byte_rndrrs
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.align 4
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.rndrrs_done:
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mov x0,x2
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ret
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File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -0,0 +1,677 @@
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#include "arm_arch.h"
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.text
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.globl ossl_md5_block_asm_data_order
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ossl_md5_block_asm_data_order:
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AARCH64_VALID_CALL_TARGET
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// Save all callee-saved registers
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stp x19,x20,[sp,#-80]!
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stp x21,x22,[sp,#16]
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stp x23,x24,[sp,#32]
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stp x25,x26,[sp,#48]
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stp x27,x28,[sp,#64]
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ldp w10, w11, [x0, #0] // Load MD5 state->A and state->B
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ldp w12, w13, [x0, #8] // Load MD5 state->C and state->D
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.align 5
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ossl_md5_blocks_loop:
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eor x17, x12, x13 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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and x16, x17, x11 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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ldp w15, w20, [x1] // Load 2 words of input data0 M[0],M[1]
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ldp w3, w21, [x1, #8] // Load 2 words of input data0 M[2],M[3]
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#ifdef __AARCH64EB__
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rev w15, w15
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rev w20, w20
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rev w3, w3
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rev w21, w21
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#endif
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eor x14, x16, x13 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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movz x9, #0xa478 // Load lower half of constant 0xd76aa478
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movk x9, #0xd76a, lsl #16 // Load upper half of constant 0xd76aa478
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add w8, w10, w15 // Add dest value
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add w7, w8, w9 // Add constant 0xd76aa478
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add w6, w7, w14 // Add aux function result
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ror w6, w6, #25 // Rotate left s=7 bits
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eor x5, x11, x12 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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add w4, w11, w6 // Add X parameter round 1 A=FF(A, B, C, D, 0xd76aa478, s=7, M[0])
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and x8, x5, x4 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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eor x17, x8, x12 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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movz x16, #0xb756 // Load lower half of constant 0xe8c7b756
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movk x16, #0xe8c7, lsl #16 // Load upper half of constant 0xe8c7b756
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add w9, w13, w20 // Add dest value
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add w7, w9, w16 // Add constant 0xe8c7b756
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add w14, w7, w17 // Add aux function result
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ror w14, w14, #20 // Rotate left s=12 bits
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eor x6, x4, x11 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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add w5, w4, w14 // Add X parameter round 1 D=FF(D, A, B, C, 0xe8c7b756, s=12, M[1])
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and x8, x6, x5 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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eor x9, x8, x11 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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movz x16, #0x70db // Load lower half of constant 0x242070db
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movk x16, #0x2420, lsl #16 // Load upper half of constant 0x242070db
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add w7, w12, w3 // Add dest value
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add w17, w7, w16 // Add constant 0x242070db
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add w14, w17, w9 // Add aux function result
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ror w14, w14, #15 // Rotate left s=17 bits
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eor x6, x5, x4 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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add w8, w5, w14 // Add X parameter round 1 C=FF(C, D, A, B, 0x242070db, s=17, M[2])
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and x7, x6, x8 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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eor x16, x7, x4 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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movz x9, #0xceee // Load lower half of constant 0xc1bdceee
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movk x9, #0xc1bd, lsl #16 // Load upper half of constant 0xc1bdceee
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add w14, w11, w21 // Add dest value
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add w6, w14, w9 // Add constant 0xc1bdceee
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add w7, w6, w16 // Add aux function result
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ror w7, w7, #10 // Rotate left s=22 bits
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eor x17, x8, x5 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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add w9, w8, w7 // Add X parameter round 1 B=FF(B, C, D, A, 0xc1bdceee, s=22, M[3])
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ldp w14, w22, [x1, #16] // Load 2 words of input data0 M[4],M[5]
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ldp w7, w23, [x1, #24] // Load 2 words of input data0 M[6],M[7]
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#ifdef __AARCH64EB__
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rev w14, w14
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rev w22, w22
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rev w7, w7
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rev w23, w23
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#endif
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and x16, x17, x9 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
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eor x6, x16, x5 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
movz x16, #0xfaf // Load lower half of constant 0xf57c0faf
|
||||
movk x16, #0xf57c, lsl #16 // Load upper half of constant 0xf57c0faf
|
||||
add w17, w4, w14 // Add dest value
|
||||
add w16, w17, w16 // Add constant 0xf57c0faf
|
||||
add w4, w16, w6 // Add aux function result
|
||||
ror w4, w4, #25 // Rotate left s=7 bits
|
||||
eor x16, x9, x8 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
add w17, w9, w4 // Add X parameter round 1 A=FF(A, B, C, D, 0xf57c0faf, s=7, M[4])
|
||||
and x16, x16, x17 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
eor x6, x16, x8 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
movz x4, #0xc62a // Load lower half of constant 0x4787c62a
|
||||
movk x4, #0x4787, lsl #16 // Load upper half of constant 0x4787c62a
|
||||
add w16, w5, w22 // Add dest value
|
||||
add w16, w16, w4 // Add constant 0x4787c62a
|
||||
add w5, w16, w6 // Add aux function result
|
||||
ror w5, w5, #20 // Rotate left s=12 bits
|
||||
eor x4, x17, x9 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
add w19, w17, w5 // Add X parameter round 1 D=FF(D, A, B, C, 0x4787c62a, s=12, M[5])
|
||||
and x6, x4, x19 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
eor x5, x6, x9 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
movz x4, #0x4613 // Load lower half of constant 0xa8304613
|
||||
movk x4, #0xa830, lsl #16 // Load upper half of constant 0xa8304613
|
||||
add w6, w8, w7 // Add dest value
|
||||
add w8, w6, w4 // Add constant 0xa8304613
|
||||
add w4, w8, w5 // Add aux function result
|
||||
ror w4, w4, #15 // Rotate left s=17 bits
|
||||
eor x6, x19, x17 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
add w8, w19, w4 // Add X parameter round 1 C=FF(C, D, A, B, 0xa8304613, s=17, M[6])
|
||||
and x5, x6, x8 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
eor x4, x5, x17 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
movz x6, #0x9501 // Load lower half of constant 0xfd469501
|
||||
movk x6, #0xfd46, lsl #16 // Load upper half of constant 0xfd469501
|
||||
add w9, w9, w23 // Add dest value
|
||||
add w5, w9, w6 // Add constant 0xfd469501
|
||||
add w9, w5, w4 // Add aux function result
|
||||
ror w9, w9, #10 // Rotate left s=22 bits
|
||||
eor x6, x8, x19 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
add w4, w8, w9 // Add X parameter round 1 B=FF(B, C, D, A, 0xfd469501, s=22, M[7])
|
||||
ldp w5, w24, [x1, #32] // Load 2 words of input data0 M[8],M[9]
|
||||
ldp w16, w25, [x1, #40] // Load 2 words of input data0 M[10],M[11]
|
||||
#ifdef __AARCH64EB__
|
||||
rev w5, w5
|
||||
rev w24, w24
|
||||
rev w16, w16
|
||||
rev w25, w25
|
||||
#endif
|
||||
and x9, x6, x4 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
eor x6, x9, x19 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
movz x9, #0x98d8 // Load lower half of constant 0x698098d8
|
||||
movk x9, #0x6980, lsl #16 // Load upper half of constant 0x698098d8
|
||||
add w17, w17, w5 // Add dest value
|
||||
add w9, w17, w9 // Add constant 0x698098d8
|
||||
add w17, w9, w6 // Add aux function result
|
||||
ror w17, w17, #25 // Rotate left s=7 bits
|
||||
eor x9, x4, x8 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
add w6, w4, w17 // Add X parameter round 1 A=FF(A, B, C, D, 0x698098d8, s=7, M[8])
|
||||
and x17, x9, x6 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
eor x9, x17, x8 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
movz x17, #0xf7af // Load lower half of constant 0x8b44f7af
|
||||
movk x17, #0x8b44, lsl #16 // Load upper half of constant 0x8b44f7af
|
||||
add w19, w19, w24 // Add dest value
|
||||
add w17, w19, w17 // Add constant 0x8b44f7af
|
||||
add w19, w17, w9 // Add aux function result
|
||||
ror w19, w19, #20 // Rotate left s=12 bits
|
||||
eor x9, x6, x4 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
add w17, w6, w19 // Add X parameter round 1 D=FF(D, A, B, C, 0x8b44f7af, s=12, M[9])
|
||||
and x9, x9, x17 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
eor x9, x9, x4 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
movz x11, #0x5bb1 // Load lower half of constant 0xffff5bb1
|
||||
movk x11, #0xffff, lsl #16 // Load upper half of constant 0xffff5bb1
|
||||
add w8, w8, w16 // Add dest value
|
||||
add w8, w8, w11 // Add constant 0xffff5bb1
|
||||
add w8, w8, w9 // Add aux function result
|
||||
ror w8, w8, #15 // Rotate left s=17 bits
|
||||
eor x9, x17, x6 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
add w8, w17, w8 // Add X parameter round 1 C=FF(C, D, A, B, 0xffff5bb1, s=17, M[10])
|
||||
and x9, x9, x8 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
eor x9, x9, x6 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
movz x11, #0xd7be // Load lower half of constant 0x895cd7be
|
||||
movk x11, #0x895c, lsl #16 // Load upper half of constant 0x895cd7be
|
||||
add w4, w4, w25 // Add dest value
|
||||
add w4, w4, w11 // Add constant 0x895cd7be
|
||||
add w9, w4, w9 // Add aux function result
|
||||
ror w9, w9, #10 // Rotate left s=22 bits
|
||||
eor x4, x8, x17 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
add w9, w8, w9 // Add X parameter round 1 B=FF(B, C, D, A, 0x895cd7be, s=22, M[11])
|
||||
ldp w11, w26, [x1, #48] // Load 2 words of input data0 M[12],M[13]
|
||||
ldp w12, w27, [x1, #56] // Load 2 words of input data0 M[14],M[15]
|
||||
#ifdef __AARCH64EB__
|
||||
rev w11, w11
|
||||
rev w26, w26
|
||||
rev w12, w12
|
||||
rev w27, w27
|
||||
#endif
|
||||
and x4, x4, x9 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
eor x4, x4, x17 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
movz x19, #0x1122 // Load lower half of constant 0x6b901122
|
||||
movk x19, #0x6b90, lsl #16 // Load upper half of constant 0x6b901122
|
||||
add w6, w6, w11 // Add dest value
|
||||
add w6, w6, w19 // Add constant 0x6b901122
|
||||
add w4, w6, w4 // Add aux function result
|
||||
ror w4, w4, #25 // Rotate left s=7 bits
|
||||
eor x6, x9, x8 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
add w4, w9, w4 // Add X parameter round 1 A=FF(A, B, C, D, 0x6b901122, s=7, M[12])
|
||||
and x6, x6, x4 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
eor x6, x6, x8 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
movz x19, #0x7193 // Load lower half of constant 0xfd987193
|
||||
movk x19, #0xfd98, lsl #16 // Load upper half of constant 0xfd987193
|
||||
add w17, w17, w26 // Add dest value
|
||||
add w17, w17, w19 // Add constant 0xfd987193
|
||||
add w17, w17, w6 // Add aux function result
|
||||
ror w17, w17, #20 // Rotate left s=12 bits
|
||||
eor x6, x4, x9 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
add w17, w4, w17 // Add X parameter round 1 D=FF(D, A, B, C, 0xfd987193, s=12, M[13])
|
||||
and x6, x6, x17 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
eor x6, x6, x9 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
movz x13, #0x438e // Load lower half of constant 0xa679438e
|
||||
movk x13, #0xa679, lsl #16 // Load upper half of constant 0xa679438e
|
||||
add w8, w8, w12 // Add dest value
|
||||
add w8, w8, w13 // Add constant 0xa679438e
|
||||
add w8, w8, w6 // Add aux function result
|
||||
ror w8, w8, #15 // Rotate left s=17 bits
|
||||
eor x6, x17, x4 // Begin aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
add w8, w17, w8 // Add X parameter round 1 C=FF(C, D, A, B, 0xa679438e, s=17, M[14])
|
||||
and x6, x6, x8 // Continue aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
eor x6, x6, x4 // End aux function round 1 F(x,y,z)=(((y^z)&x)^z)
|
||||
movz x13, #0x821 // Load lower half of constant 0x49b40821
|
||||
movk x13, #0x49b4, lsl #16 // Load upper half of constant 0x49b40821
|
||||
add w9, w9, w27 // Add dest value
|
||||
add w9, w9, w13 // Add constant 0x49b40821
|
||||
add w9, w9, w6 // Add aux function result
|
||||
ror w9, w9, #10 // Rotate left s=22 bits
|
||||
bic x6, x8, x17 // Aux function round 2 (~z & y)
|
||||
add w9, w8, w9 // Add X parameter round 1 B=FF(B, C, D, A, 0x49b40821, s=22, M[15])
|
||||
movz x13, #0x2562 // Load lower half of constant 0xf61e2562
|
||||
movk x13, #0xf61e, lsl #16 // Load upper half of constant 0xf61e2562
|
||||
add w4, w4, w20 // Add dest value
|
||||
add w4, w4, w13 // Add constant 0xf61e2562
|
||||
and x13, x9, x17 // Aux function round 2 (x & z)
|
||||
add w4, w4, w6 // Add (~z & y)
|
||||
add w4, w4, w13 // Add (x & z)
|
||||
ror w4, w4, #27 // Rotate left s=5 bits
|
||||
bic x6, x9, x8 // Aux function round 2 (~z & y)
|
||||
add w4, w9, w4 // Add X parameter round 2 A=GG(A, B, C, D, 0xf61e2562, s=5, M[1])
|
||||
movz x13, #0xb340 // Load lower half of constant 0xc040b340
|
||||
movk x13, #0xc040, lsl #16 // Load upper half of constant 0xc040b340
|
||||
add w17, w17, w7 // Add dest value
|
||||
add w17, w17, w13 // Add constant 0xc040b340
|
||||
and x13, x4, x8 // Aux function round 2 (x & z)
|
||||
add w17, w17, w6 // Add (~z & y)
|
||||
add w17, w17, w13 // Add (x & z)
|
||||
ror w17, w17, #23 // Rotate left s=9 bits
|
||||
bic x6, x4, x9 // Aux function round 2 (~z & y)
|
||||
add w17, w4, w17 // Add X parameter round 2 D=GG(D, A, B, C, 0xc040b340, s=9, M[6])
|
||||
movz x13, #0x5a51 // Load lower half of constant 0x265e5a51
|
||||
movk x13, #0x265e, lsl #16 // Load upper half of constant 0x265e5a51
|
||||
add w8, w8, w25 // Add dest value
|
||||
add w8, w8, w13 // Add constant 0x265e5a51
|
||||
and x13, x17, x9 // Aux function round 2 (x & z)
|
||||
add w8, w8, w6 // Add (~z & y)
|
||||
add w8, w8, w13 // Add (x & z)
|
||||
ror w8, w8, #18 // Rotate left s=14 bits
|
||||
bic x6, x17, x4 // Aux function round 2 (~z & y)
|
||||
add w8, w17, w8 // Add X parameter round 2 C=GG(C, D, A, B, 0x265e5a51, s=14, M[11])
|
||||
movz x13, #0xc7aa // Load lower half of constant 0xe9b6c7aa
|
||||
movk x13, #0xe9b6, lsl #16 // Load upper half of constant 0xe9b6c7aa
|
||||
add w9, w9, w15 // Add dest value
|
||||
add w9, w9, w13 // Add constant 0xe9b6c7aa
|
||||
and x13, x8, x4 // Aux function round 2 (x & z)
|
||||
add w9, w9, w6 // Add (~z & y)
|
||||
add w9, w9, w13 // Add (x & z)
|
||||
ror w9, w9, #12 // Rotate left s=20 bits
|
||||
bic x6, x8, x17 // Aux function round 2 (~z & y)
|
||||
add w9, w8, w9 // Add X parameter round 2 B=GG(B, C, D, A, 0xe9b6c7aa, s=20, M[0])
|
||||
movz x13, #0x105d // Load lower half of constant 0xd62f105d
|
||||
movk x13, #0xd62f, lsl #16 // Load upper half of constant 0xd62f105d
|
||||
add w4, w4, w22 // Add dest value
|
||||
add w4, w4, w13 // Add constant 0xd62f105d
|
||||
and x13, x9, x17 // Aux function round 2 (x & z)
|
||||
add w4, w4, w6 // Add (~z & y)
|
||||
add w4, w4, w13 // Add (x & z)
|
||||
ror w4, w4, #27 // Rotate left s=5 bits
|
||||
bic x6, x9, x8 // Aux function round 2 (~z & y)
|
||||
add w4, w9, w4 // Add X parameter round 2 A=GG(A, B, C, D, 0xd62f105d, s=5, M[5])
|
||||
movz x13, #0x1453 // Load lower half of constant 0x2441453
|
||||
movk x13, #0x244, lsl #16 // Load upper half of constant 0x2441453
|
||||
add w17, w17, w16 // Add dest value
|
||||
add w17, w17, w13 // Add constant 0x2441453
|
||||
and x13, x4, x8 // Aux function round 2 (x & z)
|
||||
add w17, w17, w6 // Add (~z & y)
|
||||
add w17, w17, w13 // Add (x & z)
|
||||
ror w17, w17, #23 // Rotate left s=9 bits
|
||||
bic x6, x4, x9 // Aux function round 2 (~z & y)
|
||||
add w17, w4, w17 // Add X parameter round 2 D=GG(D, A, B, C, 0x2441453, s=9, M[10])
|
||||
movz x13, #0xe681 // Load lower half of constant 0xd8a1e681
|
||||
movk x13, #0xd8a1, lsl #16 // Load upper half of constant 0xd8a1e681
|
||||
add w8, w8, w27 // Add dest value
|
||||
add w8, w8, w13 // Add constant 0xd8a1e681
|
||||
and x13, x17, x9 // Aux function round 2 (x & z)
|
||||
add w8, w8, w6 // Add (~z & y)
|
||||
add w8, w8, w13 // Add (x & z)
|
||||
ror w8, w8, #18 // Rotate left s=14 bits
|
||||
bic x6, x17, x4 // Aux function round 2 (~z & y)
|
||||
add w8, w17, w8 // Add X parameter round 2 C=GG(C, D, A, B, 0xd8a1e681, s=14, M[15])
|
||||
movz x13, #0xfbc8 // Load lower half of constant 0xe7d3fbc8
|
||||
movk x13, #0xe7d3, lsl #16 // Load upper half of constant 0xe7d3fbc8
|
||||
add w9, w9, w14 // Add dest value
|
||||
add w9, w9, w13 // Add constant 0xe7d3fbc8
|
||||
and x13, x8, x4 // Aux function round 2 (x & z)
|
||||
add w9, w9, w6 // Add (~z & y)
|
||||
add w9, w9, w13 // Add (x & z)
|
||||
ror w9, w9, #12 // Rotate left s=20 bits
|
||||
bic x6, x8, x17 // Aux function round 2 (~z & y)
|
||||
add w9, w8, w9 // Add X parameter round 2 B=GG(B, C, D, A, 0xe7d3fbc8, s=20, M[4])
|
||||
movz x13, #0xcde6 // Load lower half of constant 0x21e1cde6
|
||||
movk x13, #0x21e1, lsl #16 // Load upper half of constant 0x21e1cde6
|
||||
add w4, w4, w24 // Add dest value
|
||||
add w4, w4, w13 // Add constant 0x21e1cde6
|
||||
and x13, x9, x17 // Aux function round 2 (x & z)
|
||||
add w4, w4, w6 // Add (~z & y)
|
||||
add w4, w4, w13 // Add (x & z)
|
||||
ror w4, w4, #27 // Rotate left s=5 bits
|
||||
bic x6, x9, x8 // Aux function round 2 (~z & y)
|
||||
add w4, w9, w4 // Add X parameter round 2 A=GG(A, B, C, D, 0x21e1cde6, s=5, M[9])
|
||||
movz x13, #0x7d6 // Load lower half of constant 0xc33707d6
|
||||
movk x13, #0xc337, lsl #16 // Load upper half of constant 0xc33707d6
|
||||
add w17, w17, w12 // Add dest value
|
||||
add w17, w17, w13 // Add constant 0xc33707d6
|
||||
and x13, x4, x8 // Aux function round 2 (x & z)
|
||||
add w17, w17, w6 // Add (~z & y)
|
||||
add w17, w17, w13 // Add (x & z)
|
||||
ror w17, w17, #23 // Rotate left s=9 bits
|
||||
bic x6, x4, x9 // Aux function round 2 (~z & y)
|
||||
add w17, w4, w17 // Add X parameter round 2 D=GG(D, A, B, C, 0xc33707d6, s=9, M[14])
|
||||
movz x13, #0xd87 // Load lower half of constant 0xf4d50d87
|
||||
movk x13, #0xf4d5, lsl #16 // Load upper half of constant 0xf4d50d87
|
||||
add w8, w8, w21 // Add dest value
|
||||
add w8, w8, w13 // Add constant 0xf4d50d87
|
||||
and x13, x17, x9 // Aux function round 2 (x & z)
|
||||
add w8, w8, w6 // Add (~z & y)
|
||||
add w8, w8, w13 // Add (x & z)
|
||||
ror w8, w8, #18 // Rotate left s=14 bits
|
||||
bic x6, x17, x4 // Aux function round 2 (~z & y)
|
||||
add w8, w17, w8 // Add X parameter round 2 C=GG(C, D, A, B, 0xf4d50d87, s=14, M[3])
|
||||
movz x13, #0x14ed // Load lower half of constant 0x455a14ed
|
||||
movk x13, #0x455a, lsl #16 // Load upper half of constant 0x455a14ed
|
||||
add w9, w9, w5 // Add dest value
|
||||
add w9, w9, w13 // Add constant 0x455a14ed
|
||||
and x13, x8, x4 // Aux function round 2 (x & z)
|
||||
add w9, w9, w6 // Add (~z & y)
|
||||
add w9, w9, w13 // Add (x & z)
|
||||
ror w9, w9, #12 // Rotate left s=20 bits
|
||||
bic x6, x8, x17 // Aux function round 2 (~z & y)
|
||||
add w9, w8, w9 // Add X parameter round 2 B=GG(B, C, D, A, 0x455a14ed, s=20, M[8])
|
||||
movz x13, #0xe905 // Load lower half of constant 0xa9e3e905
|
||||
movk x13, #0xa9e3, lsl #16 // Load upper half of constant 0xa9e3e905
|
||||
add w4, w4, w26 // Add dest value
|
||||
add w4, w4, w13 // Add constant 0xa9e3e905
|
||||
and x13, x9, x17 // Aux function round 2 (x & z)
|
||||
add w4, w4, w6 // Add (~z & y)
|
||||
add w4, w4, w13 // Add (x & z)
|
||||
ror w4, w4, #27 // Rotate left s=5 bits
|
||||
bic x6, x9, x8 // Aux function round 2 (~z & y)
|
||||
add w4, w9, w4 // Add X parameter round 2 A=GG(A, B, C, D, 0xa9e3e905, s=5, M[13])
|
||||
movz x13, #0xa3f8 // Load lower half of constant 0xfcefa3f8
|
||||
movk x13, #0xfcef, lsl #16 // Load upper half of constant 0xfcefa3f8
|
||||
add w17, w17, w3 // Add dest value
|
||||
add w17, w17, w13 // Add constant 0xfcefa3f8
|
||||
and x13, x4, x8 // Aux function round 2 (x & z)
|
||||
add w17, w17, w6 // Add (~z & y)
|
||||
add w17, w17, w13 // Add (x & z)
|
||||
ror w17, w17, #23 // Rotate left s=9 bits
|
||||
bic x6, x4, x9 // Aux function round 2 (~z & y)
|
||||
add w17, w4, w17 // Add X parameter round 2 D=GG(D, A, B, C, 0xfcefa3f8, s=9, M[2])
|
||||
movz x13, #0x2d9 // Load lower half of constant 0x676f02d9
|
||||
movk x13, #0x676f, lsl #16 // Load upper half of constant 0x676f02d9
|
||||
add w8, w8, w23 // Add dest value
|
||||
add w8, w8, w13 // Add constant 0x676f02d9
|
||||
and x13, x17, x9 // Aux function round 2 (x & z)
|
||||
add w8, w8, w6 // Add (~z & y)
|
||||
add w8, w8, w13 // Add (x & z)
|
||||
ror w8, w8, #18 // Rotate left s=14 bits
|
||||
bic x6, x17, x4 // Aux function round 2 (~z & y)
|
||||
add w8, w17, w8 // Add X parameter round 2 C=GG(C, D, A, B, 0x676f02d9, s=14, M[7])
|
||||
movz x13, #0x4c8a // Load lower half of constant 0x8d2a4c8a
|
||||
movk x13, #0x8d2a, lsl #16 // Load upper half of constant 0x8d2a4c8a
|
||||
add w9, w9, w11 // Add dest value
|
||||
add w9, w9, w13 // Add constant 0x8d2a4c8a
|
||||
and x13, x8, x4 // Aux function round 2 (x & z)
|
||||
add w9, w9, w6 // Add (~z & y)
|
||||
add w9, w9, w13 // Add (x & z)
|
||||
eor x6, x8, x17 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
ror w9, w9, #12 // Rotate left s=20 bits
|
||||
movz x10, #0x3942 // Load lower half of constant 0xfffa3942
|
||||
add w9, w8, w9 // Add X parameter round 2 B=GG(B, C, D, A, 0x8d2a4c8a, s=20, M[12])
|
||||
movk x10, #0xfffa, lsl #16 // Load upper half of constant 0xfffa3942
|
||||
add w4, w4, w22 // Add dest value
|
||||
eor x6, x6, x9 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w4, w4, w10 // Add constant 0xfffa3942
|
||||
add w4, w4, w6 // Add aux function result
|
||||
ror w4, w4, #28 // Rotate left s=4 bits
|
||||
eor x6, x9, x8 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
movz x10, #0xf681 // Load lower half of constant 0x8771f681
|
||||
add w4, w9, w4 // Add X parameter round 3 A=HH(A, B, C, D, 0xfffa3942, s=4, M[5])
|
||||
movk x10, #0x8771, lsl #16 // Load upper half of constant 0x8771f681
|
||||
add w17, w17, w5 // Add dest value
|
||||
eor x6, x6, x4 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w17, w17, w10 // Add constant 0x8771f681
|
||||
add w17, w17, w6 // Add aux function result
|
||||
eor x6, x4, x9 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
ror w17, w17, #21 // Rotate left s=11 bits
|
||||
movz x13, #0x6122 // Load lower half of constant 0x6d9d6122
|
||||
add w17, w4, w17 // Add X parameter round 3 D=HH(D, A, B, C, 0x8771f681, s=11, M[8])
|
||||
movk x13, #0x6d9d, lsl #16 // Load upper half of constant 0x6d9d6122
|
||||
add w8, w8, w25 // Add dest value
|
||||
eor x6, x6, x17 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w8, w8, w13 // Add constant 0x6d9d6122
|
||||
add w8, w8, w6 // Add aux function result
|
||||
ror w8, w8, #16 // Rotate left s=16 bits
|
||||
eor x6, x17, x4 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
movz x13, #0x380c // Load lower half of constant 0xfde5380c
|
||||
add w8, w17, w8 // Add X parameter round 3 C=HH(C, D, A, B, 0x6d9d6122, s=16, M[11])
|
||||
movk x13, #0xfde5, lsl #16 // Load upper half of constant 0xfde5380c
|
||||
add w9, w9, w12 // Add dest value
|
||||
eor x6, x6, x8 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w9, w9, w13 // Add constant 0xfde5380c
|
||||
add w9, w9, w6 // Add aux function result
|
||||
eor x6, x8, x17 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
ror w9, w9, #9 // Rotate left s=23 bits
|
||||
movz x10, #0xea44 // Load lower half of constant 0xa4beea44
|
||||
add w9, w8, w9 // Add X parameter round 3 B=HH(B, C, D, A, 0xfde5380c, s=23, M[14])
|
||||
movk x10, #0xa4be, lsl #16 // Load upper half of constant 0xa4beea44
|
||||
add w4, w4, w20 // Add dest value
|
||||
eor x6, x6, x9 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w4, w4, w10 // Add constant 0xa4beea44
|
||||
add w4, w4, w6 // Add aux function result
|
||||
ror w4, w4, #28 // Rotate left s=4 bits
|
||||
eor x6, x9, x8 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
movz x10, #0xcfa9 // Load lower half of constant 0x4bdecfa9
|
||||
add w4, w9, w4 // Add X parameter round 3 A=HH(A, B, C, D, 0xa4beea44, s=4, M[1])
|
||||
movk x10, #0x4bde, lsl #16 // Load upper half of constant 0x4bdecfa9
|
||||
add w17, w17, w14 // Add dest value
|
||||
eor x6, x6, x4 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w17, w17, w10 // Add constant 0x4bdecfa9
|
||||
add w17, w17, w6 // Add aux function result
|
||||
eor x6, x4, x9 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
ror w17, w17, #21 // Rotate left s=11 bits
|
||||
movz x13, #0x4b60 // Load lower half of constant 0xf6bb4b60
|
||||
add w17, w4, w17 // Add X parameter round 3 D=HH(D, A, B, C, 0x4bdecfa9, s=11, M[4])
|
||||
movk x13, #0xf6bb, lsl #16 // Load upper half of constant 0xf6bb4b60
|
||||
add w8, w8, w23 // Add dest value
|
||||
eor x6, x6, x17 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w8, w8, w13 // Add constant 0xf6bb4b60
|
||||
add w8, w8, w6 // Add aux function result
|
||||
ror w8, w8, #16 // Rotate left s=16 bits
|
||||
eor x6, x17, x4 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
movz x13, #0xbc70 // Load lower half of constant 0xbebfbc70
|
||||
add w8, w17, w8 // Add X parameter round 3 C=HH(C, D, A, B, 0xf6bb4b60, s=16, M[7])
|
||||
movk x13, #0xbebf, lsl #16 // Load upper half of constant 0xbebfbc70
|
||||
add w9, w9, w16 // Add dest value
|
||||
eor x6, x6, x8 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w9, w9, w13 // Add constant 0xbebfbc70
|
||||
add w9, w9, w6 // Add aux function result
|
||||
eor x6, x8, x17 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
ror w9, w9, #9 // Rotate left s=23 bits
|
||||
movz x10, #0x7ec6 // Load lower half of constant 0x289b7ec6
|
||||
add w9, w8, w9 // Add X parameter round 3 B=HH(B, C, D, A, 0xbebfbc70, s=23, M[10])
|
||||
movk x10, #0x289b, lsl #16 // Load upper half of constant 0x289b7ec6
|
||||
add w4, w4, w26 // Add dest value
|
||||
eor x6, x6, x9 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w4, w4, w10 // Add constant 0x289b7ec6
|
||||
add w4, w4, w6 // Add aux function result
|
||||
ror w4, w4, #28 // Rotate left s=4 bits
|
||||
eor x6, x9, x8 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
movz x10, #0x27fa // Load lower half of constant 0xeaa127fa
|
||||
add w4, w9, w4 // Add X parameter round 3 A=HH(A, B, C, D, 0x289b7ec6, s=4, M[13])
|
||||
movk x10, #0xeaa1, lsl #16 // Load upper half of constant 0xeaa127fa
|
||||
add w17, w17, w15 // Add dest value
|
||||
eor x6, x6, x4 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w17, w17, w10 // Add constant 0xeaa127fa
|
||||
add w17, w17, w6 // Add aux function result
|
||||
eor x6, x4, x9 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
ror w17, w17, #21 // Rotate left s=11 bits
|
||||
movz x13, #0x3085 // Load lower half of constant 0xd4ef3085
|
||||
add w17, w4, w17 // Add X parameter round 3 D=HH(D, A, B, C, 0xeaa127fa, s=11, M[0])
|
||||
movk x13, #0xd4ef, lsl #16 // Load upper half of constant 0xd4ef3085
|
||||
add w8, w8, w21 // Add dest value
|
||||
eor x6, x6, x17 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w8, w8, w13 // Add constant 0xd4ef3085
|
||||
add w8, w8, w6 // Add aux function result
|
||||
ror w8, w8, #16 // Rotate left s=16 bits
|
||||
eor x6, x17, x4 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
movz x13, #0x1d05 // Load lower half of constant 0x4881d05
|
||||
add w8, w17, w8 // Add X parameter round 3 C=HH(C, D, A, B, 0xd4ef3085, s=16, M[3])
|
||||
movk x13, #0x488, lsl #16 // Load upper half of constant 0x4881d05
|
||||
add w9, w9, w7 // Add dest value
|
||||
eor x6, x6, x8 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w9, w9, w13 // Add constant 0x4881d05
|
||||
add w9, w9, w6 // Add aux function result
|
||||
eor x6, x8, x17 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
ror w9, w9, #9 // Rotate left s=23 bits
|
||||
movz x10, #0xd039 // Load lower half of constant 0xd9d4d039
|
||||
add w9, w8, w9 // Add X parameter round 3 B=HH(B, C, D, A, 0x4881d05, s=23, M[6])
|
||||
movk x10, #0xd9d4, lsl #16 // Load upper half of constant 0xd9d4d039
|
||||
add w4, w4, w24 // Add dest value
|
||||
eor x6, x6, x9 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w4, w4, w10 // Add constant 0xd9d4d039
|
||||
add w4, w4, w6 // Add aux function result
|
||||
ror w4, w4, #28 // Rotate left s=4 bits
|
||||
eor x6, x9, x8 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
movz x10, #0x99e5 // Load lower half of constant 0xe6db99e5
|
||||
add w4, w9, w4 // Add X parameter round 3 A=HH(A, B, C, D, 0xd9d4d039, s=4, M[9])
|
||||
movk x10, #0xe6db, lsl #16 // Load upper half of constant 0xe6db99e5
|
||||
add w17, w17, w11 // Add dest value
|
||||
eor x6, x6, x4 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w17, w17, w10 // Add constant 0xe6db99e5
|
||||
add w17, w17, w6 // Add aux function result
|
||||
eor x6, x4, x9 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
ror w17, w17, #21 // Rotate left s=11 bits
|
||||
movz x13, #0x7cf8 // Load lower half of constant 0x1fa27cf8
|
||||
add w17, w4, w17 // Add X parameter round 3 D=HH(D, A, B, C, 0xe6db99e5, s=11, M[12])
|
||||
movk x13, #0x1fa2, lsl #16 // Load upper half of constant 0x1fa27cf8
|
||||
add w8, w8, w27 // Add dest value
|
||||
eor x6, x6, x17 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w8, w8, w13 // Add constant 0x1fa27cf8
|
||||
add w8, w8, w6 // Add aux function result
|
||||
ror w8, w8, #16 // Rotate left s=16 bits
|
||||
eor x6, x17, x4 // Begin aux function round 3 H(x,y,z)=(x^y^z)
|
||||
movz x13, #0x5665 // Load lower half of constant 0xc4ac5665
|
||||
add w8, w17, w8 // Add X parameter round 3 C=HH(C, D, A, B, 0x1fa27cf8, s=16, M[15])
|
||||
movk x13, #0xc4ac, lsl #16 // Load upper half of constant 0xc4ac5665
|
||||
add w9, w9, w3 // Add dest value
|
||||
eor x6, x6, x8 // End aux function round 3 H(x,y,z)=(x^y^z)
|
||||
add w9, w9, w13 // Add constant 0xc4ac5665
|
||||
add w9, w9, w6 // Add aux function result
|
||||
ror w9, w9, #9 // Rotate left s=23 bits
|
||||
movz x6, #0x2244 // Load lower half of constant 0xf4292244
|
||||
movk x6, #0xf429, lsl #16 // Load upper half of constant 0xf4292244
|
||||
add w9, w8, w9 // Add X parameter round 3 B=HH(B, C, D, A, 0xc4ac5665, s=23, M[2])
|
||||
add w4, w4, w15 // Add dest value
|
||||
orn x13, x9, x17 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w4, w4, w6 // Add constant 0xf4292244
|
||||
eor x6, x8, x13 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w4, w4, w6 // Add aux function result
|
||||
ror w4, w4, #26 // Rotate left s=6 bits
|
||||
movz x6, #0xff97 // Load lower half of constant 0x432aff97
|
||||
movk x6, #0x432a, lsl #16 // Load upper half of constant 0x432aff97
|
||||
add w4, w9, w4 // Add X parameter round 4 A=II(A, B, C, D, 0xf4292244, s=6, M[0])
|
||||
orn x10, x4, x8 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w17, w17, w23 // Add dest value
|
||||
eor x10, x9, x10 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w17, w17, w6 // Add constant 0x432aff97
|
||||
add w6, w17, w10 // Add aux function result
|
||||
ror w6, w6, #22 // Rotate left s=10 bits
|
||||
movz x17, #0x23a7 // Load lower half of constant 0xab9423a7
|
||||
movk x17, #0xab94, lsl #16 // Load upper half of constant 0xab9423a7
|
||||
add w6, w4, w6 // Add X parameter round 4 D=II(D, A, B, C, 0x432aff97, s=10, M[7])
|
||||
add w8, w8, w12 // Add dest value
|
||||
orn x10, x6, x9 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w8, w8, w17 // Add constant 0xab9423a7
|
||||
eor x17, x4, x10 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w8, w8, w17 // Add aux function result
|
||||
ror w8, w8, #17 // Rotate left s=15 bits
|
||||
movz x17, #0xa039 // Load lower half of constant 0xfc93a039
|
||||
movk x17, #0xfc93, lsl #16 // Load upper half of constant 0xfc93a039
|
||||
add w8, w6, w8 // Add X parameter round 4 C=II(C, D, A, B, 0xab9423a7, s=15, M[14])
|
||||
orn x13, x8, x4 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w9, w9, w22 // Add dest value
|
||||
eor x13, x6, x13 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w9, w9, w17 // Add constant 0xfc93a039
|
||||
add w17, w9, w13 // Add aux function result
|
||||
ror w17, w17, #11 // Rotate left s=21 bits
|
||||
movz x9, #0x59c3 // Load lower half of constant 0x655b59c3
|
||||
movk x9, #0x655b, lsl #16 // Load upper half of constant 0x655b59c3
|
||||
add w17, w8, w17 // Add X parameter round 4 B=II(B, C, D, A, 0xfc93a039, s=21, M[5])
|
||||
add w4, w4, w11 // Add dest value
|
||||
orn x13, x17, x6 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w9, w4, w9 // Add constant 0x655b59c3
|
||||
eor x4, x8, x13 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w9, w9, w4 // Add aux function result
|
||||
ror w9, w9, #26 // Rotate left s=6 bits
|
||||
movz x4, #0xcc92 // Load lower half of constant 0x8f0ccc92
|
||||
movk x4, #0x8f0c, lsl #16 // Load upper half of constant 0x8f0ccc92
|
||||
add w9, w17, w9 // Add X parameter round 4 A=II(A, B, C, D, 0x655b59c3, s=6, M[12])
|
||||
orn x10, x9, x8 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w6, w6, w21 // Add dest value
|
||||
eor x10, x17, x10 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w4, w6, w4 // Add constant 0x8f0ccc92
|
||||
add w6, w4, w10 // Add aux function result
|
||||
ror w6, w6, #22 // Rotate left s=10 bits
|
||||
movz x4, #0xf47d // Load lower half of constant 0xffeff47d
|
||||
movk x4, #0xffef, lsl #16 // Load upper half of constant 0xffeff47d
|
||||
add w6, w9, w6 // Add X parameter round 4 D=II(D, A, B, C, 0x8f0ccc92, s=10, M[3])
|
||||
add w8, w8, w16 // Add dest value
|
||||
orn x10, x6, x17 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w8, w8, w4 // Add constant 0xffeff47d
|
||||
eor x4, x9, x10 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w8, w8, w4 // Add aux function result
|
||||
ror w8, w8, #17 // Rotate left s=15 bits
|
||||
movz x4, #0x5dd1 // Load lower half of constant 0x85845dd1
|
||||
movk x4, #0x8584, lsl #16 // Load upper half of constant 0x85845dd1
|
||||
add w8, w6, w8 // Add X parameter round 4 C=II(C, D, A, B, 0xffeff47d, s=15, M[10])
|
||||
orn x10, x8, x9 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w15, w17, w20 // Add dest value
|
||||
eor x17, x6, x10 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w15, w15, w4 // Add constant 0x85845dd1
|
||||
add w4, w15, w17 // Add aux function result
|
||||
ror w4, w4, #11 // Rotate left s=21 bits
|
||||
movz x15, #0x7e4f // Load lower half of constant 0x6fa87e4f
|
||||
movk x15, #0x6fa8, lsl #16 // Load upper half of constant 0x6fa87e4f
|
||||
add w17, w8, w4 // Add X parameter round 4 B=II(B, C, D, A, 0x85845dd1, s=21, M[1])
|
||||
add w4, w9, w5 // Add dest value
|
||||
orn x9, x17, x6 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w15, w4, w15 // Add constant 0x6fa87e4f
|
||||
eor x4, x8, x9 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w9, w15, w4 // Add aux function result
|
||||
ror w9, w9, #26 // Rotate left s=6 bits
|
||||
movz x15, #0xe6e0 // Load lower half of constant 0xfe2ce6e0
|
||||
movk x15, #0xfe2c, lsl #16 // Load upper half of constant 0xfe2ce6e0
|
||||
add w4, w17, w9 // Add X parameter round 4 A=II(A, B, C, D, 0x6fa87e4f, s=6, M[8])
|
||||
orn x9, x4, x8 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w6, w6, w27 // Add dest value
|
||||
eor x9, x17, x9 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w15, w6, w15 // Add constant 0xfe2ce6e0
|
||||
add w6, w15, w9 // Add aux function result
|
||||
ror w6, w6, #22 // Rotate left s=10 bits
|
||||
movz x9, #0x4314 // Load lower half of constant 0xa3014314
|
||||
movk x9, #0xa301, lsl #16 // Load upper half of constant 0xa3014314
|
||||
add w15, w4, w6 // Add X parameter round 4 D=II(D, A, B, C, 0xfe2ce6e0, s=10, M[15])
|
||||
add w6, w8, w7 // Add dest value
|
||||
orn x7, x15, x17 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w8, w6, w9 // Add constant 0xa3014314
|
||||
eor x9, x4, x7 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w6, w8, w9 // Add aux function result
|
||||
ror w6, w6, #17 // Rotate left s=15 bits
|
||||
movz x7, #0x11a1 // Load lower half of constant 0x4e0811a1
|
||||
movk x7, #0x4e08, lsl #16 // Load upper half of constant 0x4e0811a1
|
||||
add w8, w15, w6 // Add X parameter round 4 C=II(C, D, A, B, 0xa3014314, s=15, M[6])
|
||||
orn x9, x8, x4 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w6, w17, w26 // Add dest value
|
||||
eor x17, x15, x9 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w9, w6, w7 // Add constant 0x4e0811a1
|
||||
add w7, w9, w17 // Add aux function result
|
||||
ror w7, w7, #11 // Rotate left s=21 bits
|
||||
movz x6, #0x7e82 // Load lower half of constant 0xf7537e82
|
||||
movk x6, #0xf753, lsl #16 // Load upper half of constant 0xf7537e82
|
||||
add w9, w8, w7 // Add X parameter round 4 B=II(B, C, D, A, 0x4e0811a1, s=21, M[13])
|
||||
add w17, w4, w14 // Add dest value
|
||||
orn x7, x9, x15 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w14, w17, w6 // Add constant 0xf7537e82
|
||||
eor x4, x8, x7 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w17, w14, w4 // Add aux function result
|
||||
ror w17, w17, #26 // Rotate left s=6 bits
|
||||
movz x6, #0xf235 // Load lower half of constant 0xbd3af235
|
||||
movk x6, #0xbd3a, lsl #16 // Load upper half of constant 0xbd3af235
|
||||
add w7, w9, w17 // Add X parameter round 4 A=II(A, B, C, D, 0xf7537e82, s=6, M[4])
|
||||
orn x14, x7, x8 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w4, w15, w25 // Add dest value
|
||||
eor x17, x9, x14 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w15, w4, w6 // Add constant 0xbd3af235
|
||||
add w16, w15, w17 // Add aux function result
|
||||
ror w16, w16, #22 // Rotate left s=10 bits
|
||||
movz x14, #0xd2bb // Load lower half of constant 0x2ad7d2bb
|
||||
movk x14, #0x2ad7, lsl #16 // Load upper half of constant 0x2ad7d2bb
|
||||
add w4, w7, w16 // Add X parameter round 4 D=II(D, A, B, C, 0xbd3af235, s=10, M[11])
|
||||
add w6, w8, w3 // Add dest value
|
||||
orn x15, x4, x9 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w17, w6, w14 // Add constant 0x2ad7d2bb
|
||||
eor x16, x7, x15 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w8, w17, w16 // Add aux function result
|
||||
ror w8, w8, #17 // Rotate left s=15 bits
|
||||
movz x3, #0xd391 // Load lower half of constant 0xeb86d391
|
||||
movk x3, #0xeb86, lsl #16 // Load upper half of constant 0xeb86d391
|
||||
add w14, w4, w8 // Add X parameter round 4 C=II(C, D, A, B, 0x2ad7d2bb, s=15, M[2])
|
||||
orn x6, x14, x7 // Begin aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w15, w9, w24 // Add dest value
|
||||
eor x17, x4, x6 // End aux function round 4 I(x,y,z)=((~z|x)^y)
|
||||
add w16, w15, w3 // Add constant 0xeb86d391
|
||||
add w8, w16, w17 // Add aux function result
|
||||
ror w8, w8, #11 // Rotate left s=21 bits
|
||||
ldp w6, w15, [x0] // Reload MD5 state->A and state->B
|
||||
ldp w5, w9, [x0, #8] // Reload MD5 state->C and state->D
|
||||
add w3, w14, w8 // Add X parameter round 4 B=II(B, C, D, A, 0xeb86d391, s=21, M[9])
|
||||
add w13, w4, w9 // Add result of MD5 rounds to state->D
|
||||
add w12, w14, w5 // Add result of MD5 rounds to state->C
|
||||
add w10, w7, w6 // Add result of MD5 rounds to state->A
|
||||
add w11, w3, w15 // Add result of MD5 rounds to state->B
|
||||
stp w12, w13, [x0, #8] // Store MD5 states C,D
|
||||
stp w10, w11, [x0] // Store MD5 states A,B
|
||||
add x1, x1, #64 // Increment data pointer
|
||||
subs w2, w2, #1 // Decrement block counter
|
||||
b.ne ossl_md5_blocks_loop
|
||||
|
||||
ldp x21,x22,[sp,#16]
|
||||
ldp x23,x24,[sp,#32]
|
||||
ldp x25,x26,[sp,#48]
|
||||
ldp x27,x28,[sp,#64]
|
||||
ldp x19,x20,[sp],#80
|
||||
ret
|
||||
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,652 @@
|
|||
#include "arm_arch.h"
|
||||
|
||||
#if __ARM_MAX_ARCH__>=7
|
||||
.arch armv8-a+crypto
|
||||
.text
|
||||
.globl gcm_init_v8
|
||||
.def gcm_init_v8
|
||||
.type 32
|
||||
.endef
|
||||
.align 4
|
||||
gcm_init_v8:
|
||||
AARCH64_VALID_CALL_TARGET
|
||||
ld1 {v17.2d},[x1] //load input H
|
||||
movi v19.16b,#0xe1
|
||||
shl v19.2d,v19.2d,#57 //0xc2.0
|
||||
ext v3.16b,v17.16b,v17.16b,#8
|
||||
ushr v18.2d,v19.2d,#63
|
||||
dup v17.4s,v17.s[1]
|
||||
ext v16.16b,v18.16b,v19.16b,#8 //t0=0xc2....01
|
||||
ushr v18.2d,v3.2d,#63
|
||||
sshr v17.4s,v17.4s,#31 //broadcast carry bit
|
||||
and v18.16b,v18.16b,v16.16b
|
||||
shl v3.2d,v3.2d,#1
|
||||
ext v18.16b,v18.16b,v18.16b,#8
|
||||
and v16.16b,v16.16b,v17.16b
|
||||
orr v3.16b,v3.16b,v18.16b //H<<<=1
|
||||
eor v20.16b,v3.16b,v16.16b //twisted H
|
||||
st1 {v20.2d},[x0],#16 //store Htable[0]
|
||||
|
||||
//calculate H^2
|
||||
ext v16.16b,v20.16b,v20.16b,#8 //Karatsuba pre-processing
|
||||
pmull v0.1q,v20.1d,v20.1d
|
||||
eor v16.16b,v16.16b,v20.16b
|
||||
pmull2 v2.1q,v20.2d,v20.2d
|
||||
pmull v1.1q,v16.1d,v16.1d
|
||||
|
||||
ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
|
||||
eor v18.16b,v0.16b,v2.16b
|
||||
eor v1.16b,v1.16b,v17.16b
|
||||
eor v1.16b,v1.16b,v18.16b
|
||||
pmull v18.1q,v0.1d,v19.1d //1st phase
|
||||
|
||||
ins v2.d[0],v1.d[1]
|
||||
ins v1.d[1],v0.d[0]
|
||||
eor v0.16b,v1.16b,v18.16b
|
||||
|
||||
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase
|
||||
pmull v0.1q,v0.1d,v19.1d
|
||||
eor v18.16b,v18.16b,v2.16b
|
||||
eor v22.16b,v0.16b,v18.16b
|
||||
|
||||
ext v17.16b,v22.16b,v22.16b,#8 //Karatsuba pre-processing
|
||||
eor v17.16b,v17.16b,v22.16b
|
||||
ext v21.16b,v16.16b,v17.16b,#8 //pack Karatsuba pre-processed
|
||||
st1 {v21.2d,v22.2d},[x0],#32 //store Htable[1..2]
|
||||
//calculate H^3 and H^4
|
||||
pmull v0.1q,v20.1d, v22.1d
|
||||
pmull v5.1q,v22.1d,v22.1d
|
||||
pmull2 v2.1q,v20.2d, v22.2d
|
||||
pmull2 v7.1q,v22.2d,v22.2d
|
||||
pmull v1.1q,v16.1d,v17.1d
|
||||
pmull v6.1q,v17.1d,v17.1d
|
||||
|
||||
ext v16.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
|
||||
ext v17.16b,v5.16b,v7.16b,#8
|
||||
eor v18.16b,v0.16b,v2.16b
|
||||
eor v1.16b,v1.16b,v16.16b
|
||||
eor v4.16b,v5.16b,v7.16b
|
||||
eor v6.16b,v6.16b,v17.16b
|
||||
eor v1.16b,v1.16b,v18.16b
|
||||
pmull v18.1q,v0.1d,v19.1d //1st phase
|
||||
eor v6.16b,v6.16b,v4.16b
|
||||
pmull v4.1q,v5.1d,v19.1d
|
||||
|
||||
ins v2.d[0],v1.d[1]
|
||||
ins v7.d[0],v6.d[1]
|
||||
ins v1.d[1],v0.d[0]
|
||||
ins v6.d[1],v5.d[0]
|
||||
eor v0.16b,v1.16b,v18.16b
|
||||
eor v5.16b,v6.16b,v4.16b
|
||||
|
||||
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase
|
||||
ext v4.16b,v5.16b,v5.16b,#8
|
||||
pmull v0.1q,v0.1d,v19.1d
|
||||
pmull v5.1q,v5.1d,v19.1d
|
||||
eor v18.16b,v18.16b,v2.16b
|
||||
eor v4.16b,v4.16b,v7.16b
|
||||
eor v23.16b, v0.16b,v18.16b //H^3
|
||||
eor v25.16b,v5.16b,v4.16b //H^4
|
||||
|
||||
ext v16.16b,v23.16b, v23.16b,#8 //Karatsuba pre-processing
|
||||
ext v17.16b,v25.16b,v25.16b,#8
|
||||
ext v18.16b,v22.16b,v22.16b,#8
|
||||
eor v16.16b,v16.16b,v23.16b
|
||||
eor v17.16b,v17.16b,v25.16b
|
||||
eor v18.16b,v18.16b,v22.16b
|
||||
ext v24.16b,v16.16b,v17.16b,#8 //pack Karatsuba pre-processed
|
||||
st1 {v23.2d,v24.2d,v25.2d},[x0],#48 //store Htable[3..5]
|
||||
|
||||
//calculate H^5 and H^6
|
||||
pmull v0.1q,v22.1d, v23.1d
|
||||
pmull v5.1q,v23.1d,v23.1d
|
||||
pmull2 v2.1q,v22.2d, v23.2d
|
||||
pmull2 v7.1q,v23.2d,v23.2d
|
||||
pmull v1.1q,v16.1d,v18.1d
|
||||
pmull v6.1q,v16.1d,v16.1d
|
||||
|
||||
ext v16.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
|
||||
ext v17.16b,v5.16b,v7.16b,#8
|
||||
eor v18.16b,v0.16b,v2.16b
|
||||
eor v1.16b,v1.16b,v16.16b
|
||||
eor v4.16b,v5.16b,v7.16b
|
||||
eor v6.16b,v6.16b,v17.16b
|
||||
eor v1.16b,v1.16b,v18.16b
|
||||
pmull v18.1q,v0.1d,v19.1d //1st phase
|
||||
eor v6.16b,v6.16b,v4.16b
|
||||
pmull v4.1q,v5.1d,v19.1d
|
||||
|
||||
ins v2.d[0],v1.d[1]
|
||||
ins v7.d[0],v6.d[1]
|
||||
ins v1.d[1],v0.d[0]
|
||||
ins v6.d[1],v5.d[0]
|
||||
eor v0.16b,v1.16b,v18.16b
|
||||
eor v5.16b,v6.16b,v4.16b
|
||||
|
||||
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase
|
||||
ext v4.16b,v5.16b,v5.16b,#8
|
||||
pmull v0.1q,v0.1d,v19.1d
|
||||
pmull v5.1q,v5.1d,v19.1d
|
||||
eor v18.16b,v18.16b,v2.16b
|
||||
eor v4.16b,v4.16b,v7.16b
|
||||
eor v26.16b,v0.16b,v18.16b //H^5
|
||||
eor v28.16b,v5.16b,v4.16b //H^6
|
||||
|
||||
ext v16.16b,v26.16b, v26.16b,#8 //Karatsuba pre-processing
|
||||
ext v17.16b,v28.16b,v28.16b,#8
|
||||
ext v18.16b,v22.16b,v22.16b,#8
|
||||
eor v16.16b,v16.16b,v26.16b
|
||||
eor v17.16b,v17.16b,v28.16b
|
||||
eor v18.16b,v18.16b,v22.16b
|
||||
ext v27.16b,v16.16b,v17.16b,#8 //pack Karatsuba pre-processed
|
||||
st1 {v26.2d,v27.2d,v28.2d},[x0],#48 //store Htable[6..8]
|
||||
|
||||
//calculate H^7 and H^8
|
||||
pmull v0.1q,v22.1d,v26.1d
|
||||
pmull v5.1q,v22.1d,v28.1d
|
||||
pmull2 v2.1q,v22.2d,v26.2d
|
||||
pmull2 v7.1q,v22.2d,v28.2d
|
||||
pmull v1.1q,v16.1d,v18.1d
|
||||
pmull v6.1q,v17.1d,v18.1d
|
||||
|
||||
ext v16.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
|
||||
ext v17.16b,v5.16b,v7.16b,#8
|
||||
eor v18.16b,v0.16b,v2.16b
|
||||
eor v1.16b,v1.16b,v16.16b
|
||||
eor v4.16b,v5.16b,v7.16b
|
||||
eor v6.16b,v6.16b,v17.16b
|
||||
eor v1.16b,v1.16b,v18.16b
|
||||
pmull v18.1q,v0.1d,v19.1d //1st phase
|
||||
eor v6.16b,v6.16b,v4.16b
|
||||
pmull v4.1q,v5.1d,v19.1d
|
||||
|
||||
ins v2.d[0],v1.d[1]
|
||||
ins v7.d[0],v6.d[1]
|
||||
ins v1.d[1],v0.d[0]
|
||||
ins v6.d[1],v5.d[0]
|
||||
eor v0.16b,v1.16b,v18.16b
|
||||
eor v5.16b,v6.16b,v4.16b
|
||||
|
||||
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase
|
||||
ext v4.16b,v5.16b,v5.16b,#8
|
||||
pmull v0.1q,v0.1d,v19.1d
|
||||
pmull v5.1q,v5.1d,v19.1d
|
||||
eor v18.16b,v18.16b,v2.16b
|
||||
eor v4.16b,v4.16b,v7.16b
|
||||
eor v29.16b,v0.16b,v18.16b //H^7
|
||||
eor v31.16b,v5.16b,v4.16b //H^8
|
||||
|
||||
ext v16.16b,v29.16b,v29.16b,#8 //Karatsuba pre-processing
|
||||
ext v17.16b,v31.16b,v31.16b,#8
|
||||
eor v16.16b,v16.16b,v29.16b
|
||||
eor v17.16b,v17.16b,v31.16b
|
||||
ext v30.16b,v16.16b,v17.16b,#8 //pack Karatsuba pre-processed
|
||||
st1 {v29.2d,v30.2d,v31.2d},[x0] //store Htable[9..11]
|
||||
ret
|
||||
|
||||
.globl gcm_gmult_v8
|
||||
.def gcm_gmult_v8
|
||||
.type 32
|
||||
.endef
|
||||
.align 4
|
||||
gcm_gmult_v8:
|
||||
AARCH64_VALID_CALL_TARGET
|
||||
ld1 {v17.2d},[x0] //load Xi
|
||||
movi v19.16b,#0xe1
|
||||
ld1 {v20.2d,v21.2d},[x1] //load twisted H, ...
|
||||
shl v19.2d,v19.2d,#57
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v17.16b,v17.16b
|
||||
#endif
|
||||
ext v3.16b,v17.16b,v17.16b,#8
|
||||
|
||||
pmull v0.1q,v20.1d,v3.1d //H.lo·Xi.lo
|
||||
eor v17.16b,v17.16b,v3.16b //Karatsuba pre-processing
|
||||
pmull2 v2.1q,v20.2d,v3.2d //H.hi·Xi.hi
|
||||
pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)·(Xi.lo+Xi.hi)
|
||||
|
||||
ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
|
||||
eor v18.16b,v0.16b,v2.16b
|
||||
eor v1.16b,v1.16b,v17.16b
|
||||
eor v1.16b,v1.16b,v18.16b
|
||||
pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
|
||||
|
||||
ins v2.d[0],v1.d[1]
|
||||
ins v1.d[1],v0.d[0]
|
||||
eor v0.16b,v1.16b,v18.16b
|
||||
|
||||
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
|
||||
pmull v0.1q,v0.1d,v19.1d
|
||||
eor v18.16b,v18.16b,v2.16b
|
||||
eor v0.16b,v0.16b,v18.16b
|
||||
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v0.16b,v0.16b
|
||||
#endif
|
||||
ext v0.16b,v0.16b,v0.16b,#8
|
||||
st1 {v0.2d},[x0] //write out Xi
|
||||
|
||||
ret
|
||||
|
||||
.globl gcm_ghash_v8
|
||||
.def gcm_ghash_v8
|
||||
.type 32
|
||||
.endef
|
||||
.align 4
|
||||
gcm_ghash_v8:
|
||||
AARCH64_VALID_CALL_TARGET
|
||||
cmp x3,#64
|
||||
b.hs Lgcm_ghash_v8_4x
|
||||
ld1 {v0.2d},[x0] //load [rotated] Xi
|
||||
//"[rotated]" means that
|
||||
//loaded value would have
|
||||
//to be rotated in order to
|
||||
//make it appear as in
|
||||
//algorithm specification
|
||||
subs x3,x3,#32 //see if x3 is 32 or larger
|
||||
mov x12,#16 //x12 is used as post-
|
||||
//increment for input pointer;
|
||||
//as loop is modulo-scheduled
|
||||
//x12 is zeroed just in time
|
||||
//to preclude overstepping
|
||||
//inp[len], which means that
|
||||
//last block[s] are actually
|
||||
//loaded twice, but last
|
||||
//copy is not processed
|
||||
ld1 {v20.2d,v21.2d},[x1],#32 //load twisted H, ..., H^2
|
||||
movi v19.16b,#0xe1
|
||||
ld1 {v22.2d},[x1]
|
||||
csel x12,xzr,x12,eq //is it time to zero x12?
|
||||
ext v0.16b,v0.16b,v0.16b,#8 //rotate Xi
|
||||
ld1 {v16.2d},[x2],#16 //load [rotated] I[0]
|
||||
shl v19.2d,v19.2d,#57 //compose 0xc2.0 constant
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v16.16b,v16.16b
|
||||
rev64 v0.16b,v0.16b
|
||||
#endif
|
||||
ext v3.16b,v16.16b,v16.16b,#8 //rotate I[0]
|
||||
b.lo Lodd_tail_v8 //x3 was less than 32
|
||||
ld1 {v17.2d},[x2],x12 //load [rotated] I[1]
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v17.16b,v17.16b
|
||||
#endif
|
||||
ext v7.16b,v17.16b,v17.16b,#8
|
||||
eor v3.16b,v3.16b,v0.16b //I[i]^=Xi
|
||||
pmull v4.1q,v20.1d,v7.1d //H·Ii+1
|
||||
eor v17.16b,v17.16b,v7.16b //Karatsuba pre-processing
|
||||
pmull2 v6.1q,v20.2d,v7.2d
|
||||
b Loop_mod2x_v8
|
||||
|
||||
.align 4
|
||||
Loop_mod2x_v8:
|
||||
ext v18.16b,v3.16b,v3.16b,#8
|
||||
subs x3,x3,#32 //is there more data?
|
||||
pmull v0.1q,v22.1d,v3.1d //H^2.lo·Xi.lo
|
||||
csel x12,xzr,x12,lo //is it time to zero x12?
|
||||
|
||||
pmull v5.1q,v21.1d,v17.1d
|
||||
eor v18.16b,v18.16b,v3.16b //Karatsuba pre-processing
|
||||
pmull2 v2.1q,v22.2d,v3.2d //H^2.hi·Xi.hi
|
||||
eor v0.16b,v0.16b,v4.16b //accumulate
|
||||
pmull2 v1.1q,v21.2d,v18.2d //(H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
|
||||
ld1 {v16.2d},[x2],x12 //load [rotated] I[i+2]
|
||||
|
||||
eor v2.16b,v2.16b,v6.16b
|
||||
csel x12,xzr,x12,eq //is it time to zero x12?
|
||||
eor v1.16b,v1.16b,v5.16b
|
||||
|
||||
ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
|
||||
eor v18.16b,v0.16b,v2.16b
|
||||
eor v1.16b,v1.16b,v17.16b
|
||||
ld1 {v17.2d},[x2],x12 //load [rotated] I[i+3]
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v16.16b,v16.16b
|
||||
#endif
|
||||
eor v1.16b,v1.16b,v18.16b
|
||||
pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
|
||||
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v17.16b,v17.16b
|
||||
#endif
|
||||
ins v2.d[0],v1.d[1]
|
||||
ins v1.d[1],v0.d[0]
|
||||
ext v7.16b,v17.16b,v17.16b,#8
|
||||
ext v3.16b,v16.16b,v16.16b,#8
|
||||
eor v0.16b,v1.16b,v18.16b
|
||||
pmull v4.1q,v20.1d,v7.1d //H·Ii+1
|
||||
eor v3.16b,v3.16b,v2.16b //accumulate v3.16b early
|
||||
|
||||
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
|
||||
pmull v0.1q,v0.1d,v19.1d
|
||||
eor v3.16b,v3.16b,v18.16b
|
||||
eor v17.16b,v17.16b,v7.16b //Karatsuba pre-processing
|
||||
eor v3.16b,v3.16b,v0.16b
|
||||
pmull2 v6.1q,v20.2d,v7.2d
|
||||
b.hs Loop_mod2x_v8 //there was at least 32 more bytes
|
||||
|
||||
eor v2.16b,v2.16b,v18.16b
|
||||
ext v3.16b,v16.16b,v16.16b,#8 //re-construct v3.16b
|
||||
adds x3,x3,#32 //re-construct x3
|
||||
eor v0.16b,v0.16b,v2.16b //re-construct v0.16b
|
||||
b.eq Ldone_v8 //is x3 zero?
|
||||
Lodd_tail_v8:
|
||||
ext v18.16b,v0.16b,v0.16b,#8
|
||||
eor v3.16b,v3.16b,v0.16b //inp^=Xi
|
||||
eor v17.16b,v16.16b,v18.16b //v17.16b is rotated inp^Xi
|
||||
|
||||
pmull v0.1q,v20.1d,v3.1d //H.lo·Xi.lo
|
||||
eor v17.16b,v17.16b,v3.16b //Karatsuba pre-processing
|
||||
pmull2 v2.1q,v20.2d,v3.2d //H.hi·Xi.hi
|
||||
pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)·(Xi.lo+Xi.hi)
|
||||
|
||||
ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
|
||||
eor v18.16b,v0.16b,v2.16b
|
||||
eor v1.16b,v1.16b,v17.16b
|
||||
eor v1.16b,v1.16b,v18.16b
|
||||
pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
|
||||
|
||||
ins v2.d[0],v1.d[1]
|
||||
ins v1.d[1],v0.d[0]
|
||||
eor v0.16b,v1.16b,v18.16b
|
||||
|
||||
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
|
||||
pmull v0.1q,v0.1d,v19.1d
|
||||
eor v18.16b,v18.16b,v2.16b
|
||||
eor v0.16b,v0.16b,v18.16b
|
||||
|
||||
Ldone_v8:
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v0.16b,v0.16b
|
||||
#endif
|
||||
ext v0.16b,v0.16b,v0.16b,#8
|
||||
st1 {v0.2d},[x0] //write out Xi
|
||||
|
||||
ret
|
||||
|
||||
.def gcm_ghash_v8_4x
|
||||
.type 32
|
||||
.endef
|
||||
.align 4
|
||||
gcm_ghash_v8_4x:
|
||||
Lgcm_ghash_v8_4x:
|
||||
ld1 {v0.2d},[x0] //load [rotated] Xi
|
||||
ld1 {v20.2d,v21.2d,v22.2d},[x1],#48 //load twisted H, ..., H^2
|
||||
movi v19.16b,#0xe1
|
||||
ld1 {v26.2d,v27.2d,v28.2d},[x1] //load twisted H^3, ..., H^4
|
||||
shl v19.2d,v19.2d,#57 //compose 0xc2.0 constant
|
||||
|
||||
ld1 {v4.2d,v5.2d,v6.2d,v7.2d},[x2],#64
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v0.16b,v0.16b
|
||||
rev64 v5.16b,v5.16b
|
||||
rev64 v6.16b,v6.16b
|
||||
rev64 v7.16b,v7.16b
|
||||
rev64 v4.16b,v4.16b
|
||||
#endif
|
||||
ext v25.16b,v7.16b,v7.16b,#8
|
||||
ext v24.16b,v6.16b,v6.16b,#8
|
||||
ext v23.16b,v5.16b,v5.16b,#8
|
||||
|
||||
pmull v29.1q,v20.1d,v25.1d //H·Ii+3
|
||||
eor v7.16b,v7.16b,v25.16b
|
||||
pmull2 v31.1q,v20.2d,v25.2d
|
||||
pmull v30.1q,v21.1d,v7.1d
|
||||
|
||||
pmull v16.1q,v22.1d,v24.1d //H^2·Ii+2
|
||||
eor v6.16b,v6.16b,v24.16b
|
||||
pmull2 v24.1q,v22.2d,v24.2d
|
||||
pmull2 v6.1q,v21.2d,v6.2d
|
||||
|
||||
eor v29.16b,v29.16b,v16.16b
|
||||
eor v31.16b,v31.16b,v24.16b
|
||||
eor v30.16b,v30.16b,v6.16b
|
||||
|
||||
pmull v7.1q,v26.1d,v23.1d //H^3·Ii+1
|
||||
eor v5.16b,v5.16b,v23.16b
|
||||
pmull2 v23.1q,v26.2d,v23.2d
|
||||
pmull v5.1q,v27.1d,v5.1d
|
||||
|
||||
eor v29.16b,v29.16b,v7.16b
|
||||
eor v31.16b,v31.16b,v23.16b
|
||||
eor v30.16b,v30.16b,v5.16b
|
||||
|
||||
subs x3,x3,#128
|
||||
b.lo Ltail4x
|
||||
|
||||
b Loop4x
|
||||
|
||||
.align 4
|
||||
Loop4x:
|
||||
eor v16.16b,v4.16b,v0.16b
|
||||
ld1 {v4.2d,v5.2d,v6.2d,v7.2d},[x2],#64
|
||||
ext v3.16b,v16.16b,v16.16b,#8
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v5.16b,v5.16b
|
||||
rev64 v6.16b,v6.16b
|
||||
rev64 v7.16b,v7.16b
|
||||
rev64 v4.16b,v4.16b
|
||||
#endif
|
||||
|
||||
pmull v0.1q,v28.1d,v3.1d //H^4·(Xi+Ii)
|
||||
eor v16.16b,v16.16b,v3.16b
|
||||
pmull2 v2.1q,v28.2d,v3.2d
|
||||
ext v25.16b,v7.16b,v7.16b,#8
|
||||
pmull2 v1.1q,v27.2d,v16.2d
|
||||
|
||||
eor v0.16b,v0.16b,v29.16b
|
||||
eor v2.16b,v2.16b,v31.16b
|
||||
ext v24.16b,v6.16b,v6.16b,#8
|
||||
eor v1.16b,v1.16b,v30.16b
|
||||
ext v23.16b,v5.16b,v5.16b,#8
|
||||
|
||||
ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
|
||||
eor v18.16b,v0.16b,v2.16b
|
||||
pmull v29.1q,v20.1d,v25.1d //H·Ii+3
|
||||
eor v7.16b,v7.16b,v25.16b
|
||||
eor v1.16b,v1.16b,v17.16b
|
||||
pmull2 v31.1q,v20.2d,v25.2d
|
||||
eor v1.16b,v1.16b,v18.16b
|
||||
pmull v30.1q,v21.1d,v7.1d
|
||||
|
||||
pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
|
||||
ins v2.d[0],v1.d[1]
|
||||
ins v1.d[1],v0.d[0]
|
||||
pmull v16.1q,v22.1d,v24.1d //H^2·Ii+2
|
||||
eor v6.16b,v6.16b,v24.16b
|
||||
pmull2 v24.1q,v22.2d,v24.2d
|
||||
eor v0.16b,v1.16b,v18.16b
|
||||
pmull2 v6.1q,v21.2d,v6.2d
|
||||
|
||||
eor v29.16b,v29.16b,v16.16b
|
||||
eor v31.16b,v31.16b,v24.16b
|
||||
eor v30.16b,v30.16b,v6.16b
|
||||
|
||||
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
|
||||
pmull v0.1q,v0.1d,v19.1d
|
||||
pmull v7.1q,v26.1d,v23.1d //H^3·Ii+1
|
||||
eor v5.16b,v5.16b,v23.16b
|
||||
eor v18.16b,v18.16b,v2.16b
|
||||
pmull2 v23.1q,v26.2d,v23.2d
|
||||
pmull v5.1q,v27.1d,v5.1d
|
||||
|
||||
eor v0.16b,v0.16b,v18.16b
|
||||
eor v29.16b,v29.16b,v7.16b
|
||||
eor v31.16b,v31.16b,v23.16b
|
||||
ext v0.16b,v0.16b,v0.16b,#8
|
||||
eor v30.16b,v30.16b,v5.16b
|
||||
|
||||
subs x3,x3,#64
|
||||
b.hs Loop4x
|
||||
|
||||
Ltail4x:
|
||||
eor v16.16b,v4.16b,v0.16b
|
||||
ext v3.16b,v16.16b,v16.16b,#8
|
||||
|
||||
pmull v0.1q,v28.1d,v3.1d //H^4·(Xi+Ii)
|
||||
eor v16.16b,v16.16b,v3.16b
|
||||
pmull2 v2.1q,v28.2d,v3.2d
|
||||
pmull2 v1.1q,v27.2d,v16.2d
|
||||
|
||||
eor v0.16b,v0.16b,v29.16b
|
||||
eor v2.16b,v2.16b,v31.16b
|
||||
eor v1.16b,v1.16b,v30.16b
|
||||
|
||||
adds x3,x3,#64
|
||||
b.eq Ldone4x
|
||||
|
||||
cmp x3,#32
|
||||
b.lo Lone
|
||||
b.eq Ltwo
|
||||
Lthree:
|
||||
ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
|
||||
eor v18.16b,v0.16b,v2.16b
|
||||
eor v1.16b,v1.16b,v17.16b
|
||||
ld1 {v4.2d,v5.2d,v6.2d},[x2]
|
||||
eor v1.16b,v1.16b,v18.16b
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v5.16b,v5.16b
|
||||
rev64 v6.16b,v6.16b
|
||||
rev64 v4.16b,v4.16b
|
||||
#endif
|
||||
|
||||
pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
|
||||
ins v2.d[0],v1.d[1]
|
||||
ins v1.d[1],v0.d[0]
|
||||
ext v24.16b,v6.16b,v6.16b,#8
|
||||
ext v23.16b,v5.16b,v5.16b,#8
|
||||
eor v0.16b,v1.16b,v18.16b
|
||||
|
||||
pmull v29.1q,v20.1d,v24.1d //H·Ii+2
|
||||
eor v6.16b,v6.16b,v24.16b
|
||||
|
||||
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
|
||||
pmull v0.1q,v0.1d,v19.1d
|
||||
eor v18.16b,v18.16b,v2.16b
|
||||
pmull2 v31.1q,v20.2d,v24.2d
|
||||
pmull v30.1q,v21.1d,v6.1d
|
||||
eor v0.16b,v0.16b,v18.16b
|
||||
pmull v7.1q,v22.1d,v23.1d //H^2·Ii+1
|
||||
eor v5.16b,v5.16b,v23.16b
|
||||
ext v0.16b,v0.16b,v0.16b,#8
|
||||
|
||||
pmull2 v23.1q,v22.2d,v23.2d
|
||||
eor v16.16b,v4.16b,v0.16b
|
||||
pmull2 v5.1q,v21.2d,v5.2d
|
||||
ext v3.16b,v16.16b,v16.16b,#8
|
||||
|
||||
eor v29.16b,v29.16b,v7.16b
|
||||
eor v31.16b,v31.16b,v23.16b
|
||||
eor v30.16b,v30.16b,v5.16b
|
||||
|
||||
pmull v0.1q,v26.1d,v3.1d //H^3·(Xi+Ii)
|
||||
eor v16.16b,v16.16b,v3.16b
|
||||
pmull2 v2.1q,v26.2d,v3.2d
|
||||
pmull v1.1q,v27.1d,v16.1d
|
||||
|
||||
eor v0.16b,v0.16b,v29.16b
|
||||
eor v2.16b,v2.16b,v31.16b
|
||||
eor v1.16b,v1.16b,v30.16b
|
||||
b Ldone4x
|
||||
|
||||
.align 4
|
||||
Ltwo:
|
||||
ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
|
||||
eor v18.16b,v0.16b,v2.16b
|
||||
eor v1.16b,v1.16b,v17.16b
|
||||
ld1 {v4.2d,v5.2d},[x2]
|
||||
eor v1.16b,v1.16b,v18.16b
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v5.16b,v5.16b
|
||||
rev64 v4.16b,v4.16b
|
||||
#endif
|
||||
|
||||
pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
|
||||
ins v2.d[0],v1.d[1]
|
||||
ins v1.d[1],v0.d[0]
|
||||
ext v23.16b,v5.16b,v5.16b,#8
|
||||
eor v0.16b,v1.16b,v18.16b
|
||||
|
||||
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
|
||||
pmull v0.1q,v0.1d,v19.1d
|
||||
eor v18.16b,v18.16b,v2.16b
|
||||
eor v0.16b,v0.16b,v18.16b
|
||||
ext v0.16b,v0.16b,v0.16b,#8
|
||||
|
||||
pmull v29.1q,v20.1d,v23.1d //H·Ii+1
|
||||
eor v5.16b,v5.16b,v23.16b
|
||||
|
||||
eor v16.16b,v4.16b,v0.16b
|
||||
ext v3.16b,v16.16b,v16.16b,#8
|
||||
|
||||
pmull2 v31.1q,v20.2d,v23.2d
|
||||
pmull v30.1q,v21.1d,v5.1d
|
||||
|
||||
pmull v0.1q,v22.1d,v3.1d //H^2·(Xi+Ii)
|
||||
eor v16.16b,v16.16b,v3.16b
|
||||
pmull2 v2.1q,v22.2d,v3.2d
|
||||
pmull2 v1.1q,v21.2d,v16.2d
|
||||
|
||||
eor v0.16b,v0.16b,v29.16b
|
||||
eor v2.16b,v2.16b,v31.16b
|
||||
eor v1.16b,v1.16b,v30.16b
|
||||
b Ldone4x
|
||||
|
||||
.align 4
|
||||
Lone:
|
||||
ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
|
||||
eor v18.16b,v0.16b,v2.16b
|
||||
eor v1.16b,v1.16b,v17.16b
|
||||
ld1 {v4.2d},[x2]
|
||||
eor v1.16b,v1.16b,v18.16b
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v4.16b,v4.16b
|
||||
#endif
|
||||
|
||||
pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
|
||||
ins v2.d[0],v1.d[1]
|
||||
ins v1.d[1],v0.d[0]
|
||||
eor v0.16b,v1.16b,v18.16b
|
||||
|
||||
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
|
||||
pmull v0.1q,v0.1d,v19.1d
|
||||
eor v18.16b,v18.16b,v2.16b
|
||||
eor v0.16b,v0.16b,v18.16b
|
||||
ext v0.16b,v0.16b,v0.16b,#8
|
||||
|
||||
eor v16.16b,v4.16b,v0.16b
|
||||
ext v3.16b,v16.16b,v16.16b,#8
|
||||
|
||||
pmull v0.1q,v20.1d,v3.1d
|
||||
eor v16.16b,v16.16b,v3.16b
|
||||
pmull2 v2.1q,v20.2d,v3.2d
|
||||
pmull v1.1q,v21.1d,v16.1d
|
||||
|
||||
Ldone4x:
|
||||
ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
|
||||
eor v18.16b,v0.16b,v2.16b
|
||||
eor v1.16b,v1.16b,v17.16b
|
||||
eor v1.16b,v1.16b,v18.16b
|
||||
|
||||
pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
|
||||
ins v2.d[0],v1.d[1]
|
||||
ins v1.d[1],v0.d[0]
|
||||
eor v0.16b,v1.16b,v18.16b
|
||||
|
||||
ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
|
||||
pmull v0.1q,v0.1d,v19.1d
|
||||
eor v18.16b,v18.16b,v2.16b
|
||||
eor v0.16b,v0.16b,v18.16b
|
||||
ext v0.16b,v0.16b,v0.16b,#8
|
||||
|
||||
#ifndef __AARCH64EB__
|
||||
rev64 v0.16b,v0.16b
|
||||
#endif
|
||||
st1 {v0.2d},[x0] //write out Xi
|
||||
|
||||
ret
|
||||
|
||||
.section .rodata
|
||||
.byte 71,72,65,83,72,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
||||
.align 2
|
||||
.align 2
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,507 @@
|
|||
// Copyright 2021-2025 The OpenSSL Project Authors. All Rights Reserved.
|
||||
//
|
||||
// Licensed under the Apache License 2.0 (the "License"). You may not use
|
||||
// this file except in compliance with the License. You can obtain a copy
|
||||
// in the file LICENSE in the source distribution or at
|
||||
// https://www.openssl.org/source/license.html
|
||||
//
|
||||
// This module implements support for Armv8 SM3 instructions
|
||||
|
||||
// $output is the last argument if it looks like a file (it has an extension)
|
||||
// $flavour is the first argument if it doesn't look like a file
|
||||
#include "arm_arch.h"
|
||||
.text
|
||||
.globl ossl_hwsm3_block_data_order
|
||||
.def ossl_hwsm3_block_data_order
|
||||
.type 32
|
||||
.endef
|
||||
.align 5
|
||||
ossl_hwsm3_block_data_order:
|
||||
AARCH64_VALID_CALL_TARGET
|
||||
// load state
|
||||
ld1 {v5.4s,v6.4s}, [x0]
|
||||
rev64 v5.4s, v5.4s
|
||||
rev64 v6.4s, v6.4s
|
||||
ext v5.16b, v5.16b, v5.16b, #8
|
||||
ext v6.16b, v6.16b, v6.16b, #8
|
||||
adr x8, .Tj
|
||||
ldp s16, s17, [x8]
|
||||
|
||||
Loop:
|
||||
// load input
|
||||
ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x1], #64
|
||||
sub w2, w2, #1
|
||||
|
||||
mov v18.16b, v5.16b
|
||||
mov v19.16b, v6.16b
|
||||
|
||||
#ifndef __AARCH64EB__
|
||||
rev32 v0.16b, v0.16b
|
||||
rev32 v1.16b, v1.16b
|
||||
rev32 v2.16b, v2.16b
|
||||
rev32 v3.16b, v3.16b
|
||||
#endif
|
||||
|
||||
ext v20.16b, v16.16b, v16.16b, #4
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v4.16b, v1.16b, v2.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v0.16b, v1.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v2.16b, v3.16b, #8
|
||||
.long 0xce63c004 //sm3partw1 v4.4s, v0.4s, v3.4s
|
||||
.long 0xce76c6e4 //sm3partw2 v4.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v0.16b, v1.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5682e5 //sm3tt1a v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce408ae6 //sm3tt2a v6.4s, v23.4s, v0.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5692e5 //sm3tt1a v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce409ae6 //sm3tt2a v6.4s, v23.4s, v0.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a2e5 //sm3tt1a v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce40aae6 //sm3tt2a v6.4s, v23.4s, v0.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b2e5 //sm3tt1a v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce40bae6 //sm3tt2a v6.4s, v23.4s, v0.4s[3]
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v0.16b, v2.16b, v3.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v1.16b, v2.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v3.16b, v4.16b, #8
|
||||
.long 0xce64c020 //sm3partw1 v0.4s, v1.4s, v4.4s
|
||||
.long 0xce76c6e0 //sm3partw2 v0.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v1.16b, v2.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5682e5 //sm3tt1a v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce418ae6 //sm3tt2a v6.4s, v23.4s, v1.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5692e5 //sm3tt1a v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce419ae6 //sm3tt2a v6.4s, v23.4s, v1.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a2e5 //sm3tt1a v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce41aae6 //sm3tt2a v6.4s, v23.4s, v1.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b2e5 //sm3tt1a v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce41bae6 //sm3tt2a v6.4s, v23.4s, v1.4s[3]
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v1.16b, v3.16b, v4.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v2.16b, v3.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v4.16b, v0.16b, #8
|
||||
.long 0xce60c041 //sm3partw1 v1.4s, v2.4s, v0.4s
|
||||
.long 0xce76c6e1 //sm3partw2 v1.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v2.16b, v3.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5682e5 //sm3tt1a v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce428ae6 //sm3tt2a v6.4s, v23.4s, v2.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5692e5 //sm3tt1a v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce429ae6 //sm3tt2a v6.4s, v23.4s, v2.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a2e5 //sm3tt1a v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce42aae6 //sm3tt2a v6.4s, v23.4s, v2.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b2e5 //sm3tt1a v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce42bae6 //sm3tt2a v6.4s, v23.4s, v2.4s[3]
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v2.16b, v4.16b, v0.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v3.16b, v4.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v0.16b, v1.16b, #8
|
||||
.long 0xce61c062 //sm3partw1 v2.4s, v3.4s, v1.4s
|
||||
.long 0xce76c6e2 //sm3partw2 v2.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v3.16b, v4.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5682e5 //sm3tt1a v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce438ae6 //sm3tt2a v6.4s, v23.4s, v3.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5692e5 //sm3tt1a v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce439ae6 //sm3tt2a v6.4s, v23.4s, v3.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a2e5 //sm3tt1a v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce43aae6 //sm3tt2a v6.4s, v23.4s, v3.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b2e5 //sm3tt1a v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce43bae6 //sm3tt2a v6.4s, v23.4s, v3.4s[3]
|
||||
ext v20.16b, v17.16b, v17.16b, #4
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v3.16b, v0.16b, v1.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v4.16b, v0.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v1.16b, v2.16b, #8
|
||||
.long 0xce62c083 //sm3partw1 v3.4s, v4.4s, v2.4s
|
||||
.long 0xce76c6e3 //sm3partw2 v3.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v4.16b, v0.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5686e5 //sm3tt1b v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce448ee6 //sm3tt2b v6.4s, v23.4s, v4.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5696e5 //sm3tt1b v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce449ee6 //sm3tt2b v6.4s, v23.4s, v4.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce44aee6 //sm3tt2b v6.4s, v23.4s, v4.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce44bee6 //sm3tt2b v6.4s, v23.4s, v4.4s[3]
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v4.16b, v1.16b, v2.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v0.16b, v1.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v2.16b, v3.16b, #8
|
||||
.long 0xce63c004 //sm3partw1 v4.4s, v0.4s, v3.4s
|
||||
.long 0xce76c6e4 //sm3partw2 v4.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v0.16b, v1.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5686e5 //sm3tt1b v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce408ee6 //sm3tt2b v6.4s, v23.4s, v0.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5696e5 //sm3tt1b v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce409ee6 //sm3tt2b v6.4s, v23.4s, v0.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce40aee6 //sm3tt2b v6.4s, v23.4s, v0.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce40bee6 //sm3tt2b v6.4s, v23.4s, v0.4s[3]
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v0.16b, v2.16b, v3.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v1.16b, v2.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v3.16b, v4.16b, #8
|
||||
.long 0xce64c020 //sm3partw1 v0.4s, v1.4s, v4.4s
|
||||
.long 0xce76c6e0 //sm3partw2 v0.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v1.16b, v2.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5686e5 //sm3tt1b v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce418ee6 //sm3tt2b v6.4s, v23.4s, v1.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5696e5 //sm3tt1b v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce419ee6 //sm3tt2b v6.4s, v23.4s, v1.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce41aee6 //sm3tt2b v6.4s, v23.4s, v1.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce41bee6 //sm3tt2b v6.4s, v23.4s, v1.4s[3]
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v1.16b, v3.16b, v4.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v2.16b, v3.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v4.16b, v0.16b, #8
|
||||
.long 0xce60c041 //sm3partw1 v1.4s, v2.4s, v0.4s
|
||||
.long 0xce76c6e1 //sm3partw2 v1.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v2.16b, v3.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5686e5 //sm3tt1b v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce428ee6 //sm3tt2b v6.4s, v23.4s, v2.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5696e5 //sm3tt1b v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce429ee6 //sm3tt2b v6.4s, v23.4s, v2.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce42aee6 //sm3tt2b v6.4s, v23.4s, v2.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce42bee6 //sm3tt2b v6.4s, v23.4s, v2.4s[3]
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v2.16b, v4.16b, v0.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v3.16b, v4.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v0.16b, v1.16b, #8
|
||||
.long 0xce61c062 //sm3partw1 v2.4s, v3.4s, v1.4s
|
||||
.long 0xce76c6e2 //sm3partw2 v2.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v3.16b, v4.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5686e5 //sm3tt1b v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce438ee6 //sm3tt2b v6.4s, v23.4s, v3.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5696e5 //sm3tt1b v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce439ee6 //sm3tt2b v6.4s, v23.4s, v3.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce43aee6 //sm3tt2b v6.4s, v23.4s, v3.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce43bee6 //sm3tt2b v6.4s, v23.4s, v3.4s[3]
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v3.16b, v0.16b, v1.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v4.16b, v0.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v1.16b, v2.16b, #8
|
||||
.long 0xce62c083 //sm3partw1 v3.4s, v4.4s, v2.4s
|
||||
.long 0xce76c6e3 //sm3partw2 v3.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v4.16b, v0.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5686e5 //sm3tt1b v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce448ee6 //sm3tt2b v6.4s, v23.4s, v4.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5696e5 //sm3tt1b v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce449ee6 //sm3tt2b v6.4s, v23.4s, v4.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce44aee6 //sm3tt2b v6.4s, v23.4s, v4.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce44bee6 //sm3tt2b v6.4s, v23.4s, v4.4s[3]
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v4.16b, v1.16b, v2.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v0.16b, v1.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v2.16b, v3.16b, #8
|
||||
.long 0xce63c004 //sm3partw1 v4.4s, v0.4s, v3.4s
|
||||
.long 0xce76c6e4 //sm3partw2 v4.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v0.16b, v1.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5686e5 //sm3tt1b v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce408ee6 //sm3tt2b v6.4s, v23.4s, v0.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5696e5 //sm3tt1b v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce409ee6 //sm3tt2b v6.4s, v23.4s, v0.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce40aee6 //sm3tt2b v6.4s, v23.4s, v0.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce40bee6 //sm3tt2b v6.4s, v23.4s, v0.4s[3]
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v0.16b, v2.16b, v3.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v1.16b, v2.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v3.16b, v4.16b, #8
|
||||
.long 0xce64c020 //sm3partw1 v0.4s, v1.4s, v4.4s
|
||||
.long 0xce76c6e0 //sm3partw2 v0.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v1.16b, v2.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5686e5 //sm3tt1b v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce418ee6 //sm3tt2b v6.4s, v23.4s, v1.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5696e5 //sm3tt1b v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce419ee6 //sm3tt2b v6.4s, v23.4s, v1.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce41aee6 //sm3tt2b v6.4s, v23.4s, v1.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce41bee6 //sm3tt2b v6.4s, v23.4s, v1.4s[3]
|
||||
// s4 = w7 | w8 | w9 | w10
|
||||
ext v1.16b, v3.16b, v4.16b, #12
|
||||
// vtmp1 = w3 | w4 | w5 | w6
|
||||
ext v22.16b, v2.16b, v3.16b, #12
|
||||
// vtmp2 = w10 | w11 | w12 | w13
|
||||
ext v23.16b, v4.16b, v0.16b, #8
|
||||
.long 0xce60c041 //sm3partw1 v1.4s, v2.4s, v0.4s
|
||||
.long 0xce76c6e1 //sm3partw2 v1.4s, v23.4s, v22.4s
|
||||
eor v22.16b, v2.16b, v3.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5686e5 //sm3tt1b v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce428ee6 //sm3tt2b v6.4s, v23.4s, v2.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5696e5 //sm3tt1b v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce429ee6 //sm3tt2b v6.4s, v23.4s, v2.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce42aee6 //sm3tt2b v6.4s, v23.4s, v2.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce42bee6 //sm3tt2b v6.4s, v23.4s, v2.4s[3]
|
||||
eor v22.16b, v3.16b, v4.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5686e5 //sm3tt1b v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce438ee6 //sm3tt2b v6.4s, v23.4s, v3.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5696e5 //sm3tt1b v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce439ee6 //sm3tt2b v6.4s, v23.4s, v3.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce43aee6 //sm3tt2b v6.4s, v23.4s, v3.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce43bee6 //sm3tt2b v6.4s, v23.4s, v3.4s[3]
|
||||
eor v22.16b, v4.16b, v0.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5686e5 //sm3tt1b v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce448ee6 //sm3tt2b v6.4s, v23.4s, v4.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5696e5 //sm3tt1b v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce449ee6 //sm3tt2b v6.4s, v23.4s, v4.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce44aee6 //sm3tt2b v6.4s, v23.4s, v4.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce44bee6 //sm3tt2b v6.4s, v23.4s, v4.4s[3]
|
||||
eor v22.16b, v0.16b, v1.16b
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce5686e5 //sm3tt1b v5.4s, v23.4s, v22.4s[0]
|
||||
.long 0xce408ee6 //sm3tt2b v6.4s, v23.4s, v0.4s[0]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce5696e5 //sm3tt1b v5.4s, v23.4s, v22.4s[1]
|
||||
.long 0xce409ee6 //sm3tt2b v6.4s, v23.4s, v0.4s[1]
|
||||
.long 0xce5418b7 //sm3ss1 v23.4s, v5.4s, v20.4s, v6.4s
|
||||
shl v21.4s, v20.4s, #1
|
||||
sri v21.4s, v20.4s, #31
|
||||
.long 0xce56a6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[2]
|
||||
.long 0xce40aee6 //sm3tt2b v6.4s, v23.4s, v0.4s[2]
|
||||
.long 0xce5518b7 //sm3ss1 v23.4s, v5.4s, v21.4s, v6.4s
|
||||
shl v20.4s, v21.4s, #1
|
||||
sri v20.4s, v21.4s, #31
|
||||
.long 0xce56b6e5 //sm3tt1b v5.4s, v23.4s, v22.4s[3]
|
||||
.long 0xce40bee6 //sm3tt2b v6.4s, v23.4s, v0.4s[3]
|
||||
eor v5.16b, v5.16b, v18.16b
|
||||
eor v6.16b, v6.16b, v19.16b
|
||||
|
||||
// any remained blocks?
|
||||
cbnz w2, Loop
|
||||
|
||||
// save state
|
||||
rev64 v5.4s, v5.4s
|
||||
rev64 v6.4s, v6.4s
|
||||
ext v5.16b, v5.16b, v5.16b, #8
|
||||
ext v6.16b, v6.16b, v6.16b, #8
|
||||
st1 {v5.4s,v6.4s}, [x0]
|
||||
ret
|
||||
|
||||
|
||||
|
||||
.align 3
|
||||
_sm3_consts:
|
||||
.Tj:
|
||||
.word 0x79cc4519, 0x9d8a7a87
|
||||
|
||||
|
|
@ -2159,19 +2159,32 @@
|
|||
$(OPENSSL_PATH)/ssl/statem/statem_clnt.c
|
||||
$(OPENSSL_PATH)/ssl/statem/statem_dtls.c
|
||||
$(OPENSSL_PATH)/ssl/statem/statem_lib.c
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/aes/aesv8-armx.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/aes/bsaes-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/aes/vpaes-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/arm64cpuid.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/md5/md5-aarch64.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/modes/aes-gcm-armv8-unroll8_64.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/modes/aes-gcm-armv8_64.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/modes/ghashv8-armx.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/keccak1600-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/sha1-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/sha256-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/sha512-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sm3/sm3-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/aes/aesv8-armx.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/aes/bsaes-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/aes/vpaes-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/arm64cpuid.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/md5/md5-aarch64.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/modes/aes-gcm-armv8-unroll8_64.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/modes/aes-gcm-armv8_64.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/modes/ghashv8-armx.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/sha/keccak1600-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/sha/sha1-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/sha/sha256-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/sha/sha512-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/sm3/sm3-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/aes/aesv8-armx.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/aes/bsaes-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/aes/vpaes-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/arm64cpuid.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/md5/md5-aarch64.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/modes/aes-gcm-armv8-unroll8_64.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/modes/aes-gcm-armv8_64.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/modes/ghashv8-armx.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/sha/keccak1600-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/sha/sha1-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/sha/sha256-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/sha/sha512-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/sm3/sm3-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
# Autogenerated files list ends here
|
||||
|
||||
[Packages]
|
||||
|
|
@ -2186,6 +2199,9 @@
|
|||
[FeaturePcd.IA32, FeaturePcd.X64]
|
||||
gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStyleNasm
|
||||
|
||||
[FeaturePcd.AARCH64]
|
||||
gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
|
||||
[BuildOptions]
|
||||
#
|
||||
# Disables the following Visual Studio compiler warnings brought by openssl source,
|
||||
|
|
|
|||
|
|
@ -2320,19 +2320,32 @@
|
|||
$(OPENSSL_PATH)/ssl/statem/statem_clnt.c
|
||||
$(OPENSSL_PATH)/ssl/statem/statem_dtls.c
|
||||
$(OPENSSL_PATH)/ssl/statem/statem_lib.c
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/aes/aesv8-armx.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/aes/bsaes-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/aes/vpaes-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/arm64cpuid.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/md5/md5-aarch64.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/modes/aes-gcm-armv8-unroll8_64.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/modes/aes-gcm-armv8_64.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/modes/ghashv8-armx.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/keccak1600-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/sha1-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/sha256-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/sha512-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sm3/sm3-armv8.S | GCC
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/aes/aesv8-armx.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/aes/bsaes-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/aes/vpaes-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/arm64cpuid.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/md5/md5-aarch64.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/modes/aes-gcm-armv8-unroll8_64.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/modes/aes-gcm-armv8_64.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/modes/ghashv8-armx.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/sha/keccak1600-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/sha/sha1-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/sha/sha256-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/sha/sha512-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-ELF/crypto/sm3/sm3-armv8.S ||||!gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/aes/aesv8-armx.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/aes/bsaes-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/aes/vpaes-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/arm64cpuid.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/md5/md5-aarch64.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/modes/aes-gcm-armv8-unroll8_64.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/modes/aes-gcm-armv8_64.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/modes/ghashv8-armx.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/sha/keccak1600-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/sha/sha1-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/sha/sha256-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/sha/sha512-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
$(OPENSSL_GEN_PATH)/AARCH64-PE/crypto/sm3/sm3-armv8.S ||||gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
# Autogenerated files list ends here
|
||||
|
||||
[Packages]
|
||||
|
|
@ -2347,6 +2360,9 @@
|
|||
[FeaturePcd.IA32, FeaturePcd.X64]
|
||||
gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStyleNasm
|
||||
|
||||
[FeaturePcd.AARCH64]
|
||||
gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe
|
||||
|
||||
[BuildOptions]
|
||||
#
|
||||
# Disables the following Visual Studio compiler warnings brought by openssl source,
|
||||
|
|
|
|||
|
|
@ -29,9 +29,14 @@ my %targets = (
|
|||
perlasm_scheme => "elf",
|
||||
asm_arch => "x86_64",
|
||||
},
|
||||
"UEFI-AARCH64-GCC" => {
|
||||
"UEFI-AARCH64-ELF" => {
|
||||
inherit_from => [ "UEFI" ],
|
||||
asm_arch => "aarch64",
|
||||
perlasm_scheme => "linux64-aarch64",
|
||||
},
|
||||
"UEFI-AARCH64-PE" => {
|
||||
inherit_from => [ "UEFI" ],
|
||||
asm_arch => "aarch64",
|
||||
perlasm_scheme => "win64-aarch64",
|
||||
},
|
||||
);
|
||||
|
|
|
|||
|
|
@ -358,7 +358,7 @@ def main():
|
|||
defines = {}
|
||||
for asm in [ 'UEFI-IA32-MSFT', 'UEFI-IA32-GCC',
|
||||
'UEFI-X64-MSFT', 'UEFI-X64-GCC',
|
||||
'UEFI-AARCH64-GCC']:
|
||||
'UEFI-AARCH64-ELF', 'UEFI-AARCH64-PE']:
|
||||
(uefi, arch, cc) = asm.split('-')
|
||||
archcc = f'{arch}-{cc}'
|
||||
|
||||
|
|
@ -371,12 +371,12 @@ def main():
|
|||
|
||||
srclist = libcrypto_sources(cfg, archcc) + libssl_sources(cfg, archcc)
|
||||
if arch in ['AARCH64']:
|
||||
sources[archcc] = list(map(lambda x: f'{x} | {cc}', filter(is_asm, srclist)))
|
||||
featureflagexp = 'gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStylePe'
|
||||
else:
|
||||
featureflagexp = 'gEfiCryptoPkgTokenSpaceGuid.PcdOpensslLibAssemblySourceStyleNasm'
|
||||
if cc == 'GCC':
|
||||
featureflagexp = '!' + featureflagexp
|
||||
sources[archcc] = list(map(lambda x: f'{x} ||||{featureflagexp}', filter(is_asm, srclist)))
|
||||
if cc == 'GCC' or cc == 'ELF':
|
||||
featureflagexp = '!' + featureflagexp
|
||||
sources[archcc] = list(map(lambda x: f'{x} ||||{featureflagexp}', filter(is_asm, srclist)))
|
||||
update_MSFT_asm_format(archcc, sources[archcc])
|
||||
sources[arch] = list(filter(lambda x: not is_asm(x), srclist))
|
||||
defines[arch] = cfg['unified_info']['defines']['libcrypto']
|
||||
|
|
@ -386,7 +386,7 @@ def main():
|
|||
x64accel = sources['X64'] + sources['X64-MSFT'] + sources['X64-GCC']
|
||||
update_inf(inf, ia32accel, 'IA32', defines['IA32'])
|
||||
update_inf(inf, x64accel, 'X64', defines['X64'])
|
||||
aarch64accel = sources['AARCH64'] + sources['AARCH64-GCC']
|
||||
aarch64accel = sources['AARCH64'] + sources['AARCH64-ELF'] + sources['AARCH64-PE']
|
||||
update_inf(inf, aarch64accel, 'AARCH64', defines['AARCH64'])
|
||||
|
||||
# noaccel - ec enabled
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue