diff --git a/DynamicTablesPkg/DynamicTablesPkg.ci.yaml b/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
index 0631fe8149..bf318b94d2 100644
--- a/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
+++ b/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
@@ -112,6 +112,7 @@
            "deviceid",
            "EArch",
            "edynamic",
+           "eloongarch",
            "eventq",
            "EOBJECT",
            "gerror",
diff --git a/DynamicTablesPkg/Include/ConfigurationManagerObject.h b/DynamicTablesPkg/Include/ConfigurationManagerObject.h
index 4bdedb2277..e88ed97a38 100644
--- a/DynamicTablesPkg/Include/ConfigurationManagerObject.h
+++ b/DynamicTablesPkg/Include/ConfigurationManagerObject.h
@@ -2,6 +2,7 @@
 
   Copyright (c) 2017 - 2024, Arm Limited. All rights reserved.
   Copyright (c) 2024 Advanced Micro Devices, Inc. All rights reserved.
+  Copyright (c) 2026, Loongson Technology Corporation Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -15,6 +16,7 @@
 
 #include <ArchCommonNameSpaceObjects.h>
 #include <ArmNameSpaceObjects.h>
+#include <LoongArch64NameSpaceObjects.h>
 #include <RiscVNameSpaceObjects.h>
 #include <StandardNameSpaceObjects.h>
 #include <X64NameSpaceObjects.h>
@@ -37,6 +39,7 @@ Bits: [31:28] - Name Space ID
                 0010 - ARM
                 0011 - X64
                 0100 - RISC-V
+                0101 - LoongArch64
                 1111 - Custom/OEM
                 All other values are reserved.
 
@@ -90,6 +93,7 @@ typedef enum ObjectNameSpaceID {
   EObjNameSpaceArm,               ///< ARM Objects Namespace
   EObjNameSpaceX64,               ///< X64 Objects Namespace
   EObjNameSpaceRiscV,             ///< RISC-V Objects Namespace
+  EObjNameSpaceLoongArch64,       ///< LoongArch64 Objects Namespace
   EObjNameSpaceOem = 0xF,         ///< OEM Objects Namespace
   EObjNameSpaceMax,
 } EOBJECT_NAMESPACE_ID;
@@ -175,6 +179,16 @@ typedef struct CmObjDescriptor {
 #define CREATE_CM_RISCV_OBJECT_ID(ObjectId) \
           (CREATE_CM_OBJECT_ID (EObjNameSpaceRiscV, ObjectId))
 
+/** This macro returns a Configuration Manager Object ID
+    in the LoongArch64 Object Namespace.
+
+  @param [in] ObjectId    The Object ID.
+
+  @retval Returns a LoongArch64 Configuration Manager Object ID.
+**/
+#define CREATE_CM_LOONGARCH64_OBJECT_ID(ObjectId) \
+          (CREATE_CM_OBJECT_ID (EObjNameSpaceLoongArch64, ObjectId))
+
 /** This macro returns a Configuration Manager Object ID
     in the Arch Common Object Namespace.
 
diff --git a/DynamicTablesPkg/Include/LoongArch64NameSpaceObjects.h b/DynamicTablesPkg/Include/LoongArch64NameSpaceObjects.h
new file mode 100644
index 0000000000..f017ae630a
--- /dev/null
+++ b/DynamicTablesPkg/Include/LoongArch64NameSpaceObjects.h
@@ -0,0 +1,179 @@
+/** @file
+
+  Copyright (c) 2026, Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+    - Cm or CM   - Configuration Manager
+    - Obj or OBJ - Object
+**/
+
+#pragma once
+
+#include <AcpiObjects.h>
+#include <StandardNameSpaceObjects.h>
+
+#pragma pack(1)
+
+/** The ELOONGARCH64_OBJECT_ID enum describes the Object IDs
+    in the LoongArch64 Namespace.
+*/
+typedef enum LoongArch64ObjectID {
+  ELoongArch64ObjReserved,     ///< 0 - Reserved
+  ELoongArch64ObjMadtInfo,     ///< 1 - MADT table information
+  ELoongArch64ObjCorePicInfo,  ///< 2 - Core Programmable Interrupt Controller Info
+  ELoongArch64ObjLioPicInfo,   ///< 3 - Legacy I/O Programmable Interrupt Controller Info
+  ELoongArch64ObjHtPicInfo,    ///< 4 - HyperTransport Programmable Interrupt Controller Info
+  ELoongArch64ObjEioPicInfo,   ///< 5 - Extend I/O Programmable Interrupt Controller Info
+  ELoongArch64ObjMsiPicInfo,   ///< 6 - MSI Programmable Interrupt Controller Info
+  ELoongArch64ObjBioPicInfo,   ///< 7 - Bridge I/O Programmable Interrupt Controller Info
+  ELoongArch64ObjLpcPicInfo,   ///< 8 - Low Pin Count Programmable Interrupt Controller Info
+  ELoongArch64ObjMax
+} ELOONGARCH64_OBJECT_ID;
+
+/** A structure that describes MADT table-wide LoongArch64 information.
+
+    ID: ELoongArch64ObjMadtInfo
+*/
+typedef struct CmLoongArch64MadtInfo {
+  /// Address of the local interrupt controller.
+  UINT32    LocalApicAddress;
+
+  /// MADT flags.
+  UINT32    Flags;
+} CM_LOONGARCH64_MADT_INFO;
+
+/** A structure that describes a Core PIC.
+
+    ID: ELoongArch64ObjCorePicInfo
+*/
+typedef struct CmLoongArch64CorePicInfo {
+  /// PIC structure version. Currently, ACPI defines only version 1.
+  UINT8     Version;
+
+  /// ACPI processor UID matching the processor device's _UID.
+  UINT32    AcpiProcessorUid;
+
+  /// Physical processor ID. MAX_UINT32 is only valid for a disabled processor.
+  UINT32    CoreId;
+
+  /// CORE PIC flags. BIT0 is Enabled; all other bits are reserved.
+  UINT32    Flags;
+} CM_LOONGARCH64_CORE_PIC_INFO;
+
+/** A structure that describes a LIO PIC.
+
+    ID: ELoongArch64ObjLioPicInfo
+*/
+typedef struct CmLoongArch64LioPicInfo {
+  /// PIC structure version. Currently, ACPI defines only version 1.
+  UINT8     Version;
+
+  /// Base address
+  UINT64    Address;
+
+  /// Register space size
+  UINT16    Size;
+
+  /// Cascade vector
+  UINT8     Cascade[2];
+
+  /// Cascade map
+  UINT32    CascadeMap[2];
+} CM_LOONGARCH64_LIO_PIC_INFO;
+
+/** A structure that describes a HT PIC.
+
+    ID: ELoongArch64ObjHtPicInfo
+*/
+typedef struct CmLoongArch64HtPicInfo {
+  /// PIC structure version. Currently, ACPI defines only version 1.
+  UINT8     Version;
+
+  /// Base address
+  UINT64    Address;
+
+  /// Register space size
+  UINT16    Size;
+
+  /// Cascade vector
+  UINT8     Cascade[8];
+} CM_LOONGARCH64_HT_PIC_INFO;
+
+/** A structure that describes an EIO PIC.
+
+    ID: ELoongArch64ObjEioPicInfo
+*/
+typedef struct CmLoongArch64EioPicInfo {
+  /// PIC structure version. Currently, ACPI defines only version 1.
+  UINT8     Version;
+
+  /// Cascade vector
+  UINT8     Cascade;
+
+  /// Node ID
+  UINT8     Node;
+
+  /// Node map
+  UINT64    NodeMap;
+} CM_LOONGARCH64_EIO_PIC_INFO;
+
+/** A structure that describes a MSI PIC.
+
+    ID: ELoongArch64ObjMsiPicInfo
+*/
+typedef struct CmLoongArch64MsiPicInfo {
+  /// PIC structure version. Currently, ACPI defines only version 1.
+  UINT8     Version;
+
+  /// MSI message address
+  UINT64    MsgAddress;
+
+  /// MSI vector base
+  UINT32    Start;
+
+  /// MSI vector count
+  UINT32    Count;
+} CM_LOONGARCH64_MSI_PIC_INFO;
+
+/** A structure that describes a BIO PIC.
+
+    ID: ELoongArch64ObjBioPicInfo
+*/
+typedef struct CmLoongArch64BioPicInfo {
+  /// PIC structure version. Currently, ACPI defines only version 1.
+  UINT8     Version;
+
+  /// Base address
+  UINT64    Address;
+
+  /// Register space size
+  UINT16    Size;
+
+  /// Controller ID
+  UINT16    Id;
+
+  /// GSI base
+  UINT16    GsiBase;
+} CM_LOONGARCH64_BIO_PIC_INFO;
+
+/** A structure that describes a LPC PIC.
+
+    ID: ELoongArch64ObjLpcPicInfo
+*/
+typedef struct CmLoongArch64LpcPicInfo {
+  /// PIC structure version. Currently, ACPI defines only version 1.
+  UINT8     Version;
+
+  /// Base address
+  UINT64    Address;
+
+  /// Register space size
+  UINT16    Size;
+
+  /// Cascade vector
+  UINT8     Cascade;
+} CM_LOONGARCH64_LPC_PIC_INFO;
+
+#pragma pack()