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OvmfPkg: MmControlPei: Introduce MM control PPI to OVMF
This change adds a PEIM that produces gEfiPeiMmControlPpiGuid to be used in PEI phase, i.e. boot strap MM foundation. This flow is largely in assemblence of MM control DXE driver and used the `SmiFeatures.*` files from the DXE drivers as the common resources. Signed-off-by: Kun Qin <kun.qin@microsoft.com>
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Kun Qin
mergify[bot]
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84f140bf86
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2 changed files with 341 additions and 0 deletions
271
OvmfPkg/SmmControl2Dxe/MmControlPei.c
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271
OvmfPkg/SmmControl2Dxe/MmControlPei.c
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@ -0,0 +1,271 @@
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/** @file
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A PEIM providing synchronous SMI activations via the
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EFI_PEI_MM_CONTROL_PPI.
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We expect the PEI phase to have covered the following:
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- ensure that the underlying QEMU machine type be Q35
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(responsible: OvmfPkg/SmmAccess/SmmAccessPei.inf)
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- ensure that the ACPI PM IO space be configured
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(responsible: OvmfPkg/PlatformPei/PlatformPei.inf)
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Our own entry point is responsible for confirming the SMI feature and for
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configuring it.
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Copyright (C) 2013, 2015, Red Hat, Inc.<BR>
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Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
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Copyright (c) Microsoft Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include <IndustryStandard/Q35MchIch9.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/QemuFwCfgLib.h>
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#include <Ppi/MmControl.h>
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#include "SmiFeatures.h"
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//
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// The absolute IO port address of the SMI Control and Enable Register.
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//
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STATIC UINTN mSmiEnable;
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/**
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Invokes PPI activation from the PI PEI environment.
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@param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
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@param This The PEI_MM_CONTROL_PPI instance.
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@param ArgumentBuffer The value passed to the MMI handler. This value corresponds to the
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SwMmiInputValue in the RegisterContext parameter for the Register()
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function in the EFI_MM_SW_DISPATCH_PROTOCOL and in the Context parameter
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in the call to the DispatchFunction
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@param ArgumentBufferSize The size of the data passed in ArgumentBuffer or NULL if ArgumentBuffer is NULL.
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@param Periodic An optional mechanism to periodically repeat activation.
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@param ActivationInterval An optional parameter to repeat at this period one
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time or, if the Periodic Boolean is set, periodically.
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@retval EFI_SUCCESS The MMI has been engendered.
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@retval EFI_DEVICE_ERROR The timing is unsupported.
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@retval EFI_INVALID_PARAMETER The activation period is unsupported.
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@retval EFI_NOT_STARTED The MM base service has not been initialized.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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MmControlPeiTrigger (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_MM_CONTROL_PPI *This,
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IN OUT INT8 *ArgumentBuffer OPTIONAL,
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IN OUT UINTN *ArgumentBufferSize OPTIONAL,
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IN BOOLEAN Periodic OPTIONAL,
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IN UINTN ActivationInterval OPTIONAL
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)
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{
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UINT8 Command;
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UINT8 Data;
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//
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// No support for queued or periodic activation.
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//
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if (Periodic || (ActivationInterval > 0)) {
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return EFI_DEVICE_ERROR;
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}
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if ((ArgumentBufferSize != NULL) && (ArgumentBuffer == NULL)) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// The 0th byte as command, 1st as data... Right?
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//
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if ((NULL == ArgumentBuffer) || (*ArgumentBufferSize == 0)) {
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Command = 0;
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Data = 0;
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} else if (*ArgumentBufferSize == 1) {
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Command = *ArgumentBuffer;
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Data = 0;
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} else if (*ArgumentBufferSize == 2) {
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Command = ArgumentBuffer[0];
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Data = ArgumentBuffer[1];
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} else {
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return EFI_INVALID_PARAMETER;
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}
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//
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// The so-called "Advanced Power Management Status Port Register" is in fact
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// a generic data passing register, between the caller and the SMI
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// dispatcher. The ICH9 spec calls it "scratchpad register" -- calling it
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// "status" elsewhere seems quite the misnomer. Status registers usually
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// report about hardware status, while this register is fully governed by
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// software.
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//
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// Write to the status register first, as this won't trigger the SMI just
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// yet. Then write to the control register.
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//
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IoWrite8 (ICH9_APM_STS, Data);
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IoWrite8 (ICH9_APM_CNT, Command);
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return EFI_SUCCESS;
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}
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/**
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Clears any system state that was created in response to the Trigger() call.
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@param PeiServices General purpose services available to every PEIM.
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@param This The PEI_MM_CONTROL_PPI instance.
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@param Periodic Optional parameter to repeat at this period one
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time or, if the Periodic Boolean is set, periodically.
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@retval EFI_SUCCESS The MMI has been engendered.
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@retval EFI_DEVICE_ERROR The source could not be cleared.
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@retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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MmControlPeiClear (
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IN EFI_PEI_SERVICES **PeiServices,
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IN EFI_PEI_MM_CONTROL_PPI *This,
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IN BOOLEAN Periodic OPTIONAL
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)
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{
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if (Periodic) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// The PI spec v1.4 explains that Clear() is only supposed to clear software
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// status; it is not in fact responsible for deasserting the SMI. It gives
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// two reasons for this: (a) many boards clear the SMI automatically when
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// entering SMM, (b) if Clear() actually deasserted the SMI, then it could
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// incorrectly suppress an SMI that was asynchronously asserted between the
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// last return of the SMI handler and the call made to Clear().
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//
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// In fact QEMU automatically deasserts CPU_INTERRUPT_SMI in:
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// - x86_cpu_exec_interrupt() [target-i386/seg_helper.c], and
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// - kvm_arch_pre_run() [target-i386/kvm.c].
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//
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// So, nothing to do here.
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//
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return EFI_SUCCESS;
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}
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STATIC EFI_PEI_MM_CONTROL_PPI mMmControl =
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{
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.Trigger = MmControlPeiTrigger,
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.Clear = MmControlPeiClear
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};
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STATIC EFI_PEI_PPI_DESCRIPTOR mSmmControlPpiList =
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{
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(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEfiPeiMmControlPpiGuid,
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&mMmControl
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};
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//
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// Entry point of this driver.
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//
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EFI_STATUS
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EFIAPI
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MmControlPeiEntryPoint (
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IN EFI_PEI_FILE_HANDLE FileHandle,
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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UINT32 PmBase;
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UINT32 SmiEnableVal;
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EFI_STATUS Status;
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//
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// This module should only be included if SMRAM support is required.
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//
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ASSERT (FeaturePcdGet (PcdSmmSmramRequire));
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//
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// Calculate the absolute IO port address of the SMI Control and Enable
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// Register. (As noted at the top, the PEI phase has left us with a working
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// ACPI PM IO space.)
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//
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PmBase = PciRead32 (POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE)) &
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ICH9_PMBASE_MASK;
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mSmiEnable = PmBase + ICH9_PMBASE_OFS_SMI_EN;
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//
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// If APMC_EN is pre-set in SMI_EN, that's QEMU's way to tell us that SMI
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// support is not available. (For example due to KVM lacking it.) Otherwise,
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// this bit is clear after each reset.
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//
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SmiEnableVal = IoRead32 (mSmiEnable);
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if ((SmiEnableVal & ICH9_SMI_EN_APMC_EN) != 0) {
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DEBUG ((
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DEBUG_ERROR,
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"%a: this Q35 implementation lacks SMI\n",
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__func__
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));
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goto FatalError;
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}
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//
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// Otherwise, configure the board to inject an SMI when ICH9_APM_CNT is
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// written to. (See the Trigger() method above.)
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//
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SmiEnableVal |= ICH9_SMI_EN_APMC_EN | ICH9_SMI_EN_GBL_SMI_EN;
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IoWrite32 (mSmiEnable, SmiEnableVal);
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//
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// Prevent software from undoing the above (until platform reset).
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//
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PciOr16 (
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POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1),
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ICH9_GEN_PMCON_1_SMI_LOCK
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);
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//
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// If we can clear GBL_SMI_EN now, that means QEMU's SMI support is not
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// appropriate.
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//
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IoWrite32 (mSmiEnable, SmiEnableVal & ~(UINT32)ICH9_SMI_EN_GBL_SMI_EN);
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if (IoRead32 (mSmiEnable) != SmiEnableVal) {
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DEBUG ((
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DEBUG_ERROR,
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"%a: failed to lock down GBL_SMI_EN\n",
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__func__
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));
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goto FatalError;
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}
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//
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// We have no pointers to convert to virtual addresses. The handle itself
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// doesn't matter, as protocol services are not accessible at runtime.
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//
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Status = (*PeiServices)->InstallPpi (PeiServices, &mSmmControlPpiList);
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if (EFI_ERROR (Status)) {
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DEBUG ((
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DEBUG_ERROR,
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"%a: InstallMultipleProtocolInterfaces: %r\n",
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__func__,
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Status
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));
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goto FatalError;
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}
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return EFI_SUCCESS;
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FatalError:
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//
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// We really don't want to continue in this case.
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//
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ASSERT (FALSE);
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CpuDeadLoop ();
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return EFI_UNSUPPORTED;
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}
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70
OvmfPkg/SmmControl2Dxe/MmControlPei.inf
Normal file
70
OvmfPkg/SmmControl2Dxe/MmControlPei.inf
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@ -0,0 +1,70 @@
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## @file
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# A PEIM providing synchronous SMI activations via the
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# EFI_PEI_MM_CONTROL_PPI.
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#
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# We expect the PEI phase to have covered the following:
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# - ensure that the underlying QEMU machine type be Q35
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# (responsible: QemuQ35Pkg/SmmAccess/SmmAccessPei.inf)
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# - ensure that the ACPI PM IO space be configured
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# (responsible: QemuQ35Pkg/PlatformPei/PlatformPei.inf)
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#
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# Our own entry point is responsible for confirming the SMI feature and for
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# configuring it.
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#
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# Copyright (C) 2013, 2015, Red Hat, Inc.
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# Copyright (c) Microsoft Corporation.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = MmControlPei
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FILE_GUID = A0DBE438-701C-44AF-AB4A-25545B86B565
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MODULE_TYPE = PEIM
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VERSION_STRING = 1.0
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ENTRY_POINT = MmControlPeiEntryPoint
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#
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# The following information is for reference only and not required by the build tools.
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#
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# VALID_ARCHITECTURES = IA32 X64
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#
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[Sources]
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SmiFeatures.h
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SmiFeatures.c
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MmControlPei.c
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[Packages]
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MdePkg/MdePkg.dec
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OvmfPkg/OvmfPkg.dec
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UefiCpuPkg/UefiCpuPkg.dec
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[LibraryClasses]
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BaseLib
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DebugLib
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IoLib
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MemEncryptSevLib
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MemoryAllocationLib
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PcdLib
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PciLib
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QemuFwCfgLib
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QemuFwCfgS3Lib
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PeimEntryPoint
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[Ppis]
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gEfiPeiMmControlPpiGuid ## PRODUCES
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[Pcd]
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout ## SOMETIMES_PRODUCES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout2 ## SOMETIMES_PRODUCES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode ## SOMETIMES_PRODUCES
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[FeaturePcd]
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gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire
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gUefiOvmfPkgTokenSpaceGuid.PcdStandaloneMmEnable
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[Depex]
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TRUE
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