This commits splits out logic currently contained in
Gcd.c and Page.c to a new file called
MemoryBin.c. This is set up in preparation to
add support to PEI for memory bins (an S4 resume stability
feature).
MemoryBin.c takes all global state in as parameters so that
DXE core can use globals and PEI core can use HOBs.
There is no logic change here, just consolidating the
functionality to share with PEI.
This was requested not to be a library.
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
This reverts commit 57230fff6b.
RealTimeClockLib is not a generic library class that is intended to be
used widely to get access to the RTC when the associated runtime
services are not available in the calling context.
The purpose of RealTimeClockLib is to abstract the underlying hardware
access from the generic RealTimeClockRuntimeDxe driver, which backs the
runtime services.
This means it does not belong in a different package; it belongs in the
same package as the driver.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Create a CXL protocol for interacting with CXL endpoint devices. CXL
devices are necessarily also PCI devices, so the PCI IO protocol is also
provided as part of the CXL protocol.
The protocol provides access to the following operations for CXL devices:
- Read from a DVSEC register block
- Write to a DVSEC register block
- Perform DOE transaction
This set of operation is sufficient to implement BIOS-level CXL
functionality.
Signed-off-by: Nick Graves <nicholasgraves@google.com>
Signed-off-by: Oleksandr Tymoshenko <ovt@google.com>
Currently, the DXE page allocator does not ensure that guard
page allocations stay within the bin that it is attempting to
allocate within. As a result, S4 resume is jeopardized by
bins expanding due to guard pages, either into other bins or
out of bins. This is caught by a new assert in CoreGetMemoryMap()
to ensure the bins are correct.
This fixes this by changing the internal heap guard API to return
the adjusted size and start address of a proposed allocation. The
page allocator then can ensure that the adjusted allocation still
fits within the bin it is attempting to allocate within; if not,
it will search for another descriptor.
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
Replace the hardcoded NETWORK_COMMON_POLLING_INTERVAL (0x10 = 16ms)
with a new PCD PcdUsbNetworkPeriodicalTimer, allowing platforms to
configure the asynchronous transfer interval for USB network devices.
The default value of 16ms preserves existing behaviour.
EFI_USB_IO_PROTOCOL.UsbAsyncInterruptTransfer(), the PollingInterval
parameter must be between 1 and 255 milliseconds; a value of 0
returns EFI_INVALID_PARAMETER. The PCD is declared with a
@ValidRange of 1-255 and an ASSERT guards against a zero value at
runtime.
Co-authored-by: Abner Chang <abner.chang@amd.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
The current PciDevicePresent() implementation skips PCIe devices that
return Configuration Request Retry Status (CRS) during enumeration.
This causes devices that are slow to initialize (e.g., after power-on
or reset) to be missed entirely.
Per PCIe Base Specification Rev 3.1 Section 2.3.1, when CRS Software
Visibility is enabled and a device returns CRS, the Root Complex
reports Vendor ID as 0x0001. The specification recommends software
retry the configuration read until the device becomes ready.
This patch adds optional CRS retry support controlled by PCDs:
- PcdPciCrsRetryIntervalUs: Retry interval in microseconds (default 10000)
- PcdPciCrsTimeoutSeconds: Total timeout in seconds (default 0)
By default (PcdPciCrsTimeoutSeconds=0), CRS retry is disabled and
devices returning CRS are skipped during enumeration. Platforms
requiring CRS retry support should set PcdPciCrsTimeoutSeconds to
a non-zero value.
Additional improvements:
- Add PCI_VENDOR_ID_NONE and PCI_VENDOR_ID_CRS macros for readability
- Handle invalid PCD configurations (e.g., zero retry interval)
- Add DEBUG output for CRS detection, successful retry, and timeout
Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
MR-IOV was actually not used in MdeModulePkg and it has been
deprecated in PCIe 6.0 specification. Remove code references,
but keep PcdMrIovSupport with just a comment that it is deprecated.
Signed-off-by: Jacek Kolakowski <Jacek.Kolakowski@intel.com>
Resizable BAR driver selects max available BAR size to configure for use.
It may happen that some PCIe device declare support for size that exceeds
processor address width. Platform needs a way to define the max size it
can accept. This change introduce PCD called PcdPcieResizableBarMaxSize.
It is dynamic PCD where platform can provide its limit for BAR size.
Such PCD can be also controlled with a configuration knob.
Signed-off-by: Jacek Kolakowski <Jacek.Kolakowski@intel.com>
This PR introduces a new feature to enable infinite boot retries based on a newly created PCD.
When true, the system will continuously loop over all boot options.
PCD default is FALSE to match existing functionality.
This change is tested on QEMU based virtual platforms and physical
platforms.
This change is useful for certain server cases. Infinite retries allows
a server to continuously attempt boot in case of network failure and
recovery, and for such attempts to be accurately recorded in the TCG
logs.
Co-authored-by: Kun Qin <kun.qin@microsoft.com>
Co-authored-by: Aaron Pop <aaron.pop@microsoft.com>
Co-authored-by: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Sherry Fan <sherryfan@microsoft.com>
Some large capacity SATA HDD requires more time from power on
to ready state.
Making timeout value configurable by defining PCD
PcdSataDeviceReadyTimeout will allow platform.dsc to serve these
devices.
Defining gEfiMdeModulePkgTokenSpaceGuid.PcdSataDeviceReadyTimeout
with default value 16 Seconds in MdeModulePkg.dec.
Signed-off-by: gapandya <gaurav.pandya@amd.com>
Currently, there is no mechanism for platforms to enable or disable
support for EmbeddedDrivers in capsule updates. This patch introduces
a new PCD, PcdEmbeddedDriverSupport, allowing platforms to explicitly
control whether capsules containing EmbeddedDrivers are supported.
This ensures capsules with embedded drivers are rejected on platforms
that do not support them.
This is a breaking change.By default, PcdEmbeddedDriverSupport
is set to FALSE which disables embedded driver support in capsule updates
across all platforms unless explicitly enabled.
Platforms must opt-in by setting the PcdEmbeddedDriverSupport to TRUE
in order to enable support for capsules containing embedded drivers.
Signed-off-by: Pavithra Gurulingappa <gpavithr@qti.qualcomm.com>
edk2 is dropping support for the ARM32 architecture. This
commit removes ARM32 support from MdeModulePkg. This also
drops irrelevant VALID_ARCHITECTURE comments from infs that
are not arch specific.
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
The current fixed value of 8 for `DELAYED_DISPATCH_MAX_ENTRIES` is
not large enough to accommodate platform usage. This change replaces
the macro with a PCD that can be configured by platforms.
In the case the default PCD value is too small, an error message
explaining that the PCD should be updated will be printed followed
by an assert.
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
RealTimeClockLib is an architectural implementation that is not
restricted to the embedded segment or any platform in particular.
So the header has been moved to MdeModulePkg.
And the package has been added to the relevant INF files.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Sachin Ganesh <sachinganesh@ami.com>
Adding to the previous commit deprecating
EFI_UNICODE_COLLATION_PROTOCOL_GUID in MdeModulePkg.
Cc: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Gowtham M <gowthamm@ami.com>
When set to TRUE, bit EFI_OS_INDICATIONS_FMP_CAPSULE_SUPPORTED of
OsIndications is set.
At the moment EDK never sets this bit (there is only definition with no
uses), maybe nothing actually checks its value. Whatever the reason is,
it seems like a good idea to make setting it possible.
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
This PPI is no longer used - the EHCI and XHCI host controller PEIMs
expose PEI_USB2_HOST_CONTROLLER_PPI instead.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Move PcdSerialRegisterBase from [PcdsFixedAtBuild, PcdsPatchableInModule]
section to [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic,
PcdsDynamicEx] section to enable dynamic configuration.
Signed-off-by: Pranav V V <pranav.v.v@intel.com>
The PcdFfaTxRxPageCount can never be changed dynamically
and is configured at build time to specify the size of
the Rx/Tx buffers.
Therefore, make PcdFfaTxRxPageCount a PcdsFixedAtBuild PCD.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Update the comments for PcdDxeNxMemoryProtectionPolicy
which contained old information.
Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
Co-authored-by: Oliver Smith-Denny <osde@microsoft.com>
The Universal Graphics Adapter (UGA) is a graphic abstraction.
The UGA I/O and Draw protocols are deprecated since UEFI 2.0 was
introduced. Cf. the UEFI spec v2.9:
"Appendix L - EFI 1.10 Protocol Changes and Deprecation List"
section L.2 "Deprecated Protocols"
Remove the UGA support.
Signed-off-by: GuoMinJ <newexplorerj@gmail.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Currently, ArmFfaLib uses an internally defined Guided HOB to pass
information about the Rx/Tx buffer set up by the first executing agent.
However, the GUID definition is solely specified in the DEC file, which
is inconsistent with other GUID definitions in MdeModulePkg. This change
relocates the GUID definition to the Include/Guid folder to ensure
consistency across the package.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
ArmFfaLib is an implementation of an industry specification-defined
interface with UEFI specific method of handling Rx/Tx buffer sharing
across multiple boot phases, which is more appropriately placed in
MdeModulePkg.
This update relocates the implementation of ArmFfaLib to MdeModulePkg,
thereby supporting the FFA call primitives for all other packages that
depend on this interface.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
There are 2 reasons to move TdxMeasurementLib LibraryClass from
UefiCpuPkg to MdeModulePkg:
1. TpmMeasurementLib.h is located at MdeModulePkg/Include/Library.
It is similiar as TdxMeasurementLib.h.
2. TdxMeasurementLib is designed for TDX Measurement, it can be called
from SecurityPkg. And it is not much related to UefiCpuPkg.
Based upon above consideration, it's better to move TdxMeasurementLib
LibraryClass from UefiCpuPkg to MdeModulePkg.
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4496
This change adds the implementation that fits the needs and description
of PI spec defined Delayed Dispatch PPI in Pei Core.
The PPI would allow minimal delay for registered callbacks. As well as
allowing other functions to wait for GUIDed delayed dispatch callbacks.
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Co-authored-by: Mike Turner <mikeyt@pobox.com>
Co-authored-by: Sachin Ganesh <sachinganesh@ami.com>
Signed-off-by: Kun Qin <kuqin12@gmail.com>
Implementation of MEDIA_SANITIZE_PROTOCOL for NIST
purge/clear actions with mapping to NVM Express native
commands.
Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
PcdMmCommBufferPages is to specify the page count allocated for
the MM communication buffer.
Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com>
Co-authored-by: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Co-authored-by: Ray Ni <ray.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Wei6 Xu <wei6.xu@intel.com>
Cc: Dun Tan <dun.tan@intel.com>
Cc: Yuanhao Xie <yuanhao.xie@intel.com>
The MM communicate buffer facilitates data sharing between non-MM
and MM code.
The MM IPL code allocates a "fixed" runtime type memory as the MM
communication buffer, and communicates its address and size to MM
Core via MmCommBuffer GUIDed HOB.
Here, "fixed" implies that the buffer's location remains constant
throughout the boot process.
Data is exchanged between the MM Communication PPI/Protocol and a
software MMI handler using this fixed MM communication buffer.
Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com>
Co-authored-by: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Co-authored-by: Ray Ni <ray.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Wei6 Xu <wei6.xu@intel.com>
Cc: Dun Tan <dun.tan@intel.com>
Cc: Yuanhao Xie <yuanhao.xie@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4820
- Add the PCD to indicate the UFS device initialize completion time
- Default value of this PCD value is 600ms
Signed-off-by: Jason1 Lin <jason1.lin@intel.com>
Fire an event if a long delay occurs when starting an NVMe device.
This can be used by platforms to draw pictures on the screen or
take other actions to notify a user or move boot forward.
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4787
If ACPI Silicon Hob has been found from entry of AcpiTableDxe driver,
that means SOC related ACPI tables been pass to the DXE phase by HOB.
Each SOC related ACPI tables will be install.
Signed-off-by: George Liao <george.liao@intel.com>
Interface PrintHobList() is added to dump all HOBs info in the HobList.
Caller could specify a custom HOB print handler to replace the default
print handler when calling the interface.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Wei6 Xu <wei6.xu@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4716
Migrate FSP-T/M binary from temporary RAM to permanent RAM before NEM
tear down. Tcg module will use permanent address of FSP-T/M for
measurement. In MdeModulePkg, PeiCore installs mMigrateTempRamPpi if
PcdMigrateTemporaryRamFirmwareVolumes is True before NEM tear down and
after permanent memory ready.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com>
Cc: Chen Gang C <gang.c.chen@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Zhihao Li <zhihao.li@intel.com>
This commit defines VARIABLE_RUNTIME_CACHE_INFO HOB.
The HOB is used to store the address and size of the
buffer that will be used for variable runtime service
when the PcdEnableVariableRuntimeCache is TRUE.
In following patches, when PcdEnableVariableRuntimeCache
is TRUE, VariablePei module will install a callback of
gEfiPeiMemoryDiscoveredPpiGuid to allocate needed buffer
for different type cache, unblock the buffer and build HOB.
Then VariableSmmRuntimeDxe driver will consume the
gEdkiiVariableRuntimeCacheInfoHobGuid to initialize the
variable runtime cache related content.
Signed-off-by: Dun Tan <dun.tan@intel.com>
Add gEdkiiS3MtrrSettingGuid a new GUID for s3
MTRR setting. This GUID will be used to save
MTRR_SETTINGS at EndOfDxe by LockBox and restore
at S3 boot PEI phase for s3 usage.
Signed-off-by: Dun Tan <dun.tan@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
Adding NULL SpiHcPlatformLib instance. This library is responsible for
handling the low level details of the SPI host controller. Since this is
platform specific this library will be dependent on OEM SPI
implementation. The SPI host controller layer will utilize this library
for SPI bus transactions.
Bugzilla #4753
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Signed-off-by: Brit Chesley <brit.chesley@amd.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
https://bugzilla.tianocore.org/show_bug.cgi?id=4727
Recently some of XHCI host controllers require to have
extra 1ms delay before accessing any MMIO register
during reset. PHY transition from P3 to P0 can take
around 1.3ms and the xHCI reset can take around 1.5ms.
Add PCD to control the delay, the default is 2 ms.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Krzysztof Lewandowski <krzysztof.lewandowski@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: More Shih <more.shih@intel.com>
Cc: Ian Chiu <ian.chiu@intel.com>
Signed-off-by: Xianglei Cai <xianglei.cai@intel.com>
Reviewed-by: Krzysztof Lewandowski <krzysztof.lewandowski@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
UEFI spec defined ACPI Tables at boot time can be contained in memory of
type EfiACPIReclaimMemory or EfiAcpiMemoryNVS, although InstallAcpiTable
with AcpiTableProtocol will only allocate memory with type
EfiACPIReclaimMemory (Except FACS).
This patch provides an optional method controlled by PCD to avoid using
EfiACPIReclaimMemory, by setting the PCD PcdNoACPIReclaimMemory to TRUE,
all ACPI allocated memory will use EfiAcpiMemoryNVS instead.
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Liu Yun <yun.y.liu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Aaron Li <aaron.li@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Currently, there are multiple issues when page or pool guards are
allocated for runtime memory regions that are aligned to
non-EFI_PAGE_SIZE alignments. Multiple other issues have been fixed for
these same systems (notably ARM64 which has a 64k runtime page
allocation granularity) recently. The heap guard system is only built to
support 4k guard pages and 4k alignment.
Today, the address returned to a caller of AllocatePages will not be
aligned correctly to the runtime page allocation granularity, because
the heap guard system does not take non-4k alignment requirements into
consideration.
However, even with this bug fixed, the Memory Allocation Table cannot be
produced and an OS with a larger than 4k page granularity will not have
aligned memory regions because the guard pages are reported as part of
the same memory allocation. So what would have been, on an ARM64 system,
a 64k runtime memory allocation is actually a 72k memory allocation as
tracked by the Page.c code because the guard pages are tracked as part
of the same allocation. This is a core function of the current heap
guard architecture.
This could also be fixed with rearchitecting the heap guard system to
respect alignment requirements and shift the guard pages inside of the
outer rounded allocation or by having guard pages be the runtime
granularity. Both of these approaches have issues. In the former case,
we break UEFI spec 2.10 section 2.3.6 for AARCH64, which states that
each 64k page for runtime memory regions may not have mixed memory
attributes, which pushing the guard pages inside would create. In the
latter case, an immense amount of memory is wasted to support such large
guard pages, and with pool guard many systems could not support an
additional 128k allocation for all runtime memory.
The simpler and safer solution is to disallow page and pool guards for
runtime memory allocations for systems that have a runtime granularity
greater than the EFI_PAGE_SIZE (4k). The usefulness of such guards is
limited, as OSes do not map guard pages today, so there is only boot
time protection of these ranges. This also prevents other bugs from
being exposed by using guards for regions that have a non-4k alignment
requirement, as again, multiple have cropped up because the heap guard
system was not built to support it.
This patch adds both a static assert to ensure that either the runtime
granularity is the EFI_PAGE_SIZE or that the PCD bits are not set to
enable heap guard for runtime memory regions. It also adds a check in
the page and pool allocation system to ensure that at runtime we are not
allocating a runtime region and attempt to guard it (the PCDs are close
to being removed in favor of dynamic heap guard configurations).
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4674
Github PR: https://github.com/tianocore/edk2/pull/5382
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4533
There are use cases which not all FVs need be migrated from TempRam to
permanent memory before TempRam tears down. This new guid is introduced
to avoid unnecessary FV migration to improve boot performance. Platform
can publish MigrationInfo hob with this guid to customize FV migration
info, and PeiCore will only migrate FVs indicated by this Hob info.
This is a backwards compatible change, PeiCore will check MigrationInfo
hob before migration. If MigrationInfo hobs exists, only migrate FVs
recorded by hobs. If MigrationInfo hobs not exists, migrate all FVs to
permanent memory.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Cheng Sun <chengx.sun@intel.com>
Create a library for manipulating image properties records. The
library is currently blank and will be filled in a future patch
to help with reviewer readability.
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Dandan Bi <dandan.bi@intel.com>
Signed-off-by: Taylor Beebe <taylor.d.beebe@gmail.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Add PCD to control if modules with start addresses in PE/COFF > 0x100000
attempt to load at specified address.
If a module has an address in this range and there is untested memory
DxeCore will attempt to promote all memory to tested which bypasses any
memory testing that would occur later in boot.
There are several existing AARCH64 option roms that have base addresses
of 0x180000000.
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Ashish Singhal <ashishsingha@nvidia.com>
Message-Id: <bd36c9c24158590db2226ede05cb8c2f50c93a37.1684194452.git.jbrasen@nvidia.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4441
The EFI_RNG_PROTOCOL can rely on the RngLib. The RngLib has multiple
implementations, some of them are unsafe (e.g. BaseRngLibTimerLib).
To allow the RngDxe to detect when such implementation is used,
a GetRngGuid() function is added in a following patch.
Prepare GetRngGuid() return values and add a gEdkiiRngAlgorithmUnSafe
to describe an unsafe implementation, cf. the BaseRngLibTimerLib.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Kun Qin <kun.qin@microsoft.com>
This driver provides UEFI driver for USB RNDIS device
Signed-off-by: Richard Ho <richardho@ami.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Michael Kubacki <mikuback@linux.microsoft.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Tested-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com>
Acked-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Tony Lo <tonylo@ami.com>
Define a PPI interface that may be used by the PEI core or other PEIMs
to manage permissions on memory ranges. This is primarily intended for
restricting permissions to what is actually needed for correct execution
by the code in question, and for limiting the use of memory mappings
that are both writable and executable at the same time.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Oliver Smith-Denny <osde@linux.microsoft.com>
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4144
This Library provides API to dump Trace Hub message.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Guo Gua <gua.guo@intel.com>
Cc: Chan Laura <laura.chan@intel.com>
Cc: Prakashan Krishnadas Veliyathuparambil <krishnadas.veliyathuparambil.prakashan@intel.com>
Cc: K N Karthik <karthik.k.n@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Guo Gua <gua.guo@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: K N Karthik <karthik.k.n@intel.com>
Reviewed-by: Chan Laura <laura.chan@intel.com>
Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
