mirror of
https://github.com/tianocore/edk2
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5c6e9d475f
Add ArmSmcccSocIdLib to provide a shared interface for checking support for the SMCCC Architecture SoC ID service and retrieving the JEP106 identification code and SoC revision. Move the existing SMCCC SoC ID handling out of ProcessorSubClassDxe and update the driver to use the new library. Continue to use the MIDR value for the SMBIOS Processor ID when the SMCCC SoC ID service is unavailable. This allows other SMBIOS implementations to reuse the SMCCC handling without duplicating it or depending on the legacy ProcessorSubClassDxe driver. Signed-off-by: Varshit Pandya <Varshit.Pandya@arm.com>
355 lines
15 KiB
Text
355 lines
15 KiB
Text
#/** @file
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# ARM processor package.
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#
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# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2026, ARM Limited. All rights reserved.
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# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#**/
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[Defines]
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DEC_SPECIFICATION = 0x00010005
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PACKAGE_NAME = ArmPkg
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PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
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PACKAGE_VERSION = 0.1
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################################################################################
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#
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# Include Section - list of Include Paths that are provided by this package.
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# Comments are used for Keywords and Module Types.
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#
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# Supported Module Types:
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# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER UEFI_APPLICATION
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#
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################################################################################
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[Includes.common]
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Include # Root include for the package
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[LibraryClasses.common]
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## @libraryclass Provides an interface to Arm generic counters.
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#
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ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
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## @libraryclass Provides a Generic Interrupt Controller (GIC)
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# configuration interface.
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#
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ArmGicLib|Include/Library/ArmGicLib.h
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## @libraryclass Provides a HyperVisor Call (HVC) interface.
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#
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ArmHvcLib|Include/Library/ArmHvcLib.h
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## @libraryclass Provides a Mailbox Transport Layer (MTL) interface
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# for the System Control and Management Interface (SCMI).
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#
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ArmMtlLib|Include/Library/ArmMtlLib.h
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## @libraryclass Provides a Monitor Call interface that will use the
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# default conduit (HVC or SMC).
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#
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ArmMonitorLib|Include/Library/ArmMonitorLib.h
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## @libraryclass Provides access to the Arm SMCCC Architecture SoC ID
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# interface.
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#
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ArmSmcccSocIdLib|Include/Library/ArmSmcccSocIdLib.h
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## @libraryclass Provides an interface to query miscellaneous OEM
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# information.
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#
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OemMiscLib|Include/Library/OemMiscLib.h
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## @libraryclass Provides an OpTee interface.
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#
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OpteeLib|Include/Library/OpteeLib.h
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## @libraryclass Provides a semihosting interface.
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#
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SemihostLib|Include/Library/SemihostLib.h
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## @libraryclass Provides an interface for a StandaloneMm Mmu.
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#
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StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
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## @libraryclass Provides an interface for a Arm Transfer List.
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#
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ArmTransferListLib|Include/Library/ArmTransferListLib.h
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## @libraryclass Defines a set of interfaces for the MM core entrypoint for
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## AArch64.
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StandaloneMmCoreEntryPoint|Include/Library/ArmStandaloneMmCoreEntryPoint.h
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[Guids.common]
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gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
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## ARM MPCore table
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# Include/Guid/ArmMpCoreInfo.h
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gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
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gArmTransferListHobGuid = { 0xebe7bae8, 0xfe18, 0x43c5, { 0xbf, 0x3f, 0xf2, 0xb1, 0xaf, 0xb2, 0xdf, 0xb8 } }
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gPsaFwuUpdateAgentGuid = { 0x6823a838, 0x1b06, 0x470e, { 0x97, 0x74, 0x0c, 0xce, 0x8b, 0xfb, 0x53, 0xfd } }
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gPsaFwuImageDirectoryGuid = { 0xdeee58d9, 0x5147, 0x4ad3, { 0xa2, 0x90, 0x77, 0x66, 0x6e, 0x23, 0x41, 0xa5 } }
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gPsaFwuMetadataGuid = { 0x8a7a84a0, 0x8387, 0x40f6, { 0xab, 0x41, 0xa8, 0xb9, 0xa5, 0xa6, 0x0d, 0x23 } }
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gEdkiiTpmEventLogDescHobGuid = { 0x360c4a06, 0x146c, 0x11f0, { 0xb1, 0x73, 0x6b, 0xd5, 0x98, 0xff, 0x54, 0xd6 }}
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[Protocols.common]
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## Arm System Control and Management Interface(SCMI) Base protocol
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## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
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gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
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## Arm System Control and Management Interface(SCMI) Clock management protocol
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## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
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gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
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gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
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## Arm System Control and Management Interface(SCMI) Clock management protocol
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## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
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gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
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gEdkiiPiMmCpuDriverEpProtocolGuid = { 0x6ecbd5a1, 0xc0f8, 0x4702, { 0x83, 0x01, 0x4f, 0xc2, 0xc5, 0x47, 0x0a, 0x51 }}
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[Ppis]
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## Include/Ppi/ArmMpCoreInfo.h
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gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
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gArmTransferListPpiGuid = { 0x6d2e9da1, 0x9414, 0x41c3, {0x86, 0xbe, 0xf9, 0x16, 0x9f, 0xb4, 0x76, 0x38} }
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[PcdsFeatureFlag.common]
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gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
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# Whether to remap all unused memory NX before installing the CPU arch
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# protocol driver. This is needed on platforms that map all DRAM with RWX
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# attributes initially, and can be disabled otherwise.
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gArmTokenSpaceGuid.PcdRemapUnusedMemoryNx|TRUE|BOOLEAN|0x00000048
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[PcdsFixedAtBuild.common]
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gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
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gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
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#
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# ARM Secure Firmware PCDs
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#
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gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
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gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
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gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
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gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
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#
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# ARM Hypervisor Firmware PCDs
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#
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gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
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gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
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gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
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gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
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#
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# ARM StanaloneMm Stack size.
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#
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gArmTokenSpaceGuid.PcdStMmStackSize|0x2000|UINT32|0x0000005D
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# Use ClusterId + CoreId to identify the PrimaryCore
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
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# The Primary Core is ClusterId[0] & CoreId[0]
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gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
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#
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# SMBIOS PCDs
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#
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gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
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gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
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gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
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gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
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gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
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gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
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gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
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gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
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gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
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gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
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gArmTokenSpaceGuid.PcdProcessorSocketType|L""|VOID*|0x30000076
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#
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# ARM L2x0 PCDs
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#
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gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
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#
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# ARM Normal (or Non Secure) Firmware PCDs
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#
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gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
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gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
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#
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# Value to add to a host address to obtain a device address, using
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# unsigned 64-bit integer arithmetic on AArch64. This means we can
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# rely on truncation on overflow to specify negative offsets.
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#
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gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
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#
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# Boot the Uefi Shell instead of UiApp when no valid boot option is found.
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# This is useful in CI environment so that startup.nsh can be launched.
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# The default value is FALSE.
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#
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gArmTokenSpaceGuid.PcdUefiShellDefaultBootEnable|FALSE|BOOLEAN|0x0000052
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## Define the conduit to use for monitor calls.
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# Default PcdMonitorConduitHvc = FALSE, conduit = SMC
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# If PcdMonitorConduitHvc = TRUE, conduit = HVC
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gArmTokenSpaceGuid.PcdMonitorConduitHvc|FALSE|BOOLEAN|0x00000047
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#
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# AArch64 Security Extension
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#
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# Secure Configuration Register
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# - BIT0 : NS - Non Secure bit
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# - BIT1 : IRQ Handler
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# - BIT2 : FIQ Handler
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# - BIT3 : EA - External Abort
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# - BIT4 : FW - F bit writable
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# - BIT5 : AW - A bit writable
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# - BIT6 : nET - Not Early Termination
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# - BIT7 : SCD - Secure Monitor Call Disable
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# - BIT8 : HCE - Hyp Call enable
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# - BIT9 : SIF - Secure Instruction Fetch
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# - BIT10: RW - Register width control for lower exception levels
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# - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
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# - BIT12: TWI - Trap WFI
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# - BIT13: TWE - Trap WFE
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# 0x501 = NS | HCE | RW
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gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
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# By default we do transition to EL2 non-secure mode with Stack for EL2.
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# Mode Description Bits
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# NS EL2 SP2 all interrupts disabled = 0x3c9
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# NS EL1 SP1 all interrupts disabled = 0x3c5
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# Other modes include using SP0 or switching to Aarch32, but these are
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# not currently supported.
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gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
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[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
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gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
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gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
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#
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# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
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# redefined when using UEFI in a context of virtual machine.
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#
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[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
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# System Memory (DRAM): These PCDs define the region of in-built system memory
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# Some platforms can get DRAM extensions, these additional regions may be
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# declared to UEFI using separate resource descriptor HOBs
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gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
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gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
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gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
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gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
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gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
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gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
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#
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# For FmpDevicePsaFwuLib.
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#
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gArmTokenSpaceGuid.PcdSystemFirmwareFmpLowestSupportedVersion|0x00000000|UINT32|0x30000060
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gArmTokenSpaceGuid.PcdSystemFirmwareFmpVersion|0x00000000|UINT32|0x30000061
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gArmTokenSpaceGuid.PcdSystemFirmwareFmpVersionString|""|VOID*|0x30000062
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[PcdsFixedAtBuild.common, PcdsDynamic.common]
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# ARM Architectural Timer Interrupt(GIC PPI) numbers
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gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
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gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
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gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
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gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
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gArmTokenSpaceGuid.PcdArmArchTimerHypVirtIntrNum|28|UINT32|0x0000004A
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#
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# ARM Generic Watchdog
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#
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gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
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gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
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gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
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#
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# ARM Generic Interrupt Controller
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#
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gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
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# Base address for the GIC Redistributor region that contains the boot CPU
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gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
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gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
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gArmTokenSpaceGuid.PcdGicIrsConfigFrameBase|0|UINT64|0x00000064
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#
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# Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
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# Note that "IO" is just another MMIO range that simulates IO space; there
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# are no special instructions to access it.
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#
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# The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
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# specific to their containing address spaces. In order to get the physical
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# address for the CPU, for a given access, the respective translation value
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# has to be added.
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#
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# The translations always have to be initialized like this, using UINT64:
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#
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# UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
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# UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
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# UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
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#
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# gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
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# gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
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# gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
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#
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# because (a) the target address space (ie. the cpu-physical space) is
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# 64-bit, and (b) the translation values are meant as offsets for *modular*
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# arithmetic.
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#
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# Accordingly, the translation itself needs to be implemented as:
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#
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# UINT64 UntranslatedIoAddress; // input parameter
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# UINT32 UntranslatedMmio32Address; // input parameter
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# UINT64 UntranslatedMmio64Address; // input parameter
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#
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# UINT64 TranslatedIoAddress; // output parameter
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# UINT64 TranslatedMmio32Address; // output parameter
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# UINT64 TranslatedMmio64Address; // output parameter
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#
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# TranslatedIoAddress = UntranslatedIoAddress +
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# gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;
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# TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
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# gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;
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# TranslatedMmio64Address = UntranslatedMmio64Address +
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# gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;
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#
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# The modular arithmetic performed in UINT64 ensures that the translation
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# works correctly regardless of the relation between IoCpuBase and
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# PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
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# PcdPciMmio64Base.
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#
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gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
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gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
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gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
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gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
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gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
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gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
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#
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# Inclusive range of allowed PCI buses.
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#
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gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
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gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A
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[PcdsDynamicEx]
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#
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# This dynamic PCD hold the GUID of a firmware FFS which contains
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# the LinuxBoot payload.
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#
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gArmTokenSpaceGuid.PcdLinuxBootFileGuid|{0x0}|VOID*|0x0000005C
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