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ArmVirtQemu uses an initial early ID map in emulated NOR flash that is activated right out of reset, in order to avoid running a good chunk of the SEC and PEI stages with the MMU and caches disabled. This early ID map is currently not compatible with LPA2, and the associated startup code consciously omits 52-bit physical addressing, as it was not supported for 4k page sizes when this code was written. This means that by the time ArmConfigureMmu() runs, the TCR control register is already programmed with a value that reflects the non-LPA2 nature of the active page tables. Given that the MMU is on at that point, TCR cannot simply be updated to a value that enables LPA2. Yet this is what happens currently, and so the boot hangs really early when running ArmVirtQemu on LPA2 capable CPUs. Disabling the MMU again at this point is problematic, because it would require cache maintenance on the stack and on other live RAM regions. Given that the early page tables are in read-only NOR flash, updating them on the fly to make them LPA2 compatible is impossible. So instead, provide a second set of early page tables, but using 5 levels of paging for LPA2, and omitting the shareability attributes in the page table descriptors, as LPA2 repurposes these bits as physical address bits. Also update the startup code to program TCR.IPS and TCR.DS accordingly, but only if LPA2 is supported and the PArange is 52 bits: this reflects the logic in ArmConfigureMmu(), ensuring that the TCR value it calculates is identical to the one chosen by the early code. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> |
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| .. | ||
| ArmPlatformHelper.S | ||
| ArmPlatformLibQemu.c | ||
| ArmPlatformLibQemu.inf | ||
| IdMap.S | ||