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https://github.com/tianocore/edk2
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7835e5802a
Replace traditional `#ifndef`/`#define`/`#endif` include guards with
`#pragma` once.
`#pragma once` is a widely supported preprocessor directive that
prevents header files from being included multiple times. It is
supported by all toolchains used to build edk2: GCC, Clang/LLVM, and
MSVC.
Compared to macro-based include guards, `#pragma once`:
- Eliminates the risk of macro name collisions or copy/paste errors
where two headers inadvertently use the same guard macro.
- Eliminate inconsistency in the way include guard macros are named
(e.g., some files use `__FILE_H__`, others use `FILE_H_`, etc.).
- Reduces boilerplate (three lines replaced by one).
- Avoids polluting the macro namespace with guard symbols.
- Can improve build times as the preprocessor can skip re-opening the
file entirely, rather than re-reading it to find the matching
`#endif` ("multiple-include optimization").
- Note that some compilers may already optimize traditional include
guards, by recognzining the idiomatic pattern.
This change is made acknowledging that overall portability of the
code will technically be reduced, as `#pragma once` is not part of the
C/C++ standards.
However, this is considered acceptable given:
1. edk2 already defines a subset of supported compilers in
BaseTools/Conf/tools_def.template, all of which have supported
`#pragma once` for over two decades.
2. There have been concerns raised to the project about inconsistent
include guard naming and potential macro collisions.
Approximate compiler support dates:
- MSVC: Supported since Visual C++ 4.2 (1996)
- GCC: Supported since 3.4 (2004)
(http://gnu.ist.utl.pt/software/gcc/gcc-3.4/changes.html)
- Clang (LLVM based): Since initial release in 2007
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
203 lines
7.4 KiB
C
203 lines
7.4 KiB
C
/** @file
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Provides services to maintain instruction and data caches.
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The Cache Maintenance Library provides abstractions for basic processor cache operations.
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It removes the need to use assembly in C code.
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#pragma once
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/**
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Invalidates the entire instruction cache in cache coherency domain of the
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calling CPU.
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**/
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VOID
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EFIAPI
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InvalidateInstructionCache (
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VOID
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);
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/**
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Invalidates a range of instruction cache lines in the cache coherency domain
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of the calling CPU.
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Invalidates the instruction cache lines specified by Address and Length. If
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Address is not aligned on a cache line boundary, then entire instruction
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cache line containing Address is invalidated. If Address + Length is not
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aligned on a cache line boundary, then the entire instruction cache line
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containing Address + Length -1 is invalidated. This function may choose to
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invalidate the entire instruction cache if that is more efficient than
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invalidating the specified range. If Length is 0, then no instruction cache
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lines are invalidated. Address is returned.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@param Address The base address of the instruction cache lines to
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invalidate. If the CPU is in a physical addressing mode, then
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Address is a physical address. If the CPU is in a virtual
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addressing mode, then Address is a virtual address.
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@param Length The number of bytes to invalidate from the instruction cache.
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@return Address.
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**/
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VOID *
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EFIAPI
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InvalidateInstructionCacheRange (
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IN VOID *Address,
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IN UINTN Length
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);
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/**
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Writes Back and Invalidates the entire data cache in cache coherency domain
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of the calling CPU.
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Writes Back and Invalidates the entire data cache in cache coherency domain
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of the calling CPU. This function guarantees that all dirty cache lines are
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written back to system memory, and also invalidates all the data cache lines
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in the cache coherency domain of the calling CPU.
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**/
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VOID
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EFIAPI
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WriteBackInvalidateDataCache (
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VOID
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);
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/**
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Writes Back and Invalidates a range of data cache lines in the cache
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coherency domain of the calling CPU.
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Writes Back and Invalidate the data cache lines specified by Address and
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Length. If Address is not aligned on a cache line boundary, then entire data
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cache line containing Address is written back and invalidated. If Address +
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Length is not aligned on a cache line boundary, then the entire data cache
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line containing Address + Length -1 is written back and invalidated. This
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function may choose to write back and invalidate the entire data cache if
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that is more efficient than writing back and invalidating the specified
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range. If Length is 0, then no data cache lines are written back and
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invalidated. Address is returned.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@param Address The base address of the data cache lines to write back and
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invalidate. If the CPU is in a physical addressing mode, then
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Address is a physical address. If the CPU is in a virtual
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addressing mode, then Address is a virtual address.
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@param Length The number of bytes to write back and invalidate from the
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data cache.
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@return Address of cache invalidation.
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**/
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VOID *
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EFIAPI
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WriteBackInvalidateDataCacheRange (
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IN VOID *Address,
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IN UINTN Length
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);
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/**
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Writes Back the entire data cache in cache coherency domain of the calling
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CPU.
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Writes Back the entire data cache in cache coherency domain of the calling
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CPU. This function guarantees that all dirty cache lines are written back to
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system memory. This function may also invalidate all the data cache lines in
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the cache coherency domain of the calling CPU.
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**/
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VOID
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EFIAPI
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WriteBackDataCache (
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VOID
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);
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/**
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Writes Back a range of data cache lines in the cache coherency domain of the
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calling CPU.
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Writes Back the data cache lines specified by Address and Length. If Address
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is not aligned on a cache line boundary, then entire data cache line
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containing Address is written back. If Address + Length is not aligned on a
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cache line boundary, then the entire data cache line containing Address +
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Length -1 is written back. This function may choose to write back the entire
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data cache if that is more efficient than writing back the specified range.
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If Length is 0, then no data cache lines are written back. This function may
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also invalidate all the data cache lines in the specified range of the cache
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coherency domain of the calling CPU. Address is returned.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@param Address The base address of the data cache lines to write back. If
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the CPU is in a physical addressing mode, then Address is a
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physical address. If the CPU is in a virtual addressing
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mode, then Address is a virtual address.
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@param Length The number of bytes to write back from the data cache.
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@return Address of cache written in main memory.
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**/
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VOID *
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EFIAPI
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WriteBackDataCacheRange (
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IN VOID *Address,
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IN UINTN Length
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);
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/**
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Invalidates the entire data cache in cache coherency domain of the calling
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CPU.
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Invalidates the entire data cache in cache coherency domain of the calling
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CPU. This function must be used with care because dirty cache lines are not
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written back to system memory. It is typically used for cache diagnostics. If
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the CPU does not support invalidation of the entire data cache, then a write
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back and invalidate operation should be performed on the entire data cache.
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**/
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VOID
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EFIAPI
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InvalidateDataCache (
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VOID
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);
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/**
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Invalidates a range of data cache lines in the cache coherency domain of the
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calling CPU.
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Invalidates the data cache lines specified by Address and Length. If Address
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is not aligned on a cache line boundary, then entire data cache line
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containing Address is invalidated. If Address + Length is not aligned on a
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cache line boundary, then the entire data cache line containing Address +
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Length -1 is invalidated. This function must never invalidate any cache lines
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outside the specified range. If Length is 0, the no data cache lines are
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invalidated. Address is returned. This function must be used with care
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because dirty cache lines are not written back to system memory. It is
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typically used for cache diagnostics. If the CPU does not support
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invalidation of a data cache range, then a write back and invalidate
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operation should be performed on the data cache range.
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If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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@param Address The base address of the data cache lines to invalidate. If
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the CPU is in a physical addressing mode, then Address is a
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physical address. If the CPU is in a virtual addressing mode,
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then Address is a virtual address.
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@param Length The number of bytes to invalidate from the data cache.
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@return Address.
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**/
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VOID *
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EFIAPI
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InvalidateDataCacheRange (
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IN VOID *Address,
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IN UINTN Length
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);
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