Jian J Wang 54ec85dd29 MdeModulePkg/PiSmmIpl: fix non-executable SMM RAM ... This patch fixes an issue introduced by commit 5b91bf82c6 and 0c9f2cb10b This issue will only happen if PcdDxeNxMemoryProtectionPolicy is enabled for reserved memory, which will mark SMM RAM as NX (non- executable) during DXE core initialization. SMM IPL driver will unset the NX attribute for SMM RAM to allow loading and running SMM core/drivers. But above commit will fail the unset operation of the NX attribute due to a fact that SMM RAM has zero cache attribute (MRC code always sets 0 attribute to reserved memory), which will cause GCD internal method ConverToCpuArchAttributes() to return 0 attribute, which is taken as invalid CPU paging attribute and skip the calling of gCpu->SetMemoryAttributes(). The solution is to make use of existing functionality in PiSmmIpl to make sure one cache attribute is set for SMM RAM. For performance consideration, PiSmmIpl will always try to set SMM RAM to write-back. But there's a hole in the code which will fail the setting write-back attribute because of no corresponding cache capabilities. This patch will add necessary cache capabilities before setting corresponding attributes. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>		2018-04-13 13:05:00 +08:00
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Dxe	MdeModulePkg/DxeCore: add sanity check for SetMemoryAttributes	2018-04-13 13:04:59 +08:00
DxeIplPeim	MdeModulePkg DxeIpl: remove the hard code alignment adjustment in Decompress()	2018-01-19 13:20:29 +08:00
Pei	MdeModulePkg/Core/Pei: fix REGISITER -> REGISTER typo	2018-03-09 18:08:59 +01:00
PiSmmCore	MdeModulePkg/PiSmmIpl: fix non-executable SMM RAM	2018-04-13 13:05:00 +08:00
RuntimeDxe	MdeModulePkg: Update RuntimeDxe Crc32 to check the input parameter	2017-10-16 11:23:07 +08:00