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https://github.com/tgrysztar/fasm
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release 1.71.02
This commit is contained in:
Tomasz Grysztar
parent
367bc95b16
commit
90c5a8c5ad
9 changed files with 131 additions and 68 deletions
28
FASM.TXT
28
FASM.TXT
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@ -1454,7 +1454,7 @@ computes the sine of that value, "fcos" computes the cosine of that value,
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value, "frndint" rounds it to the nearest integral value, depending on the
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current rounding mode. "f2xm1" computes the exponential value of 2 to the
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power of ST0 and substracts the 1.0 from it, the value of ST0 must lie in the
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range -1.0 to +1.0. All these instruction store the result in ST0 and have no
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range -1.0 to +1.0. All these instructions store the result in ST0 and have no
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operands.
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"fsincos" computes both the sine and the cosine of the value in ST0
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register, stores the sine in ST0 and pushes the cosine on the top of FPU
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@ -1471,7 +1471,7 @@ remainder in the way specified by IEEE Standard 754. "fscale" truncates the
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value in ST1 and increases the exponent of ST0 by this value. "fxtract"
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separates the value in ST0 into its exponent and significand, stores the
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exponent in ST0 and pushes the significand onto the register stack. "fnop"
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performs no operation. These instruction have no operands.
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performs no operation. These instructions have no operands.
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"fxch" exchanges the contents of ST0 an another FPU register. The operand
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should be an FPU register, if no operand is specified, the contents of ST0 and
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ST1 are exchanged.
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@ -1504,7 +1504,7 @@ another FPU register and set the ZF, PF and CF flags according to the results.
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"fcomip" and "fucomip" additionaly pop the register stack after performing the
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comparison. The instructions obtained by attaching the FPU condition mnemonic
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(see table 2.2) to the "fcmov" mnemonic transfer the specified FPU register
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into ST0 register if the fiven test condition is true. These instruction
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into ST0 register if the given test condition is true. These instructions
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allow two different syntaxes, one with single operand specifying the source
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FPU register, and one with two operands, in that case destination operand
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should be ST0 register and the second operand specifies the source FPU
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@ -1533,7 +1533,7 @@ and sets the flags in FPU status word to indicate the class of value in the
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register. These instructions have no operands.
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"fstsw" and "fnstsw" store the current value of the FPU status word in the
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destination location. The destination operand can be either a 16-bit memory or
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the AX register. "fstsw" checks for pending umasked FPU exceptions before
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the AX register. "fstsw" checks for pending unmasked FPU exceptions before
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storing the status word, "fnstsw" does not.
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"fstcw" and "fnstcw" store the current value of the FPU control word at the
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specified destination in memory. "fstcw" checks for pending umasked FPU
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@ -1549,7 +1549,7 @@ FPU state (operating environment and register stack) at the specified
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destination in memory and reinitializes the FPU. "fsave" check for pending
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unmasked FPU exceptions before proceeding, "fnsave" does not. "frstor"
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loads the FPU state from the specified memory location. All these instructions
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need an operand being a memory location. For each of these instruction
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need an operand being a memory location. For each of these instructions
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exist two additional mnemonics that allow to precisely select the type of the
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operation. The "fstenvw", "fnstenvw", "fldenvw", "fsavew", "fnsavew" and
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"frstorw" mnemonics force the instruction to perform operation as in the 16-bit
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@ -1561,12 +1561,12 @@ state. "finit" checks for pending unmasked FPU exception before proceeding,
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FPU status word. "fclex" checks for pending unmasked FPU exception before
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proceeding, "fnclex" does not. "wait" and "fwait" are synonyms for the same
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instruction, which causes the processor to check for pending unmasked FPU
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exceptions and handle them before proceeding. These instruction have no
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exceptions and handle them before proceeding. These instructions have no
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operands.
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"ffree" sets the tag associated with specified FPU register to empty. The
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operand should be an FPU register.
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"fincstp" and "fdecstp" rotate the FPU stack by one by adding or
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substracting one to the pointer of the top of stack. These instruction have no
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substracting one to the pointer of the top of stack. These instructions have no
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operands.
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@ -1948,7 +1948,7 @@ operand. "cvtpd2dq" and "cvttpd2dq" convert packed double precision floating
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point values to packed two double word integers, storing the result in the low
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quad word of the destination operand. "cvtdq2ps" converts packed four
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double word integers to packed single precision floating point values.
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For all these instruction destination operand must be a SSE register, the
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For all these instructions destination operand must be a SSE register, the
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source operand can be a 128-bit memory location or SSE register.
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"cvtdq2pd" converts packed two double word integers from the source operand to
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packed double precision floating point values, the source can be a 64-bit
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@ -2050,7 +2050,7 @@ source operand into high quad word of destination operand. "haddpd" performs
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the addition of two double precision values within each operand, and stores
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the result from destination operand into low quad word of destination operand,
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and the result from source operand into high quad word of destination operand.
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All these instruction need the destination operand to be SSE register, source
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All these instructions need the destination operand to be SSE register, source
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operand can be SSE register or 128-bit memory location.
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"monitor" sets up an address range for monitoring of write-back stores. It
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need its three operands to be EAX, ECX and EDX register in that order. "mwait"
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@ -2300,7 +2300,7 @@ packed quad words into the destination register. "pminsb" and "pmaxsb"
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return the minimum or maximum values of packed signed bytes, "pminuw" and
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"pmaxuw" return the minimum and maximum values of packed unsigned words,
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"pminud", "pmaxud", "pminsd" and "pmaxsd" return minimum or maximum values
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of packed unsigned or signed words. These instruction complement the
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of packed unsigned or signed words. These instructions complement the
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instructions computing packed minimum or maximum introduced by SSE.
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"ptest" sets the ZF flag to one when the result of bitwise AND of the
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both operands is zero, and zeroes the ZF otherwise. It also sets CF flag
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@ -2842,7 +2842,7 @@ AVX. They introduce new vector instructions (and sometimes also their SSE
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equivalents that use classic instruction encoding), and even some new
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instructions operating on general registers that use the AVX-like encoding
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allowing the extended syntax with separate destination and source operands.
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The CPU support for each of these instruction sets needs to be determined
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The CPU support for each of these instructions sets needs to be determined
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separately.
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The AES extension provides a specialized set of instructions for the
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purpose of cryptographic computations defined by Advanced Encryption Standard.
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@ -2964,7 +2964,7 @@ unsigned quad words. The respective values from the first and second source
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are compared and the corresponding data element in destination is set to
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either all ones or all zeros depending on the result of comparison. The fourth
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operand has to specify one of the eight comparison types (table 2.5). All
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these instruction have also variants with only three operands and the type
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these instructions have also variants with only three operands and the type
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of comparison encoded within the instruction name by inserting the comparison
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mnemonic after "vpcom".
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@ -3021,7 +3021,7 @@ from the first and second source and then add the products to the parallel
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values from the third source, then "vpmacsww" takes the lowest 16 bits of the
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result and "vpmacssww" saturates the result down to 16-bit value, and they
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store the final 16-bit results in the destination. "vpmacsdd" and "vpmacssdd"
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perform the analogous operation on 32-bit values. "vpmacswd" and "vpmacswd" do
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perform the analogous operation on 32-bit values. "vpmacswd" and "vpmacsswd" do
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the same calculation only on the low 16-bit values from each 32-bit block and
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form the 32-bit results. "vpmacsdql" and "vpmacssdql" perform such operation
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on the low 32-bit values from each 64-bit block and form the 64-bit results,
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@ -3703,7 +3703,7 @@ while it will itself define "alpha" when it's not already defined earlier, thus
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potentially causing the error because of double definition if the "alpha" is
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also defined somewhere later.
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The "used" operator may be expected to behave in a similar manner in
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analogous cases, however any other kinds of predictions my not be so simple and
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analogous cases, however any other kinds of predictions may not be so simple and
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you should never rely on them this way.
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The "err" directive, usually used to stop the assembly when some condition is
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met, stops the assembly immediately, regardless of whether the current pass
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@ -1,5 +1,5 @@
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flat assembler version 1.70
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flat assembler version 1.71
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Copyright (c) 1999-2012, Tomasz Grysztar.
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All rights reserved.
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@ -256,10 +256,12 @@ get_params:
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stosb
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pop ds
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cmp [input_file],0
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je bad_params
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je no_input_file
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clc
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ret
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bad_params:
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pop ds
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no_input_file:
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stc
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ret
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@ -290,17 +290,27 @@ calculate_expression:
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mov [error_info],ebx
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jmp calculation_loop
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calculate_add:
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mov ecx,[ebx+16]
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cmp byte [edi+12],0
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je add_values
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mov ecx,[edi+16]
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cmp byte [ebx+12],0
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je add_values
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call recoverable_misuse
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add_values:
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xor ah,ah
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mov ah,[ebx+12]
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mov al,[edi+12]
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or [ebx+12],al
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or al,al
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jz add_values
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or ah,ah
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jz add_relocatable
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add ah,al
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jnz invalid_add
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mov ecx,[edi+16]
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cmp ecx,[ebx+16]
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je add_values
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invalid_add:
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call recoverable_misuse
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jmp add_values
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add_relocatable:
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mov ah,al
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mov ecx,[edi+16]
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mov [ebx+16],ecx
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add_values:
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mov [ebx+12],ah
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mov eax,[edi]
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add [ebx],eax
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mov eax,[edi+4]
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@ -314,31 +324,29 @@ calculate_expression:
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jz calculation_loop
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push esi
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mov esi,ebx
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lea ebx,[edi+10]
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mov cl,[edi+8]
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mov cl,[edi+10]
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mov al,[edi+8]
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call add_register
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lea ebx,[edi+11]
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mov cl,[edi+9]
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mov cl,[edi+11]
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mov al,[edi+9]
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call add_register
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pop esi
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jmp calculation_loop
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add_register:
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or cl,cl
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or al,al
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jz add_register_done
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add_register_start:
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cmp [esi+8],cl
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cmp [esi+8],al
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jne add_in_second_slot
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mov al,[ebx]
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add [esi+10],al
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add [esi+10],cl
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jo value_out_of_range
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jnz add_register_done
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mov byte [esi+8],0
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ret
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add_in_second_slot:
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cmp [esi+9],cl
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cmp [esi+9],al
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jne create_in_first_slot
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mov al,[ebx]
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add [esi+11],al
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add [esi+11],cl
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jo value_out_of_range
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jnz add_register_done
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mov byte [esi+9],0
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@ -346,16 +354,14 @@ calculate_expression:
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create_in_first_slot:
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cmp byte [esi+8],0
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jne create_in_second_slot
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mov [esi+8],cl
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mov al,[ebx]
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mov [esi+10],al
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mov [esi+8],al
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mov [esi+10],cl
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ret
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create_in_second_slot:
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cmp byte [esi+9],0
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jne invalid_expression
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mov [esi+9],cl
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mov al,[ebx]
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mov [esi+11],al
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mov [esi+9],al
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mov [esi+11],cl
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add_register_done:
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ret
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out_of_range:
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@ -366,6 +372,8 @@ calculate_expression:
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mov al,[edi+12]
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or al,al
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jz sub_values
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or ah,ah
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jz negate_relocatable
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cmp al,ah
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jne invalid_sub
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xor ah,ah
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@ -374,6 +382,12 @@ calculate_expression:
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je sub_values
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invalid_sub:
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call recoverable_misuse
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jmp sub_values
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negate_relocatable:
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neg al
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mov ah,al
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mov ecx,[edi+16]
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mov [ebx+16],ecx
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sub_values:
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mov [ebx+12],ah
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mov eax,[edi]
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@ -391,18 +405,18 @@ calculate_expression:
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jz calculation_loop
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push esi
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mov esi,ebx
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lea ebx,[edi+10]
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mov cl,[edi+8]
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mov cl,[edi+10]
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mov al,[edi+8]
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call sub_register
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lea ebx,[edi+11]
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mov cl,[edi+9]
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mov cl,[edi+11]
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mov al,[edi+9]
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call sub_register
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pop esi
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jmp calculation_loop
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sub_register:
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or cl,cl
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or al,al
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jz add_register_done
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neg byte [ebx]
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neg cl
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jo value_out_of_range
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jmp add_register_start
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calculate_mul:
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@ -424,6 +438,7 @@ calculate_expression:
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xor bl,bl
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cmp byte [esi+13],0
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je mul_first_sign_ok
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xor bl,-1
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mov eax,[esi]
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mov edx,[esi+4]
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not eax
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@ -434,10 +449,20 @@ calculate_expression:
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mov [esi+4],edx
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or eax,edx
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jz mul_overflow
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xor bl,-1
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mul_first_sign_ok:
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cmp byte [edi+13],0
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je mul_second_sign_ok
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xor bl,-1
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cmp byte [esi+8],0
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je mul_first_register_sign_ok
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neg byte [esi+10]
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jo invalid_expression
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mul_first_register_sign_ok:
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cmp byte [esi+9],0
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je mul_second_register_sign_ok
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neg byte [esi+11]
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jo invalid_expression
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mul_second_register_sign_ok:
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mov eax,[edi]
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mov edx,[edi+4]
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not eax
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@ -448,7 +473,6 @@ calculate_expression:
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mov [edi+4],edx
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or eax,edx
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jz mul_overflow
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xor bl,-1
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mul_second_sign_ok:
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cmp dword [esi+4],0
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jz mul_numbers
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@ -879,12 +903,17 @@ calculate_expression:
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not dword [edi]
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jmp finish_not
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calculate_neg:
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cmp word [edi+8],0
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jne invalid_expression
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cmp byte [edi+12],0
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je neg_ok
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call recoverable_misuse
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neg_ok:
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cmp byte [edi+8],0
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je neg_first_register_ok
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neg byte [edi+10]
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jo invalid_expression
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neg_first_register_ok:
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cmp byte [edi+9],0
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je neg_second_register_ok
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neg byte [edi+11]
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jo invalid_expression
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neg_second_register_ok:
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neg byte [edi+12]
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xor eax,eax
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xor edx,edx
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xor cl,cl
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|
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@ -2438,8 +2438,10 @@ mark_coff_relocation:
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test [format_flags],8
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jnz coff_64bit_relocation
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mov al,6
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cmp [value_type],2
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je coff_relocation
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cmp [value_type],5
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jne coff_relocation
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jne invalid_use_of_symbol
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inc al
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jmp coff_relocation
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coff_64bit_relocation:
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@ -2447,8 +2449,10 @@ mark_coff_relocation:
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cmp [value_type],4
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je coff_relocation
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mov al,2
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cmp [value_type],2
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je coff_relocation
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cmp [value_type],5
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jne coff_relocation
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jne invalid_use_of_symbol
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inc al
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jmp coff_relocation
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coff_relocation_relative:
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||||
|
|
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|
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@ -1,5 +1,5 @@
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; flat assembler version 1.70
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; flat assembler version 1.71
|
||||
; Copyright (c) 1999-2012, Tomasz Grysztar.
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; All rights reserved.
|
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;
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@ -33,7 +33,7 @@
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; cannot simply be copied and put under another distribution licence
|
||||
; (including the GNU Public Licence).
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||||
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VERSION_STRING equ "1.71.01"
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VERSION_STRING equ "1.71.02"
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VERSION_MAJOR = 1
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VERSION_MINOR = 71
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|
|
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|
|
@ -343,9 +343,14 @@ listing:
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address_ok:
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ret
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address_register:
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test dh,dh
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jz register_ok
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cmp dh,0
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je register_ok
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jl negative_register
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mov al,'+'
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jmp register_sign_ok
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negative_register:
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mov al,'-'
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register_sign_ok:
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stosb
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push esi
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mov esi,address_registers
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||||
|
|
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|
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@ -114,15 +114,25 @@ symbols:
|
|||
mov bl,[edx+13]
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||||
mov bh,[edx+15]
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call write_address_register
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||||
cmp byte [edx+11],0
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mov bl,[edx+11]
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cmp bl,0
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je symbol_type_ok
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jl negated_symbol
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mov ax,', '
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stosw
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||||
cmp byte [edx+11],1
|
||||
jmp write_symbol_type
|
||||
negated_symbol:
|
||||
mov ax,', '
|
||||
stosw
|
||||
mov esi,_negated
|
||||
call write_string
|
||||
neg bl
|
||||
write_symbol_type:
|
||||
cmp bl,1
|
||||
je segment_type
|
||||
cmp byte [edx+11],5
|
||||
cmp bl,5
|
||||
je rva_type
|
||||
cmp byte [edx+11],6
|
||||
cmp bl,6
|
||||
je plt_type
|
||||
test byte [edx+20+3],80h
|
||||
jnz external
|
||||
|
|
@ -250,9 +260,14 @@ write_dec_number:
|
|||
pop edx ebx
|
||||
ret
|
||||
write_address_register:
|
||||
test bh,bh
|
||||
jz register_ok
|
||||
cmp bh,0
|
||||
je register_ok
|
||||
jl negative_register
|
||||
mov al,'+'
|
||||
jmp register_sign_ok
|
||||
negative_register:
|
||||
mov al,'-'
|
||||
register_sign_ok:
|
||||
stosb
|
||||
push esi
|
||||
mov esi,address_registers
|
||||
|
|
@ -390,6 +405,7 @@ address_registers db 23h,2,'bx'
|
|||
db 0F8h,3,'rip'
|
||||
db 0,1,'?'
|
||||
|
||||
_negated db 'negated ',0
|
||||
_relocatable_segment db 'relocatable segment',0
|
||||
_relocatable db 'relocatable',0
|
||||
_in_section db ' in section ',0
|
||||
|
|
|
|||
|
|
@ -2,6 +2,13 @@
|
|||
Visit http://flatassembler.net/ for more information.
|
||||
|
||||
|
||||
version 1.71.02 (Sep 26, 2012)
|
||||
|
||||
[-] Expression calculator now allows to calculate the difference of
|
||||
relocatable addresses in a reverse order (first substracting/negating
|
||||
and then adding the other one).
|
||||
|
||||
|
||||
version 1.71.01 (Sep 23, 2012)
|
||||
|
||||
[+] Added support for ADX, RDSEED and SMAP instruction sets.
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue