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x86/insns.dat: non-vector instructions from ISE 319433-046 2022-09

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Additional nonvector instructions from the Intel Instruction Set
Extensions document 319433-046 September 2022.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin 2022-11-12 13:15:03 -08:00
parent a3fd34ab80
commit 2b01ddf2ec
2 changed files with 35 additions and 4 deletions
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4
x86/iflags.ph
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@ -100,6 +100,10 @@ if_("AMXINT8", "AMX 8-bit integer multiplication");
if_("FRED", "Flexible Return and Exception Delivery (FRED)");
if_("RAOINT", "Remote atomic operations (RAO-INT)");
if_("UINTR", "User interrupts");
if_("CMPCCXADD", "CMPccXADD instructions");
if_("PREFETCHI", "PREFETCHI0 and PREFETCHI1");
if_("WRMSRNS", "WRMSRNS");
if_("MSRLIST", "RDMSRLIST and WRMSRLIST");
# Put these last to minimize their relevance
if_("OBSOLETE", "Instruction removed from architecture");

35
x86/insns.dat
View file

@ -1636,10 +1636,12 @@ XRSTORS64 mem [m: o64 np 0f c7 /3] LONG,FUTURE
; These instructions are not SSE-specific; they are
;# Generic memory operations
; and work even if CR4.OSFXFR == 0
PREFETCHNTA mem8 [m: 0f 18 /0] KATMAI
PREFETCHT0 mem8 [m: 0f 18 /1] KATMAI
PREFETCHT1 mem8 [m: 0f 18 /2] KATMAI
PREFETCHT2 mem8 [m: 0f 18 /3] KATMAI
PREFETCHNTA mem8 [m: 0f 18 /0] KATMAI,SB
PREFETCHT0 mem8 [m: 0f 18 /1] KATMAI,SB
PREFETCHT1 mem8 [m: 0f 18 /2] KATMAI,SB
PREFETCHT2 mem8 [m: 0f 18 /3] KATMAI,SB
PREFETCHIT0 mem8 [m: 0f 18 /7] FUTURE,PREFETCHI,SB
PREFETCHIT1 mem8 [m: 0f 18 /6] FUTURE,PREFETCHI,SB
SFENCE void [ np 0f ae f8] KATMAI
;# New MMX instructions introduced in Katmai
@ -6305,6 +6307,31 @@ VSUBPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.np.map5.w0 5
VSUBSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.f3.map5.w0 5c /r] AVX512FP16,FUTURE
VUCOMISH xmmreg,xmmrm16|sae [rm:t1s: evex.lig.np.map5.w0 2e /r] AVX512FP16,FUTURE
;# RAO-INT weakly ordered atomic operations
AADD mem32,reg32 [mr: norexw np 0f 38 fc /r ] RAOINT,FUTURE,SD
AADD mem64,reg64 [mr: o64 np 0f 38 fc /r ] RAOINT,FUTURE,SQ,LONG
AAND mem32,reg32 [mr: norexw 66 0f 38 fc /r ] RAOINT,FUTURE,SD
AAND mem64,reg64 [mr: o64 66 0f 38 fc /r ] RAOINT,FUTURE,SQ,LONG
AXOR mem32,reg32 [mr: norexw f3 0f 38 fc /r ] RAOINT,FUTURE,SD
AXOR mem64,reg64 [mr: o64 f3 0f 38 fc /r ] RAOINT,FUTURE,SQ,LONG
;# User interrupts
CLUI void [ f3 0f 01 ee ] UINTR,FUTURE,LONG
SENDUIPI reg64 [m: o64nw f3 0f c7 /6 ] UINTR,FUTURE,LONG
STUI void [ f3 0f 01 ef ] UINTR,FUTURE,LONG
TESTUI void [ f3 0f 01 ed ] UINTR,FUTURE,LONG
UIRET void [ f3 0f 01 ec ] UINTR,FUTURE,LONG
;# Compare, exchange and add conditional
CMPccXADD mem32,reg32,reg32 [mrv: vex.128.66.0f38.w0 e0+c /r] CMPCCXADD,FUTURE,LONG,SD
CMPccXADD mem64,reg64,reg64 [mrv: vex.128.66.0f38.w1 e0+c /r] CMPCCXADD,FUTURE,LONG,SQ
;# WRMSRNS and MSRLIST instructions
WRMSRNS void [ np 0f 01 c6 ] WRMSRNS,FUTURE,PRIV,LONG
RDMSRLIST void [ f2 0f 01 c6 ] MSRLIST,FUTURE,PRIV,LONG
WRMSRLIST void [ f3 0f 01 c6 ] MSRLIST,FUTURE,PRIV,LONG
;# Systematic names for the hinting nop instructions
; These should be last in the file
HINT_NOP0 rm16 [m: o16 0f 18 /0] P6,UNDOC