mirror of
https://github.com/netwide-assembler/nasm
synced 2026-08-26 16:23:04 -04:00
Merge remote-tracking branch 'yongjie/apx.wip' into apx.wip
This commit is contained in:
H. Peter Anvin
commit
33262b072a
7 changed files with 597 additions and 0 deletions
44
travis/test/avx10.1.asm
Normal file
44
travis/test/avx10.1.asm
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;Testname=avx10.1; Arguments=-fbin -oavx10.1.bin -O0 -DSRC; Files=stdout stderr avx10.1.bin
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%macro testcase 2
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%ifdef BIN
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db %1
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%endif
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%ifdef SRC
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%2
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%endif
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%endmacro
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bits 64
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testcase { 0x62, 0xf5, 0x6c, 0x08, 0x5f, 0xcb }, { vmaxph xmm1,xmm2,xmm3 }
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testcase { 0x62, 0xf5, 0x6c, 0x28, 0x5f, 0xcb }, { vmaxph ymm1,ymm2,ymm3 }
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testcase { 0x62, 0xf5, 0x6c, 0x48, 0x5f, 0xcb }, { vmaxph zmm1,zmm2,zmm3 }
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testcase { 0x62, 0xb5, 0x6c, 0x08, 0x5f, 0x4c, 0xf0, 0x01 }, { vmaxph xmm1,xmm2,[rax+r14*8+0x10] }
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testcase { 0x62, 0xb5, 0x6c, 0x28, 0x5f, 0x8c, 0xf0, 0x10, 0x00, 0x00, 0x00 }, { vmaxph ymm1,ymm2,[rax+r14*8+0x10] }
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testcase { 0x62, 0xb5, 0x6c, 0x48, 0x5f, 0x8c, 0xf0, 0x10, 0x00, 0x00, 0x00 }, { vmaxph zmm1,zmm2,[rax+r14*8+0x10] }
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testcase { 0x62, 0xf5, 0x6c, 0x08, 0x5d, 0xcb }, { vminph xmm1,xmm2,xmm3 }
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testcase { 0x62, 0xf5, 0x6c, 0x28, 0x5d, 0xcb }, { vminph ymm1,ymm2,ymm3 }
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testcase { 0x62, 0xf5, 0x6c, 0x48, 0x5d, 0xcb }, { vminph zmm1,zmm2,zmm3 }
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testcase { 0x62, 0xb5, 0x6c, 0x08, 0x5d, 0x4c, 0xf0, 0x01 }, { vminph xmm1,xmm2,[rax+r14*8+0x10] }
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testcase { 0x62, 0xb5, 0x6c, 0x28, 0x5d, 0x8c, 0xf0, 0x10, 0x00, 0x00, 0x00 }, { vminph ymm1,ymm2,[rax+r14*8+0x10] }
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testcase { 0x62, 0xb5, 0x6c, 0x48, 0x5d, 0x8c, 0xf0, 0x10, 0x00, 0x00, 0x00 }, { vminph zmm1,zmm2,[rax+r14*8+0x10] }
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testcase { 0x62, 0xf3, 0x7c, 0x08, 0x08, 0xca, 0x0a }, { vrndscaleph xmm1,xmm2,10 }
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testcase { 0x62, 0xf3, 0x7c, 0x28, 0x08, 0xca, 0x0a }, { vrndscaleph ymm1,ymm2,10 }
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testcase { 0x62, 0xf3, 0x7c, 0x48, 0x08, 0xca, 0x0a }, { vrndscaleph zmm1,zmm2,10 }
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testcase { 0x62, 0xf3, 0x7c, 0x89, 0x08, 0xca, 0x0a }, { vrndscaleph xmm1{k1}{z},xmm2,10 }
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testcase { 0x62, 0xf3, 0x7c, 0xa9, 0x08, 0xca, 0x0a }, { vrndscaleph ymm1{k1}{z},ymm2,10 }
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testcase { 0x62, 0xf3, 0x7c, 0xc9, 0x08, 0xca, 0x0a }, { vrndscaleph zmm1{k1}{z},zmm2,10 }
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testcase { 0x62, 0xf3, 0x6c, 0x08, 0x0a, 0xcb, 0x0a }, { vrndscalesh xmm1,xmm2,xmm3,10 }
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testcase { 0x62, 0xf3, 0x6c, 0x89, 0x0a, 0xcb, 0x0a }, { vrndscalesh xmm1{k1}{z},xmm2,xmm3,10 }
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testcase { 0x62, 0xf3, 0x6c, 0x99, 0x0a, 0xcb, 0x0a }, { vrndscalesh xmm1{k1}{z},xmm2,xmm3,{sae},10 }
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testcase { 0x62, 0xf5, 0x7d, 0x08, 0x1d, 0xca }, { vcvtps2phx xmm1,xmm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x28, 0x1d, 0xca }, { vcvtps2phx xmm1,ymm2 }
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testcase { 0x62, 0xb5, 0x7d, 0x08, 0x1d, 0x4c, 0xf0, 0x01 }, { vcvtps2phx xmm1,[rax+r14*8+0x10] }
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testcase { 0x62, 0xf5, 0x7d, 0x48, 0x1d, 0xca }, { vcvtps2phx ymm1,zmm2 }
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testcase { 0x62, 0xb5, 0x7d, 0x48, 0x1d, 0x8c, 0xf0, 0x10, 0x00, 0x00, 0x00 }, { vcvtps2phx ymm1,[rax+r14*8+0x10] }
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testcase { 0x62, 0xb5, 0x7d, 0xc9, 0x1d, 0x8c, 0xf0, 0x10, 0x00, 0x00, 0x00 }, { vcvtps2phx ymm1{k1}{z},[rax+r14*8+0x10] }
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BIN
travis/test/avx10.1.bin.t
Normal file
BIN
travis/test/avx10.1.bin.t
Normal file
Binary file not shown.
18
travis/test/avx10.1.json
Normal file
18
travis/test/avx10.1.json
Normal file
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[
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{
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"description": "Test AVX10.1 instructions (-Ox)",
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"id": "avx10.1",
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"format": "bin",
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"source": "avx10.1.asm",
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"option": "-Ox -DSRC",
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"target": [
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{ "output": "avx10.1.bin" }
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]
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},
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{
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"description": "Test AVX10.1 instructions (-O0)",
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"ref": "avx10.1",
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"option": "-O0 -DBIN",
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"update": false
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}
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]
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265
travis/test/avx10.2.asm
Normal file
265
travis/test/avx10.2.asm
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;Testname=avx10.2; Arguments=-fbin -oavx10.2.bin -O0 -DSRC; Files=stdout stderr avx10.2.bin
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%macro testcase 2
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%ifdef BIN
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db %1
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%endif
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%ifdef SRC
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%2
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%endif
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%endmacro
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bits 64
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testcase { 0x62, 0xf5, 0x6d, 0x08, 0x58, 0xcb }, { VADDBF16 xmm1, xmm2, xmm3 }
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testcase { 0x62, 0xb5, 0x6d, 0x08, 0x58, 0x4c, 0xf0, 0x01 }, { VADDBF16 xmm1, xmm2, [rax+r14*8+0x10] }
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testcase { 0x62, 0xf5, 0x6d, 0x28, 0x58, 0xcb }, { VADDBF16 ymm1, ymm2, ymm3 }
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testcase { 0x62, 0xf5, 0x6d, 0x48, 0x58, 0xcb }, { VADDBF16 zmm1, zmm2, zmm3 }
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testcase { 0x62, 0xf3, 0x77, 0x08, 0xc2, 0xca, 0x10 }, { VCMPBF16 k1, xmm1, xmm2, 0x10 }
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testcase { 0x62, 0xf3, 0x77, 0x0a, 0xc2, 0xca, 0x10 }, { VCMPBF16 k1{k2}, xmm1, xmm2, 0x10 }
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testcase { 0x62, 0xb3, 0x77, 0x08, 0xc2, 0x54, 0xf0, 0x01, 0x10 }, { VCMPBF16 k2, xmm1, [rax+r14*8+0x10], 0x10 }
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testcase { 0x62, 0xf3, 0x77, 0x28, 0xc2, 0xca, 0x10 }, { VCMPBF16 k1, ymm1, ymm2, 0x10 }
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testcase { 0x62, 0xf3, 0x77, 0x48, 0xc2, 0xca, 0x10 }, { VCMPBF16 k1, zmm1, zmm2, 0x10 }
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testcase { 0x62, 0xf5, 0x7d, 0x08, 0x2f, 0xca }, { VCOMISBF16 xmm1, xmm2 }
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testcase { 0x62, 0xf1, 0xff, 0x08, 0x2f, 0xca }, { VCOMXSD xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7e, 0x08, 0x2f, 0xca }, { VCOMXSH xmm1, xmm2 }
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testcase { 0x62, 0xf1, 0x7e, 0x08, 0x2f, 0xca }, { VCOMXSS xmm1, xmm2 }
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testcase { 0x62, 0xf2, 0x6f, 0x08, 0x74, 0xcb }, { VCVT2PH2BF8 xmm1, xmm2, xmm3 }
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testcase { 0x62, 0xb2, 0x6f, 0x08, 0x74, 0x4c, 0xf0, 0x01 }, { VCVT2PH2BF8 xmm1, xmm2, [rax+r14*8+0x10] }
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testcase { 0x62, 0xf2, 0x6f, 0x28, 0x74, 0xcb }, { VCVT2PH2BF8 ymm1, ymm2, ymm3 }
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testcase { 0x62, 0xf2, 0x6f, 0x48, 0x74, 0xcb }, { VCVT2PH2BF8 zmm1, zmm2, zmm3 }
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testcase { 0x62, 0xf5, 0x6f, 0x08, 0x74, 0xcb }, { VCVT2PH2BF8S xmm1, xmm2, xmm3 }
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testcase { 0x62, 0xb5, 0x6f, 0x08, 0x74, 0x4c, 0xf0, 0x01 }, { VCVT2PH2BF8S xmm1, xmm2, [rax+r14*8+0x10] }
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testcase { 0x62, 0xf5, 0x6f, 0x28, 0x74, 0xcb }, { VCVT2PH2BF8S ymm1, ymm2, ymm3 }
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testcase { 0x62, 0xf5, 0x6f, 0x48, 0x74, 0xcb }, { VCVT2PH2BF8S zmm1, zmm2, zmm3 }
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testcase { 0x62, 0xf5, 0x6f, 0x08, 0x18, 0xcb }, { VCVT2PH2HF8 xmm1, xmm2, xmm3 }
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testcase { 0x62, 0xb5, 0x6f, 0x08, 0x18, 0x4c, 0xf0, 0x01 }, { VCVT2PH2HF8 xmm1, xmm2, [rax+r14*8+0x10] }
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testcase { 0x62, 0xf5, 0x6f, 0x28, 0x18, 0xcb }, { VCVT2PH2HF8 ymm1, ymm2, ymm3 }
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testcase { 0x62, 0xf5, 0x6f, 0x48, 0x18, 0xcb }, { VCVT2PH2HF8 zmm1, zmm2, zmm3 }
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testcase { 0x62, 0xf5, 0x6f, 0x08, 0x1b, 0xcb }, { VCVT2PH2HF8S xmm1, xmm2, xmm3 }
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testcase { 0x62, 0xb5, 0x6f, 0x08, 0x1b, 0x4c, 0xf0, 0x01 }, { VCVT2PH2HF8S xmm1, xmm2, [rax+r14*8+0x10] }
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testcase { 0x62, 0xf5, 0x6f, 0x28, 0x1b, 0xcb }, { VCVT2PH2HF8S ymm1, ymm2, ymm3 }
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testcase { 0x62, 0xf5, 0x6f, 0x48, 0x1b, 0xcb }, { VCVT2PH2HF8S zmm1, zmm2, zmm3 }
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testcase { 0x62, 0xf5, 0x7f, 0x08, 0x69, 0xca }, { VCVTBF162IBS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7f, 0x28, 0x69, 0xca }, { VCVTBF162IBS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7f, 0x48, 0x69, 0xca }, { VCVTBF162IBS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7f, 0x08, 0x6b, 0xca }, { VCVTBF162IUBS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7f, 0x28, 0x6b, 0xca }, { VCVTBF162IUBS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7f, 0x48, 0x6b, 0xca }, { VCVTBF162IUBS zmm1, zmm2 }
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testcase { 0x62, 0xf2, 0x7e, 0x08, 0x74, 0xca }, { VCVTPH2BF8 xmm1, xmm2 }
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testcase { 0x62, 0xf2, 0x7e, 0x28, 0x74, 0xca }, { VCVTPH2BF8 ymm1, ymm2 }
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testcase { 0x62, 0xf2, 0x7e, 0x48, 0x74, 0xca }, { VCVTPH2BF8 zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7e, 0x08, 0x74, 0xca }, { VCVTPH2BF8S xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7e, 0x28, 0x74, 0xca }, { VCVTPH2BF8S ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7e, 0x48, 0x74, 0xca }, { VCVTPH2BF8S zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7e, 0x08, 0x18, 0xca }, { VCVTPH2HF8 xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7e, 0x28, 0x18, 0xca }, { VCVTPH2HF8 ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7e, 0x48, 0x18, 0xca }, { VCVTPH2HF8 zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7e, 0x08, 0x1b, 0xca }, { VCVTPH2HF8S xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7e, 0x28, 0x1b, 0xca }, { VCVTPH2HF8S ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7e, 0x48, 0x1b, 0xca }, { VCVTPH2HF8S zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x08, 0x69, 0xca }, { VCVTPH2IBS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x28, 0x69, 0xca }, { VCVTPH2IBS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x48, 0x69, 0xca }, { VCVTPH2IBS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x08, 0x6b, 0xca }, { VCVTPH2IUBS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x28, 0x6b, 0xca }, { VCVTPH2IUBS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x48, 0x6b, 0xca }, { VCVTPH2IUBS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x08, 0x69, 0xca }, { VCVTPS2IBS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x28, 0x69, 0xca }, { VCVTPS2IBS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x48, 0x69, 0xca }, { VCVTPS2IBS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x08, 0x6b, 0xca }, { VCVTPS2IUBS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x28, 0x6b, 0xca }, { VCVTPS2IUBS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x48, 0x6b, 0xca }, { VCVTPS2IUBS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7f, 0x08, 0x68, 0xca }, { VCVTTBF162IBS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7f, 0x28, 0x68, 0xca }, { VCVTTBF162IBS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7f, 0x48, 0x68, 0xca }, { VCVTTBF162IBS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7f, 0x08, 0x6a, 0xca }, { VCVTTBF162IUBS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7f, 0x28, 0x6a, 0xca }, { VCVTTBF162IUBS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7f, 0x48, 0x6a, 0xca }, { VCVTTBF162IUBS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0xfc, 0x08, 0x6d, 0xca }, { VCVTTPD2DQS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0xfc, 0x28, 0x6d, 0xca }, { VCVTTPD2DQS xmm1, ymm2 }
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testcase { 0x62, 0xf5, 0xfc, 0x48, 0x6d, 0xca }, { VCVTTPD2DQS ymm1, zmm2 }
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testcase { 0x62, 0xf5, 0xfd, 0x08, 0x6d, 0xca }, { VCVTTPD2QQS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0xfd, 0x28, 0x6d, 0xca }, { VCVTTPD2QQS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0xfd, 0x48, 0x6d, 0xca }, { VCVTTPD2QQS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0xfc, 0x08, 0x6c, 0xca }, { VCVTTPD2UDQS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0xfc, 0x28, 0x6c, 0xca }, { VCVTTPD2UDQS xmm1, ymm2 }
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testcase { 0x62, 0xf5, 0xfc, 0x48, 0x6c, 0xca }, { VCVTTPD2UDQS ymm1, zmm2 }
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testcase { 0x62, 0xf5, 0xfd, 0x08, 0x6c, 0xca }, { VCVTTPD2UQQS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0xfd, 0x28, 0x6c, 0xca }, { VCVTTPD2UQQS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0xfd, 0x48, 0x6c, 0xca }, { VCVTTPD2UQQS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x08, 0x68, 0xca }, { VCVTTPH2IBS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x28, 0x68, 0xca }, { VCVTTPH2IBS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x48, 0x68, 0xca }, { VCVTTPH2IBS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x08, 0x6a, 0xca }, { VCVTTPH2IUBS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x28, 0x6a, 0xca }, { VCVTTPH2IUBS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x48, 0x6a, 0xca }, { VCVTTPH2IUBS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x08, 0x6d, 0xca }, { VCVTTPS2DQS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x28, 0x6d, 0xca }, { VCVTTPS2DQS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x48, 0x6d, 0xca }, { VCVTTPS2DQS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x08, 0x68, 0xca }, { VCVTTPS2IBS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x28, 0x68, 0xca }, { VCVTTPS2IBS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x48, 0x68, 0xca }, { VCVTTPS2IBS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x08, 0x6a, 0xca }, { VCVTTPS2IUBS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x28, 0x6a, 0xca }, { VCVTTPS2IUBS ymm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x48, 0x6a, 0xca }, { VCVTTPS2IUBS zmm1, zmm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x08, 0x6d, 0xca }, { VCVTTPS2QQS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x28, 0x6d, 0xca }, { VCVTTPS2QQS ymm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7d, 0x48, 0x6d, 0xca }, { VCVTTPS2QQS zmm1, ymm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x08, 0x6c, 0xca }, { VCVTTPS2UDQS xmm1, xmm2 }
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testcase { 0x62, 0xf5, 0x7c, 0x28, 0x6c, 0xca }, { VCVTTPS2UDQS ymm1, ymm2 }
|
||||
testcase { 0x62, 0xf5, 0x7c, 0x48, 0x6c, 0xca }, { VCVTTPS2UDQS zmm1, zmm2 }
|
||||
testcase { 0x62, 0xf5, 0x7d, 0x08, 0x6c, 0xca }, { VCVTTPS2UQQS xmm1, xmm2 }
|
||||
testcase { 0x62, 0xf5, 0x7d, 0x28, 0x6c, 0xca }, { VCVTTPS2UQQS ymm1, xmm2 }
|
||||
testcase { 0x62, 0xf5, 0x7d, 0x48, 0x6c, 0xca }, { VCVTTPS2UQQS zmm1, ymm2 }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x08, 0x5e, 0xcb }, { VDIVBF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb5, 0x6d, 0x08, 0x5e, 0x4c, 0xf0, 0x01 }, { VDIVBF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x28, 0x5e, 0xcb }, { VDIVBF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x48, 0x5e, 0xcb }, { VDIVBF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6c, 0x08, 0x52, 0xcb }, { VDPPHPS xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6c, 0x28, 0x52, 0xcb }, { VDPPHPS ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf2, 0x6c, 0x48, 0x52, 0xcb }, { VDPPHPS zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0x98, 0xcb }, { VFMADD132BF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0x98, 0x4c, 0xf0, 0x01 }, { VFMADD132BF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0x98, 0xcb }, { VFMADD132BF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0x98, 0xcb }, { VFMADD132BF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0xa8, 0xcb }, { VFMADD213BF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0xa8, 0x4c, 0xf0, 0x01 }, { VFMADD213BF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0xa8, 0xcb }, { VFMADD213BF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0xa8, 0xcb }, { VFMADD213BF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0xb8, 0xcb }, { VFMADD231BF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0xb8, 0x4c, 0xf0, 0x01 }, { VFMADD231BF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0xb8, 0xcb }, { VFMADD231BF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0xb8, 0xcb }, { VFMADD231BF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0x9a, 0xcb }, { VFMSUB132BF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0x9a, 0x4c, 0xf0, 0x01 }, { VFMSUB132BF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0x9a, 0xcb }, { VFMSUB132BF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0x9a, 0xcb }, { VFMSUB132BF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0xaa, 0xcb }, { VFMSUB213BF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0xaa, 0x4c, 0xf0, 0x01 }, { VFMSUB213BF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0xaa, 0xcb }, { VFMSUB213BF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0xaa, 0xcb }, { VFMSUB213BF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0xba, 0xcb }, { VFMSUB231BF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0xba, 0x4c, 0xf0, 0x01 }, { VFMSUB231BF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0xba, 0xcb }, { VFMSUB231BF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0xba, 0xcb }, { VFMSUB231BF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0x9c, 0xcb }, { VFNMADD132BF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0x9c, 0x4c, 0xf0, 0x01 }, { VFNMADD132BF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0x9c, 0xcb }, { VFNMADD132BF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0x9c, 0xcb }, { VFNMADD132BF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0xac, 0xcb }, { VFNMADD213BF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0xac, 0x4c, 0xf0, 0x01 }, { VFNMADD213BF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0xac, 0xcb }, { VFNMADD213BF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0xac, 0xcb }, { VFNMADD213BF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0xbc, 0xcb }, { VFNMADD231BF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0xbc, 0x4c, 0xf0, 0x01 }, { VFNMADD231BF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0xbc, 0xcb }, { VFNMADD231BF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0xbc, 0xcb }, { VFNMADD231BF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0x9e, 0xcb }, { VFNMSUB132BF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0x9e, 0x4c, 0xf0, 0x01 }, { VFNMSUB132BF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0x9e, 0xcb }, { VFNMSUB132BF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0x9e, 0xcb }, { VFNMSUB132BF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0xae, 0xcb }, { VFNMSUB213BF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0xae, 0x4c, 0xf0, 0x01 }, { VFNMSUB213BF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0xae, 0xcb }, { VFNMSUB213BF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0xae, 0xcb }, { VFNMSUB213BF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0xbe, 0xcb }, { VFNMSUB231BF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0xbe, 0x4c, 0xf0, 0x01 }, { VFNMSUB231BF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0xbe, 0xcb }, { VFNMSUB231BF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0xbe, 0xcb }, { VFNMSUB231BF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf3, 0x7f, 0x08, 0x66, 0xc9, 0x10 }, { VFPCLASSBF16 k1, xmm1, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x7f, 0x28, 0x66, 0xc9, 0x10 }, { VFPCLASSBF16 k1, ymm1, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x7f, 0x48, 0x66, 0xc9, 0x10 }, { VFPCLASSBF16 k1, zmm1, 0x10 }
|
||||
testcase { 0x62, 0xf6, 0x7c, 0x08, 0x42, 0xca }, { VGETEXPBF16 xmm1, xmm2 }
|
||||
testcase { 0x62, 0xf6, 0x7c, 0x28, 0x42, 0xca }, { VGETEXPBF16 ymm1, ymm2 }
|
||||
testcase { 0x62, 0xf6, 0x7c, 0x48, 0x42, 0xca }, { VGETEXPBF16 zmm1, zmm2 }
|
||||
testcase { 0x62, 0xf3, 0x7f, 0x08, 0x26, 0xca, 0x10 }, { VGETMANTBF16 xmm1, xmm2, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x7f, 0x28, 0x26, 0xca, 0x10 }, { VGETMANTBF16 ymm1, ymm2, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x7f, 0x48, 0x26, 0xca, 0x10 }, { VGETMANTBF16 zmm1, zmm2, 0x10 }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x08, 0x5f, 0xcb }, { VMAXBF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb5, 0x6d, 0x08, 0x5f, 0x4c, 0xf0, 0x01 }, { VMAXBF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x28, 0x5f, 0xcb }, { VMAXBF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x48, 0x5f, 0xcb }, { VMAXBF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x08, 0x5d, 0xcb }, { VMINBF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb5, 0x6d, 0x08, 0x5d, 0x4c, 0xf0, 0x01 }, { VMINBF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x28, 0x5d, 0xcb }, { VMINBF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x48, 0x5d, 0xcb }, { VMINBF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf3, 0x6f, 0x08, 0x52, 0xcb, 0x10 }, { VMINMAXBF16 xmm1, xmm2, xmm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x6f, 0x28, 0x52, 0xcb, 0x10 }, { VMINMAXBF16 ymm1, ymm2, ymm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x6f, 0x48, 0x52, 0xcb, 0x10 }, { VMINMAXBF16 zmm1, zmm2, zmm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0xed, 0x08, 0x52, 0xcb, 0x10 }, { VMINMAXPD xmm1, xmm2, xmm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0xed, 0x28, 0x52, 0xcb, 0x10 }, { VMINMAXPD ymm1, ymm2, ymm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0xed, 0x48, 0x52, 0xcb, 0x10 }, { VMINMAXPD zmm1, zmm2, zmm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x6c, 0x08, 0x52, 0xcb, 0x10 }, { VMINMAXPH xmm1, xmm2, xmm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x6c, 0x28, 0x52, 0xcb, 0x10 }, { VMINMAXPH ymm1, ymm2, ymm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x6c, 0x48, 0x52, 0xcb, 0x10 }, { VMINMAXPH zmm1, zmm2, zmm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x6d, 0x08, 0x52, 0xcb, 0x10 }, { VMINMAXPS xmm1, xmm2, xmm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x6d, 0x28, 0x52, 0xcb, 0x10 }, { VMINMAXPS ymm1, ymm2, ymm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x6d, 0x48, 0x52, 0xcb, 0x10 }, { VMINMAXPS zmm1, zmm2, zmm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0xed, 0x08, 0x53, 0xcb, 0x10 }, { VMINMAXSD xmm1, xmm2, xmm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x6c, 0x08, 0x53, 0xcb, 0x10 }, { VMINMAXSH xmm1, xmm2, xmm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x6d, 0x08, 0x53, 0xcb, 0x10 }, { VMINMAXSS xmm1, xmm2, xmm3, 0x10 }
|
||||
testcase { 0x62, 0xf1, 0x7e, 0x08, 0x7e, 0xca }, { VMOVD xmm1, xmm2 }
|
||||
testcase { 0x62, 0xf1, 0x7e, 0x08, 0x7e, 0xca }, { VMOVD xmm1, xmm2 }
|
||||
testcase { 0x62, 0xf5, 0x7e, 0x08, 0x6e, 0xca }, { VMOVW xmm1, xmm2 }
|
||||
testcase { 0x62, 0xf5, 0x7e, 0x08, 0x6e, 0xca }, { VMOVW xmm1, xmm2 }
|
||||
testcase { 0xc4, 0xe3, 0x69, 0x42, 0xcb, 0x10 }, { VMPSADBW xmm1, xmm2, xmm3, 0x10 }
|
||||
testcase { 0xc4, 0xe3, 0x6d, 0x42, 0xcb, 0x10 }, { VMPSADBW ymm1, ymm2, ymm3, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x6e, 0x48, 0x42, 0xcb, 0x10 }, { VMPSADBW zmm1, zmm2, zmm3, 0x10 }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x08, 0x59, 0xcb }, { VMULBF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb5, 0x6d, 0x08, 0x59, 0x4c, 0xf0, 0x01 }, { VMULBF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x28, 0x59, 0xcb }, { VMULBF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x48, 0x59, 0xcb }, { VMULBF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6f, 0x08, 0x50, 0xcb }, { VPDPBSSD xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6f, 0x28, 0x50, 0xcb }, { VPDPBSSD ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf2, 0x6f, 0x48, 0x50, 0xcb }, { VPDPBSSD zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6f, 0x08, 0x51, 0xcb }, { VPDPBSSDS xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6f, 0x28, 0x51, 0xcb }, { VPDPBSSDS ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf2, 0x6f, 0x48, 0x51, 0xcb }, { VPDPBSSDS zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6e, 0x08, 0x50, 0xcb }, { VPDPBSUD xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6e, 0x28, 0x50, 0xcb }, { VPDPBSUD ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf2, 0x6e, 0x48, 0x50, 0xcb }, { VPDPBSUD zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6e, 0x08, 0x51, 0xcb }, { VPDPBSUDS xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6e, 0x28, 0x51, 0xcb }, { VPDPBSUDS ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf2, 0x6e, 0x48, 0x51, 0xcb }, { VPDPBSUDS zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6c, 0x08, 0x50, 0xcb }, { VPDPBUUD xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6c, 0x28, 0x50, 0xcb }, { VPDPBUUD ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf2, 0x6c, 0x48, 0x50, 0xcb }, { VPDPBUUD zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6c, 0x08, 0x51, 0xcb }, { VPDPBUUDS xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xf2, 0x6c, 0x28, 0x51, 0xcb }, { VPDPBUUDS ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf2, 0x6c, 0x48, 0x51, 0xcb }, { VPDPBUUDS zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf6, 0x7c, 0x08, 0x4c, 0xca }, { VRCPBF16 xmm1, xmm2 }
|
||||
testcase { 0x62, 0xf6, 0x7c, 0x28, 0x4c, 0xca }, { VRCPBF16 ymm1, ymm2 }
|
||||
testcase { 0x62, 0xf6, 0x7c, 0x48, 0x4c, 0xca }, { VRCPBF16 zmm1, zmm2 }
|
||||
testcase { 0x62, 0xf3, 0x7f, 0x08, 0x56, 0xca, 0x10 }, { VREDUCEBF16 xmm1, xmm2, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x7f, 0x28, 0x56, 0xca, 0x10 }, { VREDUCEBF16 ymm1, ymm2, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x7f, 0x48, 0x56, 0xca, 0x10 }, { VREDUCEBF16 zmm1, zmm2, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x7f, 0x08, 0x08, 0xca, 0x10 }, { VRNDSCALEBF16 xmm1, xmm2, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x7f, 0x28, 0x08, 0xca, 0x10 }, { VRNDSCALEBF16 ymm1, ymm2, 0x10 }
|
||||
testcase { 0x62, 0xf3, 0x7f, 0x48, 0x08, 0xca, 0x10 }, { VRNDSCALEBF16 zmm1, zmm2, 0x10 }
|
||||
testcase { 0x62, 0xf6, 0x7c, 0x08, 0x4e, 0xca }, { VRSQRTBF16 xmm1, xmm2 }
|
||||
testcase { 0x62, 0xf6, 0x7c, 0x28, 0x4e, 0xca }, { VRSQRTBF16 ymm1, ymm2 }
|
||||
testcase { 0x62, 0xf6, 0x7c, 0x48, 0x4e, 0xca }, { VRSQRTBF16 zmm1, zmm2 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x08, 0x2c, 0xcb }, { VSCALEFBF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb6, 0x6c, 0x08, 0x2c, 0x4c, 0xf0, 0x01 }, { VSCALEFBF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x28, 0x2c, 0xcb }, { VSCALEFBF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf6, 0x6c, 0x48, 0x2c, 0xcb }, { VSCALEFBF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf5, 0x7d, 0x08, 0x51, 0xca }, { VSQRTBF16 xmm1, xmm2 }
|
||||
testcase { 0x62, 0xf5, 0x7d, 0x28, 0x51, 0xca }, { VSQRTBF16 ymm1, ymm2 }
|
||||
testcase { 0x62, 0xf5, 0x7d, 0x48, 0x51, 0xca }, { VSQRTBF16 zmm1, zmm2 }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x08, 0x5c, 0xcb }, { VSUBBF16 xmm1, xmm2, xmm3 }
|
||||
testcase { 0x62, 0xb5, 0x6d, 0x08, 0x5c, 0x4c, 0xf0, 0x01 }, { VSUBBF16 xmm1, xmm2, [rax+r14*8+0x10] }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x28, 0x5c, 0xcb }, { VSUBBF16 ymm1, ymm2, ymm3 }
|
||||
testcase { 0x62, 0xf5, 0x6d, 0x48, 0x5c, 0xcb }, { VSUBBF16 zmm1, zmm2, zmm3 }
|
||||
testcase { 0x62, 0xf1, 0xff, 0x08, 0x2e, 0xca }, { VUCOMXSD xmm1, xmm2 }
|
||||
testcase { 0x62, 0xf5, 0x7e, 0x08, 0x2e, 0xca }, { VUCOMXSH xmm1, xmm2 }
|
||||
testcase { 0x62, 0xf1, 0x7e, 0x08, 0x2e, 0xca }, { VUCOMXSS xmm1, xmm2 }
|
||||
testcase { 0x62, 0xf5, 0x7f, 0x08, 0x6d, 0xc1 }, { VCVTTSD2SIS eax, xmm1 }
|
||||
testcase { 0x62, 0xf5, 0xff, 0x08, 0x6d, 0xc1 }, { VCVTTSD2SIS rax, xmm1 }
|
||||
testcase { 0x62, 0xf5, 0x7f, 0x08, 0x6c, 0xc1 }, { VCVTTSD2USIS eax, xmm1 }
|
||||
testcase { 0x62, 0xf5, 0xff, 0x08, 0x6c, 0xc1 }, { VCVTTSD2USIS rax, xmm1 }
|
||||
testcase { 0x62, 0xf5, 0x7e, 0x08, 0x6d, 0xc1 }, { VCVTTSS2SIS eax, xmm1 }
|
||||
testcase { 0x62, 0xf5, 0xfe, 0x08, 0x6d, 0xc1 }, { VCVTTSS2SIS rax, xmm1 }
|
||||
testcase { 0x62, 0xf5, 0x7e, 0x08, 0x6c, 0xc1 }, { VCVTTSS2USIS eax, xmm1 }
|
||||
testcase { 0x62, 0xf5, 0xfe, 0x08, 0x6c, 0xc1 }, { VCVTTSS2USIS rax, xmm1 }
|
||||
2
travis/test/avx10.2.bin.t
Normal file
2
travis/test/avx10.2.bin.t
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
bőmXËbµmXLđbőm(XËbőmHXËbówÂĘbów
|
||||
ÂĘbłwÂTđbów(ÂĘbówHÂĘbő}/Ębń˙/Ębő~/Ębń~/ĘbňotËb˛otLđbňo(tËbňoHtËbőotËbµotLđbőo(tËbőoHtËbőoËbµoLđbőo(ËbőoHËbőoËbµoLđbőo(ËbőoHËbőiĘbő(iĘbőHiĘbőkĘbő(kĘbőHkĘbň~tĘbň~(tĘbň~HtĘbő~tĘbő~(tĘbő~HtĘbő~Ębő~(Ębő~HĘbő~Ębő~(Ębő~HĘbő|iĘbő|(iĘbő|HiĘbő|kĘbő|(kĘbő|HkĘbő}iĘbő}(iĘbő}HiĘbő}kĘbő}(kĘbő}HkĘbőhĘbő(hĘbőHhĘbőjĘbő(jĘbőHjĘbőümĘbőü(mĘbőüHmĘbőýmĘbőý(mĘbőýHmĘbőülĘbőü(lĘbőüHlĘbőýlĘbőý(lĘbőýHlĘbő|hĘbő|(hĘbő|HhĘbő|jĘbő|(jĘbő|HjĘbő|mĘbő|(mĘbő|HmĘbő}hĘbő}(hĘbő}HhĘbő}jĘbő}(jĘbő}HjĘbő}mĘbő}(mĘbő}HmĘbő|lĘbő|(lĘbő|HlĘbő}lĘbő}(lĘbő}HlĘbőm^Ëbµm^Lđbőm(^ËbőmH^ËbňlRËbňl(RËbňlHRËböl<EFBFBD>Ëb¶l<EFBFBD>Lđböl(<EFBFBD>ËbölH<EFBFBD>Ëböl¨Ëb¶l¨Lđböl(¨ËbölH¨Ëböl¸Ëb¶l¸Lđböl(¸ËbölH¸ËbölšËb¶lšLđböl(šËbölHšËbölŞËb¶lŞLđböl(ŞËbölHŞËbölşËb¶lşLđböl(şËbölHşËbölśËb¶lśLđböl(śËbölHśËböl¬Ëb¶l¬Lđböl(¬ËbölH¬ËbölĽËb¶lĽLđböl(ĽËbölHĽËbölžËb¶lžLđböl(žËbölHžËböl®Ëb¶l®Lđböl(®ËbölH®ËbölľËb¶lľLđböl(ľËbölHľËbófÉbó(fÉbóHfÉbö|BĘbö|(BĘbö|HBĘbó&Ębó(&ĘbóH&Ębőm_Ëbµm_Lđbőm(_ËbőmH_Ëbőm]Ëbµm]Lđbőm(]ËbőmH]ËbóoRËbóo(RËbóoHRËbóíRËbóí(RËbóíHRËbólRËból(RËbólHRËbómRËbóm(RËbómHRËbóíSËbólSËbómSËbń~~Ębń~~Ębő~nĘbő~nĘÄăiBËÄămBËbónHBËbőmYËbµmYLđbőm(YËbőmHYËbňoPËbňo(PËbňoHPËbňoQËbňo(QËbňoHQËbňnPËbňn(PËbňnHPËbňnQËbňn(QËbňnHQËbňlPËbňl(PËbňlHPËbňlQËbňl(QËbňlHQËbö|LĘbö|(LĘbö|HLĘbóVĘbó(VĘbóHVĘbóĘbó(ĘbóHĘbö|NĘbö|(NĘbö|HNĘböl,Ëb¶l,Lđböl(,ËbölH,Ëbő}QĘbő}(QĘbő}HQĘbőm\Ëbµm\Lđbőm(\ËbőmH\Ëbń˙.Ębő~.Ębń~.ĘbőmÁbő˙mÁbőlÁbő˙lÁbő~mÁbőţmÁbő~lÁbőţlÁ
|
||||
19
travis/test/avx10.2.json
Normal file
19
travis/test/avx10.2.json
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
[
|
||||
{
|
||||
"description": "Test AVX10.2 instructions (-Ox)",
|
||||
"id": "avx10.2",
|
||||
"format": "bin",
|
||||
"source": "avx10.2.asm",
|
||||
"option": "-Ox -DSRC",
|
||||
"target": [
|
||||
{ "output": "avx10.2.bin" }
|
||||
]
|
||||
},
|
||||
{
|
||||
"description": "Test AVX10.2 instructions (-O0)",
|
||||
"ref": "avx10.2",
|
||||
"option": "-O0 -DBIN",
|
||||
"update": false
|
||||
}
|
||||
]
|
||||
|
||||
249
x86/insns.dat
249
x86/insns.dat
|
|
@ -3820,6 +3820,9 @@ VINSERTPS xmmreg,xmmreg*,xmmrm32,imm8 [rvmi:t1s: evex.nds.128.66.0
|
|||
VMAXPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 5f /r ] AVX512VL,AVX512
|
||||
VMAXPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 5f /r ] AVX512VL,AVX512
|
||||
VMAXPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 5f /r ] AVX512
|
||||
VMAXPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.128.np.map5.w0 5f /r ] AVX512VL,AVX512FP16
|
||||
VMAXPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.256.np.map5.w0 5f /r ] AVX512VL,AVX512FP16
|
||||
VMAXPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|sae [rvm:fv: evex.512.np.map5.w0 5f /r ] AVX512FP16
|
||||
VMAXPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 5f /r ] AVX512VL,AVX512
|
||||
VMAXPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 5f /r ] AVX512VL,AVX512
|
||||
VMAXPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 5f /r ] AVX512
|
||||
|
|
@ -3828,6 +3831,9 @@ VMAXSS xmmreg|mask|z,xmmreg*,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f
|
|||
VMINPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 5d /r ] AVX512VL,AVX512
|
||||
VMINPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 5d /r ] AVX512VL,AVX512
|
||||
VMINPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 5d /r ] AVX512
|
||||
VMINPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.128.np.map5.w0 5d /r ] AVX512VL,AVX512FP16
|
||||
VMINPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.256.np.map5.w0 5d /r ] AVX512VL,AVX512FP16
|
||||
VMINPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|sae [rvm:fv: evex.512.np.map5.w0 5d /r ] AVX512FP16
|
||||
VMINPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 5d /r ] AVX512VL,AVX512
|
||||
VMINPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 5d /r ] AVX512VL,AVX512
|
||||
VMINPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 5d /r ] AVX512
|
||||
|
|
@ -5011,10 +5017,14 @@ VREDUCESS xmmreg|mask|z,xmmreg*,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.lig.6
|
|||
VRNDSCALEPD xmmreg|mask|z,xmmrm128|b64,imm8 [rmi:fv: evex.128.66.0f3a.w1 09 /r ib ] AVX512VL,AVX512
|
||||
VRNDSCALEPD ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv: evex.256.66.0f3a.w1 09 /r ib ] AVX512VL,AVX512
|
||||
VRNDSCALEPD zmmreg|mask|z,zmmrm512|b64|sae,imm8 [rmi:fv: evex.512.66.0f3a.w1 09 /r ib ] AVX512
|
||||
VRNDSCALEPH xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv: evex.128.np.0f3a.w0 08 /r ib ] AVX512VL,AVX512FP16
|
||||
VRNDSCALEPH ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv: evex.256.np.0f3a.w0 08 /r ib ] AVX512VL,AVX512FP16
|
||||
VRNDSCALEPH zmmreg|mask|z,zmmrm512|b16|sae,imm8 [rmi:fv: evex.512.np.0f3a.w0 08 /r ib ] AVX512FP16
|
||||
VRNDSCALEPS xmmreg|mask|z,xmmrm128|b32,imm8 [rmi:fv: evex.128.66.0f3a.w0 08 /r ib ] AVX512VL,AVX512
|
||||
VRNDSCALEPS ymmreg|mask|z,ymmrm256|b32,imm8 [rmi:fv: evex.256.66.0f3a.w0 08 /r ib ] AVX512VL,AVX512
|
||||
VRNDSCALEPS zmmreg|mask|z,zmmrm512|b32|sae,imm8 [rmi:fv: evex.512.66.0f3a.w0 08 /r ib ] AVX512
|
||||
VRNDSCALESD xmmreg|mask|z,xmmreg*,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w1 0b /r ib ] AVX512
|
||||
VRNDSCALESH xmmreg|mask|z,xmmreg*,xmmrm16|sae,imm8 [rvmi:t1s: evex.nds.lig.np.0f3a.w0 0a /r ib ] AVX512FP16
|
||||
VRNDSCALESS xmmreg|mask|z,xmmreg*,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w0 0a /r ib ] AVX512
|
||||
VRSQRT14PD xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f38.w1 4e /r ] AVX512VL,AVX512
|
||||
VRSQRT14PD ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f38.w1 4e /r ] AVX512VL,AVX512
|
||||
|
|
@ -5364,6 +5374,9 @@ VCVTPS2PH mem256|mask,zmmreg|sae,imm8 [mri:hvm: evex.512.66.0f3a.w0 1d /r ib] AV
|
|||
VCVTPS2PH xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.map5.w0 1d /r] AVX512FP16,AVX512VL
|
||||
VCVTPS2PH ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.map5.w0 1d /r] AVX512FP16,AVX512VL
|
||||
VCVTPS2PH zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.66.map5.w0 1d /r] AVX512FP16
|
||||
VCVTPS2PHX xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.map5.w0 1d /r] AVX512FP16,AVX512VL
|
||||
VCVTPS2PHX xmmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.map5.w0 1d /r] AVX512FP16,AVX512VL
|
||||
VCVTPS2PHX ymmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.66.map5.w0 1d /r] AVX512FP16
|
||||
VCVTQQ2PH xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.np.map5.w1 5b /r] AVX512FP16,AVX512VL
|
||||
VCVTQQ2PH ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.np.map5.w1 5b /r] AVX512FP16,AVX512VL
|
||||
VCVTQQ2PH zmmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.np.map5.w1 5b /r] AVX512FP16,AVX512VL
|
||||
|
|
@ -5588,3 +5601,239 @@ HRESET imm [i: f3 0f3a f0 c0 ib ] HRESET,PRIV,SB,ND
|
|||
$wdq NOP imm,reg#,rm# [irm: o# 0f ibn /r] P6,UNDOC,SM1-2
|
||||
$wdq HINT_NOP imm,reg#,rm# [irm: o# 0f ibn /r] P6,UNDOC,SM1-2,ND
|
||||
$hint_nops
|
||||
|
||||
;# AVX10.2 BF16 instructions
|
||||
VADDBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.66.map5.w0 58 /r ] AVX10_2
|
||||
VADDBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.66.map5.w0 58 /r ] AVX10_2
|
||||
VADDBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.66.map5.w0 58 /r ] AVX10_2
|
||||
VCMPBF16 kreg|mask,xmmreg,xmmrm128|b16,imm8 [rvmi:fv: evex.128.f2.0f3a.w0 c2 /r ib] AVX10_2
|
||||
VCMPBF16 kreg|mask,ymmreg,ymmrm256|b16,imm8 [rvmi:fv: evex.256.f2.0f3a.w0 c2 /r ib] AVX10_2
|
||||
VCMPBF16 kreg|mask,zmmreg,zmmrm512|b16,imm8 [rvmi:fv: evex.512.f2.0f3a.w0 c2 /r ib] AVX10_2
|
||||
VCOMISBF16 xmmreg,xmmrm16 [rm:t1s: evex.lig.66.map5.w0 2f /r] AVX10_2
|
||||
VDIVBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.66.map5.w0 5e /r ] AVX10_2
|
||||
VDIVBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.66.map5.w0 5e /r ] AVX10_2
|
||||
VDIVBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.66.map5.w0 5e /r ] AVX10_2
|
||||
VFMADD132BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 98 /r ] AVX10_2
|
||||
VFMADD132BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 98 /r ] AVX10_2
|
||||
VFMADD132BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 98 /r ] AVX10_2
|
||||
VFMADD213BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 a8 /r ] AVX10_2
|
||||
VFMADD213BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 a8 /r ] AVX10_2
|
||||
VFMADD213BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 a8 /r ] AVX10_2
|
||||
VFMADD231BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 b8 /r ] AVX10_2
|
||||
VFMADD231BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 b8 /r ] AVX10_2
|
||||
VFMADD231BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 b8 /r ] AVX10_2
|
||||
VFMSUB132BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 9a /r ] AVX10_2
|
||||
VFMSUB132BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 9a /r ] AVX10_2
|
||||
VFMSUB132BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 9a /r ] AVX10_2
|
||||
VFMSUB213BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 aa /r ] AVX10_2
|
||||
VFMSUB213BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 aa /r ] AVX10_2
|
||||
VFMSUB213BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 aa /r ] AVX10_2
|
||||
VFMSUB231BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 ba /r ] AVX10_2
|
||||
VFMSUB231BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 ba /r ] AVX10_2
|
||||
VFMSUB231BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 ba /r ] AVX10_2
|
||||
VFNMADD132BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 9c /r ] AVX10_2
|
||||
VFNMADD132BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 9c /r ] AVX10_2
|
||||
VFNMADD132BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 9c /r ] AVX10_2
|
||||
VFNMADD213BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 ac /r ] AVX10_2
|
||||
VFNMADD213BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 ac /r ] AVX10_2
|
||||
VFNMADD213BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 ac /r ] AVX10_2
|
||||
VFNMADD231BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 bc /r ] AVX10_2
|
||||
VFNMADD231BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 bc /r ] AVX10_2
|
||||
VFNMADD231BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 bc /r ] AVX10_2
|
||||
VFNMSUB132BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 9e /r ] AVX10_2
|
||||
VFNMSUB132BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 9e /r ] AVX10_2
|
||||
VFNMSUB132BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 9e /r ] AVX10_2
|
||||
VFNMSUB213BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 ae /r ] AVX10_2
|
||||
VFNMSUB213BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 ae /r ] AVX10_2
|
||||
VFNMSUB213BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 ae /r ] AVX10_2
|
||||
VFNMSUB231BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 be /r ] AVX10_2
|
||||
VFNMSUB231BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 be /r ] AVX10_2
|
||||
VFNMSUB231BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 be /r ] AVX10_2
|
||||
VFPCLASSBF16 kreg|mask,xmmrm128|b16,imm8 [rmi:fv: evex.128.f2.0f3a.w0 66 /r ib ] AVX10_2
|
||||
VFPCLASSBF16 kreg|mask,ymmrm256|b16,imm8 [rmi:fv: evex.256.f2.0f3a.w0 66 /r ib ] AVX10_2
|
||||
VFPCLASSBF16 kreg|mask,zmmrm512|b16,imm8 [rmi:fv: evex.512.f2.0f3a.w0 66 /r ib ] AVX10_2
|
||||
VGETEXPBF16 xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.np.map6.w0 42 /r ] AVX10_2
|
||||
VGETEXPBF16 ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.np.map6.w0 42 /r ] AVX10_2
|
||||
VGETEXPBF16 zmmreg|mask|z,zmmrm512|b16 [rm:fv: evex.512.np.map6.w0 42 /r ] AVX10_2
|
||||
VGETMANTBF16 xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv: evex.128.f2.0f3a.w0 26 /r ib] AVX10_2
|
||||
VGETMANTBF16 ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv: evex.256.f2.0f3a.w0 26 /r ib] AVX10_2
|
||||
VGETMANTBF16 zmmreg|mask|z,zmmrm512|b16,imm8 [rmi:fv: evex.512.f2.0f3a.w0 26 /r ib] AVX10_2
|
||||
VMAXBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.66.map5.w0 5f /r ] AVX10_2
|
||||
VMAXBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.66.map5.w0 5f /r ] AVX10_2
|
||||
VMAXBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.66.map5.w0 5f /r ] AVX10_2
|
||||
VMINBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.66.map5.w0 5d /r ] AVX10_2
|
||||
VMINBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.66.map5.w0 5d /r ] AVX10_2
|
||||
VMINBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.66.map5.w0 5d /r ] AVX10_2
|
||||
VMULBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.66.map5.w0 59 /r ] AVX10_2
|
||||
VMULBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.66.map5.w0 59 /r ] AVX10_2
|
||||
VMULBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.66.map5.w0 59 /r ] AVX10_2
|
||||
VRCPBF16 xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.np.map6.w0 4c /r ] AVX10_2
|
||||
VRCPBF16 ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.np.map6.w0 4c /r ] AVX10_2
|
||||
VRCPBF16 zmmreg|mask|z,zmmrm512|b16 [rm:fv: evex.512.np.map6.w0 4c /r ] AVX10_2
|
||||
VREDUCEBF16 xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv: evex.128.f2.0f3a.w0 56 /r ib] AVX10_2
|
||||
VREDUCEBF16 ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv: evex.256.f2.0f3a.w0 56 /r ib] AVX10_2
|
||||
VREDUCEBF16 zmmreg|mask|z,zmmrm512|b16,imm8 [rmi:fv: evex.512.f2.0f3a.w0 56 /r ib] AVX10_2
|
||||
VRNDSCALEBF16 xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv: evex.128.f2.0f3a.w0 08 /r ib] AVX10_2
|
||||
VRNDSCALEBF16 ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv: evex.256.f2.0f3a.w0 08 /r ib] AVX10_2
|
||||
VRNDSCALEBF16 zmmreg|mask|z,zmmrm512|b16,imm8 [rmi:fv: evex.512.f2.0f3a.w0 08 /r ib] AVX10_2
|
||||
VRSQRTBF16 xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.np.map6.w0 4e /r ] AVX10_2
|
||||
VRSQRTBF16 ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.np.map6.w0 4e /r ] AVX10_2
|
||||
VRSQRTBF16 zmmreg|mask|z,zmmrm512|b16 [rm:fv: evex.512.np.map6.w0 4e /r ] AVX10_2
|
||||
VSCALEFBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.np.map6.w0 2c /r ] AVX10_2
|
||||
VSCALEFBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.np.map6.w0 2c /r ] AVX10_2
|
||||
VSCALEFBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.np.map6.w0 2c /r ] AVX10_2
|
||||
VSQRTBF16 xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.66.map5.w0 51 /r ] AVX10_2
|
||||
VSQRTBF16 ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.66.map5.w0 51 /r ] AVX10_2
|
||||
VSQRTBF16 zmmreg|mask|z,zmmrm512|b16 [rm:fv: evex.512.66.map5.w0 51 /r ] AVX10_2
|
||||
VSUBBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.66.map5.w0 5c /r ] AVX10_2
|
||||
VSUBBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.66.map5.w0 5c /r ] AVX10_2
|
||||
VSUBBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.66.map5.w0 5c /r ] AVX10_2
|
||||
|
||||
;# AVX10.2 Compare scalar fp with enhanced eflags instructions
|
||||
VCOMXSD xmmreg,xmmrm64|sae [rm:t1s: evex.lig.f2.0f.w1 2f /r ] AVX10_2
|
||||
VCOMXSH xmmreg,xmmrm16|sae [rm:t1s: evex.lig.f3.map5.w0 2f /r ] AVX10_2
|
||||
VCOMXSS xmmreg,xmmrm32|sae [rm:t1s: evex.lig.f3.0f.w0 2f /r ] AVX10_2
|
||||
VUCOMXSD xmmreg,xmmrm64|sae [rm:t1s: evex.lig.f2.0f.w1 2e /r ] AVX10_2
|
||||
VUCOMXSH xmmreg,xmmrm16|sae [rm:t1s: evex.lig.f3.map5.w0 2e /r ] AVX10_2
|
||||
VUCOMXSS xmmreg,xmmrm32|sae [rm:t1s: evex.lig.f3.0f.w0 2e /r ] AVX10_2
|
||||
|
||||
;# AVX10.2 Convert instructions
|
||||
VCVT2PH2BF8 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.f2.0f38.w0 74 /r ] AVX10_2
|
||||
VCVT2PH2BF8 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.f2.0f38.w0 74 /r ] AVX10_2
|
||||
VCVT2PH2BF8 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.f2.0f38.w0 74 /r ] AVX10_2
|
||||
VCVT2PH2BF8S xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.f2.map5.w0 74 /r ] AVX10_2
|
||||
VCVT2PH2BF8S ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.f2.map5.w0 74 /r ] AVX10_2
|
||||
VCVT2PH2BF8S zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.f2.map5.w0 74 /r ] AVX10_2
|
||||
VCVT2PH2HF8 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.f2.map5.w0 18 /r ] AVX10_2
|
||||
VCVT2PH2HF8 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.f2.map5.w0 18 /r ] AVX10_2
|
||||
VCVT2PH2HF8 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.f2.map5.w0 18 /r ] AVX10_2
|
||||
VCVT2PH2HF8S xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv: evex.128.f2.map5.w0 1b /r ] AVX10_2
|
||||
VCVT2PH2HF8S ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv: evex.256.f2.map5.w0 1b /r ] AVX10_2
|
||||
VCVT2PH2HF8S zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv: evex.512.f2.map5.w0 1b /r ] AVX10_2
|
||||
VCVTPH2BF8 xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.f3.0f38.w0 74 /r ] AVX10_2
|
||||
VCVTPH2BF8 ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.f3.0f38.w0 74 /r ] AVX10_2
|
||||
VCVTPH2BF8 zmmreg|mask|z,zmmrm512|b16 [rm:fv: evex.512.f3.0f38.w0 74 /r ] AVX10_2
|
||||
VCVTPH2BF8S xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.f3.map5.w0 74 /r ] AVX10_2
|
||||
VCVTPH2BF8S ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.f3.map5.w0 74 /r ] AVX10_2
|
||||
VCVTPH2BF8S zmmreg|mask|z,zmmrm512|b16 [rm:fv: evex.512.f3.map5.w0 74 /r ] AVX10_2
|
||||
VCVTPH2HF8 xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.f3.map5.w0 18 /r ] AVX10_2
|
||||
VCVTPH2HF8 ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.f3.map5.w0 18 /r ] AVX10_2
|
||||
VCVTPH2HF8 zmmreg|mask|z,zmmrm512|b16 [rm:fv: evex.512.f3.map5.w0 18 /r ] AVX10_2
|
||||
VCVTPH2HF8S xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.f3.map5.w0 1b /r ] AVX10_2
|
||||
VCVTPH2HF8S ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.f3.map5.w0 1b /r ] AVX10_2
|
||||
VCVTPH2HF8S zmmreg|mask|z,zmmrm512|b16 [rm:fv: evex.512.f3.map5.w0 1b /r ] AVX10_2
|
||||
|
||||
;# AVX10.2 Integer and FP16 VNNI, media new instructions
|
||||
VDPPHPS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.128.np.0f38.w0 52 /r ] AVX10_2
|
||||
VDPPHPS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.256.np.0f38.w0 52 /r ] AVX10_2
|
||||
VDPPHPS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.512.np.0f38.w0 52 /r ] AVX10_2
|
||||
VMPSADBW xmmreg|mask|z,xmmreg,xmmrm128,imm8 [rvmi:fvm: evex.128.f3.0f3a.w0 42 /r ib] AVX10_2
|
||||
VMPSADBW ymmreg|mask|z,ymmreg,ymmrm256,imm8 [rvmi:fvm: evex.256.f3.0f3a.w0 42 /r ib] AVX10_2
|
||||
VMPSADBW zmmreg|mask|z,zmmreg,zmmrm512,imm8 [rvmi:fvm: evex.512.f3.0f3a.w0 42 /r ib] AVX10_2
|
||||
VPDPBSSD xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.128.f2.0f38.w0 50 /r ] AVX10_2
|
||||
VPDPBSSD ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.256.f2.0f38.w0 50 /r ] AVX10_2
|
||||
VPDPBSSD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.512.f2.0f38.w0 50 /r ] AVX10_2
|
||||
VPDPBSSDS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.128.f2.0f38.w0 51 /r ] AVX10_2
|
||||
VPDPBSSDS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.256.f2.0f38.w0 51 /r ] AVX10_2
|
||||
VPDPBSSDS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.512.f2.0f38.w0 51 /r ] AVX10_2
|
||||
VPDPBSUD xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.128.f3.0f38.w0 50 /r ] AVX10_2
|
||||
VPDPBSUD ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.256.f3.0f38.w0 50 /r ] AVX10_2
|
||||
VPDPBSUD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.512.f3.0f38.w0 50 /r ] AVX10_2
|
||||
VPDPBSUDS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.128.f3.0f38.w0 51 /r ] AVX10_2
|
||||
VPDPBSUDS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.256.f3.0f38.w0 51 /r ] AVX10_2
|
||||
VPDPBSUDS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.512.f3.0f38.w0 51 /r ] AVX10_2
|
||||
VPDPBUUD xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.128.np.0f38.w0 50 /r ] AVX10_2
|
||||
VPDPBUUD ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.256.np.0f38.w0 50 /r ] AVX10_2
|
||||
VPDPBUUD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.512.np.0f38.w0 50 /r ] AVX10_2
|
||||
VPDPBUUDS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.128.np.0f38.w0 51 /r ] AVX10_2
|
||||
VPDPBUUDS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.256.np.0f38.w0 51 /r ] AVX10_2
|
||||
VPDPBUUDS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.512.np.0f38.w0 51 /r ] AVX10_2
|
||||
|
||||
;# AVX10.2 MINMAX instructions
|
||||
VMINMAXBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16,imm8 [rvmi:fv: evex.128.f2.0f3a.w0 52 /r ib] AVX10_2
|
||||
VMINMAXBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16,imm8 [rvmi:fv: evex.256.f2.0f3a.w0 52 /r ib] AVX10_2
|
||||
VMINMAXBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16,imm8 [rvmi:fv: evex.512.f2.0f3a.w0 52 /r ib] AVX10_2
|
||||
VMINMAXPD xmmreg|mask|z,xmmreg,xmmrm128|b64,imm8 [rvmi:fv: evex.128.66.0f3a.w1 52 /r ib] AVX10_2
|
||||
VMINMAXPD ymmreg|mask|z,ymmreg,ymmrm256|b64,imm8 [rvmi:fv: evex.256.66.0f3a.w1 52 /r ib] AVX10_2
|
||||
VMINMAXPD zmmreg|mask|z,zmmreg,zmmrm512|b64|sae,imm8 [rvmi:fv: evex.512.66.0f3a.w1 52 /r ib] AVX10_2
|
||||
VMINMAXPH xmmreg|mask|z,xmmreg,xmmrm128|b16,imm8 [rvmi:fv: evex.128.np.0f3a.w0 52 /r ib] AVX10_2
|
||||
VMINMAXPH ymmreg|mask|z,ymmreg,ymmrm256|b16,imm8 [rvmi:fv: evex.256.np.0f3a.w0 52 /r ib] AVX10_2
|
||||
VMINMAXPH zmmreg|mask|z,zmmreg,zmmrm512|b16|sae,imm8 [rvmi:fv: evex.512.np.0f3a.w0 52 /r ib] AVX10_2
|
||||
VMINMAXPS xmmreg|mask|z,xmmreg,xmmrm128|b32,imm8 [rvmi:fv: evex.128.66.0f3a.w0 52 /r ib] AVX10_2
|
||||
VMINMAXPS ymmreg|mask|z,ymmreg,ymmrm256|b32,imm8 [rvmi:fv: evex.256.66.0f3a.w0 52 /r ib] AVX10_2
|
||||
VMINMAXPS zmmreg|mask|z,zmmreg,zmmrm512|b32|sae,imm8 [rvmi:fv: evex.512.66.0f3a.w0 52 /r ib] AVX10_2
|
||||
VMINMAXSD xmmreg|mask|z,xmmreg,xmmrm64|sae,imm8 [rvmi:t1s: evex.lig.66.0f3a.w1 53 /r ib] AVX10_2
|
||||
VMINMAXSH xmmreg|mask|z,xmmreg,xmmrm16|sae,imm8 [rvmi:t1s: evex.lig.np.0f3a.w0 53 /r ib] AVX10_2
|
||||
VMINMAXSS xmmreg|mask|z,xmmreg,xmmrm32|sae,imm8 [rvmi:t1s: evex.lig.66.0f3a.w0 53 /r ib] AVX10_2
|
||||
|
||||
;# AVX10.2 Saturating convert instructions
|
||||
VCVTBF162IBS xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.f2.map5.w0 69 /r ] AVX10_2
|
||||
VCVTBF162IBS ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.f2.map5.w0 69 /r ] AVX10_2
|
||||
VCVTBF162IBS zmmreg|mask|z,zmmrm512|b16 [rm:fv: evex.512.f2.map5.w0 69 /r ] AVX10_2
|
||||
VCVTBF162IUBS xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.f2.map5.w0 6b /r ] AVX10_2
|
||||
VCVTBF162IUBS ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.f2.map5.w0 6b /r ] AVX10_2
|
||||
VCVTBF162IUBS zmmreg|mask|z,zmmrm512|b16 [rm:fv: evex.512.f2.map5.w0 6b /r ] AVX10_2
|
||||
VCVTTBF162IBS xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.f2.map5.w0 68 /r ] AVX10_2
|
||||
VCVTTBF162IBS ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.f2.map5.w0 68 /r ] AVX10_2
|
||||
VCVTTBF162IBS zmmreg|mask|z,zmmrm512|b16 [rm:fv: evex.512.f2.map5.w0 68 /r ] AVX10_2
|
||||
VCVTTBF162IUBS xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.f2.map5.w0 6a /r ] AVX10_2
|
||||
VCVTTBF162IUBS ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.f2.map5.w0 6a /r ] AVX10_2
|
||||
VCVTTBF162IUBS zmmreg|mask|z,zmmrm512|b16 [rm:fv: evex.512.f2.map5.w0 6a /r ] AVX10_2
|
||||
VCVTTPD2DQS xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.np.map5.w1 6d /r ] AVX10_2
|
||||
VCVTTPD2DQS xmmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.np.map5.w1 6d /r ] AVX10_2
|
||||
VCVTTPD2DQS ymmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.np.map5.w1 6d /r ] AVX10_2
|
||||
VCVTTPD2QQS xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.map5.w1 6d /r ] AVX10_2
|
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VCVTTPD2QQS ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.map5.w1 6d /r ] AVX10_2
|
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VCVTTPD2QQS zmmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.66.map5.w1 6d /r ] AVX10_2
|
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VCVTTPD2UDQS xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.np.map5.w1 6c /r ] AVX10_2
|
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VCVTTPD2UDQS xmmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.np.map5.w1 6c /r ] AVX10_2
|
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VCVTTPD2UDQS ymmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.np.map5.w1 6c /r ] AVX10_2
|
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VCVTTPD2UQQS xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.map5.w1 6c /r ] AVX10_2
|
||||
VCVTTPD2UQQS ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.map5.w1 6c /r ] AVX10_2
|
||||
VCVTTPD2UQQS zmmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.66.map5.w1 6c /r ] AVX10_2
|
||||
VCVTPH2IBS xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.np.map5.w0 69 /r ] AVX10_2
|
||||
VCVTPH2IBS ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.np.map5.w0 69 /r ] AVX10_2
|
||||
VCVTPH2IBS zmmreg|mask|z,zmmrm512|b16|er [rm:fv: evex.512.np.map5.w0 69 /r ] AVX10_2
|
||||
VCVTPH2IUBS xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.np.map5.w0 6b /r ] AVX10_2
|
||||
VCVTPH2IUBS ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.np.map5.w0 6b /r ] AVX10_2
|
||||
VCVTPH2IUBS zmmreg|mask|z,zmmrm512|b16|er [rm:fv: evex.512.np.map5.w0 6b /r ] AVX10_2
|
||||
VCVTTPH2IBS xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.np.map5.w0 68 /r ] AVX10_2
|
||||
VCVTTPH2IBS ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.np.map5.w0 68 /r ] AVX10_2
|
||||
VCVTTPH2IBS zmmreg|mask|z,zmmrm512|b16|sae [rm:fv: evex.512.np.map5.w0 68 /r ] AVX10_2
|
||||
VCVTTPH2IUBS xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.np.map5.w0 6a /r ] AVX10_2
|
||||
VCVTTPH2IUBS ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.np.map5.w0 6a /r ] AVX10_2
|
||||
VCVTTPH2IUBS zmmreg|mask|z,zmmrm512|b16|sae [rm:fv: evex.512.np.map5.w0 6a /r ] AVX10_2
|
||||
VCVTTPS2DQS xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.np.map5.w0 6d /r ] AVX10_2
|
||||
VCVTTPS2DQS ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.np.map5.w0 6d /r ] AVX10_2
|
||||
VCVTTPS2DQS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.np.map5.w0 6d /r ] AVX10_2
|
||||
VCVTPS2IBS xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.map5.w0 69 /r ] AVX10_2
|
||||
VCVTPS2IBS ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.map5.w0 69 /r ] AVX10_2
|
||||
VCVTPS2IBS zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.66.map5.w0 69 /r ] AVX10_2
|
||||
VCVTPS2IUBS xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.map5.w0 6b /r ] AVX10_2
|
||||
VCVTPS2IUBS ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.map5.w0 6b /r ] AVX10_2
|
||||
VCVTPS2IUBS zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.66.map5.w0 6b /r ] AVX10_2
|
||||
VCVTTPS2IBS xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.map5.w0 68 /r ] AVX10_2
|
||||
VCVTTPS2IBS ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.map5.w0 68 /r ] AVX10_2
|
||||
VCVTTPS2IBS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.66.map5.w0 68 /r ] AVX10_2
|
||||
VCVTTPS2IUBS xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.map5.w0 6a /r ] AVX10_2
|
||||
VCVTTPS2IUBS ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.map5.w0 6a /r ] AVX10_2
|
||||
VCVTTPS2IUBS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.66.map5.w0 6a /r ] AVX10_2
|
||||
VCVTTPS2QQS xmmreg|mask|z,xmmrm64|b32 [rm:hv: evex.128.66.map5.w0 6d /r ] AVX10_2
|
||||
VCVTTPS2QQS ymmreg|mask|z,xmmrm128|b32 [rm:hv: evex.256.66.map5.w0 6d /r ] AVX10_2
|
||||
VCVTTPS2QQS zmmreg|mask|z,ymmrm256|b32|sae [rm:hv: evex.512.66.map5.w0 6d /r ] AVX10_2
|
||||
VCVTTPS2UDQS xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.np.map5.w0 6c /r ] AVX10_2
|
||||
VCVTTPS2UDQS ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.np.map5.w0 6c /r ] AVX10_2
|
||||
VCVTTPS2UDQS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.np.map5.w0 6c /r ] AVX10_2
|
||||
VCVTTPS2UQQS xmmreg|mask|z,xmmrm64|b32 [rm:hv: evex.128.66.map5.w0 6c /r ] AVX10_2
|
||||
VCVTTPS2UQQS ymmreg|mask|z,xmmrm128|b32 [rm:hv: evex.256.66.map5.w0 6c /r ] AVX10_2
|
||||
VCVTTPS2UQQS zmmreg|mask|z,ymmrm256|b32|sae [rm:hv: evex.512.66.map5.w0 6c /r ] AVX10_2
|
||||
$dq VCVTTSD2SIS reg#,xmmrm64|sae [rm:t1s: evex.lig.f2.map5.w# 6d /r ] AVX10_2
|
||||
$dq VCVTTSD2USIS reg#,xmmrm64|sae [rm:t1s: evex.lig.f2.map5.w# 6c /r ] AVX10_2
|
||||
$dq VCVTTSS2SIS reg#,xmmrm32|sae [rm:t1s: evex.lig.f3.map5.w# 6d /r ] AVX10_2
|
||||
$dq VCVTTSS2USIS reg#,xmmrm32|sae [rm:t1s: evex.lig.f3.map5.w# 6c /r ] AVX10_2
|
||||
|
||||
;# AVX10.2 Zero-extending partial vector copy instructions
|
||||
VMOVD xmmreg,xmmrm32 [rm:t1s: evex.128.f3.0f.w0 7e /r ] AVX10_2
|
||||
VMOVD xmmrm32,xmmreg [rm:t1s: evex.128.66.0f.w0 d6 /r ] AVX10_2
|
||||
VMOVW xmmreg,xmmrm16 [rm:t1s: evex.128.f3.map5.w0 6e /r ] AVX10_2
|
||||
VMOVW xmmrm16,xmmreg [rm:t1s: evex.128.f3.map5.w0 7e /r ] AVX10_2
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue