mirror of
https://github.com/netwide-assembler/nasm
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regs: clean up and somewhat automate register range flags
Doing the register range flags by hand is a bit more work than
necessary when dealing with APX, so auto-generate the flags for ranges
{0, 1-15, 16+} using 3 bits.
In theory we could handle even more automagically by splitting ranges
up further: the existing ranges are sets of {0, 1, 2, 3, 4-5, 6-7,
8-15, 16-31} which would require 7 bits, although it would remove most
of the subclass bits for registers; it would require separating the
subclass bits for EAs from the ones for registers (which might be a
good idea anyway...)
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin
parent
49640ed315
commit
a556ea3edf
4 changed files with 210 additions and 172 deletions
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@ -193,80 +193,134 @@ static inline bool is_reg_class(opflags_t class, opflags_t reg)
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#define IS_SREG(reg) is_reg_class(REG_SREG, (reg))
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#define IS_FSGS(reg) is_reg_class(REG_FSGS, (reg))
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/*
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* These are used across the RM classes so cannot conflict with neither EA
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* nor REG subtypes! x86/insns.pl automatically adds RN_FLAGS(x) to the
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* defintion of each register type.
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*/
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#define RN_L16 GEN_SUBCLASS(5) /* Register number 0-15 */
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#define RN_ZERO (GEN_SUBCLASS(6) | RN_L16) /* Register number 0 */
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#define RN_NZERO GEN_SUBCLASS(7) /* Register number 1+ */
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#define RN_1_15 (RN_NZERO | RN_L16) /* Register number 1-15 */
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#define RN_FLAGS(n) ((n) == 0 ? RN_ZERO : \
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(n) < 16 ? RN_1_15 : \
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0)
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#define RM_L16 (RN_L16 | REGMEM)
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#define RM_ZERO (RN_ZERO | REGMEM)
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#define RM_NZERO (RN_NZERO | REGMEM)
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#define RM_1_15 (RM_1_15 | REGMEM)
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/* Register classes */
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#define REG_EA ( REGMEM | REGISTER) /* 'normal' reg, qualifies as EA */
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#define RM_GPR ( REG_CLASS_GPR | REGMEM) /* integer operand */
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#define REG_GPR ( REG_CLASS_GPR | REGMEM | REGISTER) /* integer register */
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#define REG8 ( REG_CLASS_GPR | BITS8 | REGMEM | REGISTER) /* 8-bit GPR */
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#define REG16 ( REG_CLASS_GPR | BITS16 | REGMEM | REGISTER) /* 16-bit GPR */
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#define REG32 ( REG_CLASS_GPR | BITS32 | REGMEM | REGISTER) /* 32-bit GPR */
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#define REG64 ( REG_CLASS_GPR | BITS64 | REGMEM | REGISTER) /* 64-bit GPR */
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#define FPUREG ( REG_CLASS_FPUREG | REGISTER) /* floating point stack registers */
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#define FPU0 (GEN_SUBCLASS(1) | REG_CLASS_FPUREG | REGISTER) /* FPU stack register zero */
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#define RM_MMX ( REG_CLASS_RM_MMX | REGMEM) /* MMX operand */
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#define MMXREG ( REG_CLASS_RM_MMX | REGMEM | REGISTER) /* MMX register */
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#define RM_XMM ( REG_CLASS_RM_XMM | REGMEM) /* XMM (SSE) operand */
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#define XMMREG ( REG_CLASS_RM_XMM | REGMEM | REGISTER) /* XMM (SSE) register */
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#define RM_YMM ( REG_CLASS_RM_YMM | REGMEM) /* YMM (AVX) operand */
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#define YMMREG ( REG_CLASS_RM_YMM | REGMEM | REGISTER) /* YMM (AVX) register */
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#define RM_ZMM ( REG_CLASS_RM_ZMM | REGMEM) /* ZMM (AVX512) operand */
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#define ZMMREG ( REG_CLASS_RM_ZMM | REGMEM | REGISTER) /* ZMM (AVX512) register */
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#define RM_OPMASK ( REG_CLASS_OPMASK | REGMEM) /* Opmask operand */
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#define OPMASKREG ( REG_CLASS_OPMASK | REGMEM | REGISTER) /* Opmask register */
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#define OPMASK0 (GEN_SUBCLASS(1) | REG_CLASS_OPMASK | REGMEM | REGISTER) /* Opmask register zero (k0) */
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#define REG_L16 (RN_L16 | REGISTER)
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#define REG_ZERO (RN_ZERO | REGISTER)
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#define REG_NZERO (RN_NZERO | REGISTER)
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#define REG_1_15 (RN_1_15 | REGISTER)
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#define REG_SMASK SUBCLASS_MASK
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#define REG_EA ( REGMEM | REGISTER ) /* 'normal' reg, qualifies as EA */
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#define RM_GPR (REG_CLASS_GPR | REGMEM ) /* integer operand */
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#define REG_GPR (REG_CLASS_GPR | REG_EA ) /* integer register */
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#define FPUREG (REG_CLASS_FPUREG | REGISTER ) /* fp stack registers */
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#define FPU0 (REG_CLASS_FPUREG | REG_ZERO ) /* fp stack register zero */
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#define RM_MMX (REG_CLASS_RM_MMX | REGMEM ) /* MMX operand */
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#define MMXREG (REG_CLASS_RM_MMX | REG_EA ) /* MMX register */
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#define RM_XMM (REG_CLASS_RM_XMM | REGMEM ) /* XMM operand */
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#define XMMREG (REG_CLASS_RM_XMM | REG_EA ) /* XMM register */
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#define RM_XMM_L16 (REG_CLASS_RM_XMM | REGMEM | RN_L16 ) /* XMM operand reg 0-15 */
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#define XMM_L16 (REG_CLASS_RM_XMM | REG_EA | RN_L16 ) /* XMM register 0-15 */
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#define XMM0 (REG_CLASS_RM_XMM | REGMEM | REG_ZERO ) /* XMM register 0 */
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#define RM_YMM (REG_CLASS_RM_YMM | REGMEM ) /* YMM operand */
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#define YMMREG (REG_CLASS_RM_YMM | REG_EA ) /* YMM register */
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#define RM_YMM_L16 (REG_CLASS_RM_YMM | REGMEM | RN_L16 ) /* YMM operand reg 0-15 */
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#define YMM_L16 (REG_CLASS_RM_YMM | REG_EA | RN_L16 ) /* YMM register 0-15 */
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#define YMM0 (REG_CLASS_RM_YMM | REGMEM | REG_ZERO ) /* YMM register 0 */
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#define RM_ZMM (REG_CLASS_RM_ZMM | REGMEM ) /* ZMM operand */
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#define ZMMREG (REG_CLASS_RM_ZMM | REG_EA ) /* ZMM register */
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#define RM_ZMM_L16 (REG_CLASS_RM_ZMM | REGMEM | RN_L16 ) /* ZMM operand reg 0-15 */
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#define ZMM_L16 (REG_CLASS_RM_ZMM | REG_EA | RN_L16 ) /* ZMM register 0-15 */
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#define ZMM0 (REG_CLASS_RM_ZMM | REGMEM | REG_ZERO ) /* ZMM register 0 */
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#define RM_OPMASK (REG_CLASS_OPMASK | REGMEM ) /* Opmask operand */
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#define OPMASKREG (REG_CLASS_OPMASK | REG_EA ) /* Opmask register */
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#define OPMASK0 (REG_CLASS_OPMASK | REG_EA ) /* Opmask register zero (k0) */
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#define RM_K RM_OPMASK
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#define KREG OPMASKREG
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#define RM_BND ( REG_CLASS_BND | REGMEM) /* Bounds operand */
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#define BNDREG ( REG_CLASS_BND | REGMEM | REGISTER) /* Bounds register */
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#define TMMREG ( REG_CLASS_RM_TMM | REGMEM | REGISTER) /* TMM (AMX) register */
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#define REG_CDT ( REG_CLASS_CDT | BITS32 | REGISTER) /* CRn, DRn and TRn */
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#define REG_CREG (GEN_SUBCLASS(1) | REG_CLASS_CDT | BITS32 | REGISTER) /* CRn */
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#define REG_DREG (GEN_SUBCLASS(2) | REG_CLASS_CDT | BITS32 | REGISTER) /* DRn */
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#define REG_TREG (GEN_SUBCLASS(3) | REG_CLASS_CDT | BITS32 | REGISTER) /* TRn */
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#define REG_SREG ( REG_CLASS_SREG | BITS16 | REGISTER) /* any segment register */
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#define RM_BND (REG_CLASS_BND | REGMEM ) /* Bounds operand */
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#define BNDREG (REG_CLASS_BND | REG_EA ) /* Bounds register */
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#define TMMREG (REG_CLASS_RM_TMM | REG_EA ) /* TMM (AMX) register */
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#define REG_CDT (REG_CLASS_CDT | REGISTER) /* CRn, DRn and TRn */
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#define REG_CREG (GEN_SUBCLASS(0) | REG_CDT ) /* CRn */
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#define REG_DREG (GEN_SUBCLASS(1) | REG_CDT ) /* DRn */
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#define REG_TREG (GEN_SUBCLASS(2) | REG_CDT ) /* TRn */
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#define REG_SREG (REG_CLASS_SREG | REGISTER | BITS16) /* segment register */
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/* Segment registers */
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#define REG_ES (GEN_SUBCLASS(0) | GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER) /* ES */
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#define REG_CS (GEN_SUBCLASS(1) | GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER) /* CS */
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#define REG_SS (GEN_SUBCLASS(0) | GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER) /* SS */
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#define REG_DS (GEN_SUBCLASS(1) | GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER) /* DS */
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#define REG_FS (GEN_SUBCLASS(0) | GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* FS */
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#define REG_GS (GEN_SUBCLASS(1) | GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* GS */
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#define REG_FSGS ( GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* FS or GS */
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#define REG_SEG67 ( GEN_SUBCLASS(5) | REG_CLASS_SREG | BITS16 | REGISTER) /* Unimplemented segment registers */
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#define REG_ES (GEN_SUBCLASS(0) | GEN_SUBCLASS(2) | REG_SREG) /* ES */
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#define REG_CS (GEN_SUBCLASS(1) | GEN_SUBCLASS(2) | REG_SREG) /* CS */
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#define REG_SS (GEN_SUBCLASS(0) | GEN_SUBCLASS(3) | REG_SREG) /* SS */
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#define REG_DS (GEN_SUBCLASS(1) | GEN_SUBCLASS(3) | REG_SREG) /* DS */
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#define REG_FS (GEN_SUBCLASS(0) | GEN_SUBCLASS(4) | REG_SREG) /* FS */
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#define REG_GS (GEN_SUBCLASS(1) | GEN_SUBCLASS(4) | REG_SREG) /* GS */
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#define REG_FSGS ( GEN_SUBCLASS(4) | REG_SREG) /* FS or GS */
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#define REG_SEG6 (GEN_SUBCLASS(0) | GEN_SUBCLASS(5) | REG_SREG)
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#define REG_SEG7 (GEN_SUBCLASS(1) | GEN_SUBCLASS(5) | REG_SREG)
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#define REG_SEG67 ( GEN_SUBCLASS(5) | REG_SREG)
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/* Special GPRs */
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#define REG_SMASK SUBCLASS_MASK /* a mask for the following */
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#define REG_ACCUM (GEN_SUBCLASS(1) | REG_CLASS_GPR | REGMEM | REGISTER) /* accumulator: AL, AX, EAX, RAX */
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#define REG_AL (GEN_SUBCLASS(1) | REG_CLASS_GPR | BITS8 | REGMEM | REGISTER)
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#define REG_AX (GEN_SUBCLASS(1) | REG_CLASS_GPR | BITS16 | REGMEM | REGISTER)
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#define REG_EAX (GEN_SUBCLASS(1) | REG_CLASS_GPR | BITS32 | REGMEM | REGISTER)
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#define REG_RAX (GEN_SUBCLASS(1) | REG_CLASS_GPR | BITS64 | REGMEM | REGISTER)
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#define REG_COUNT (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | REGMEM | REGISTER) /* counter: CL, CX, ECX, RCX */
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#define REG_CL (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | BITS8 | REGMEM | REGISTER)
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#define REG_CX (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | BITS16 | REGMEM | REGISTER)
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#define REG_ECX (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | BITS32 | REGMEM | REGISTER)
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#define REG_RCX (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | BITS64 | REGMEM | REGISTER)
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#define REG_DL (GEN_SUBCLASS(5) | GEN_SUBCLASS(3) | REG_CLASS_GPR | BITS8 | REGMEM | REGISTER) /* data: DL, DX, EDX, RDX */
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#define REG_DX (GEN_SUBCLASS(5) | GEN_SUBCLASS(3) | REG_CLASS_GPR | BITS16 | REGMEM | REGISTER)
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#define REG_EDX (GEN_SUBCLASS(5) | GEN_SUBCLASS(3) | REG_CLASS_GPR | BITS32 | REGMEM | REGISTER)
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#define REG_RDX (GEN_SUBCLASS(5) | GEN_SUBCLASS(3) | REG_CLASS_GPR | BITS64 | REGMEM | REGISTER)
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#define REG_HIGH (GEN_SUBCLASS(5) | GEN_SUBCLASS(4) | REG_CLASS_GPR | BITS8 | REGMEM | REGISTER) /* high regs: AH, CH, DH, BH */
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#define REG_NOTACC GEN_SUBCLASS(5) /* non-accumulator register */
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#define REG8NA (GEN_SUBCLASS(5) | REG_CLASS_GPR | BITS8 | REGMEM | REGISTER) /* 8-bit non-acc GPR */
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#define REG16NA (GEN_SUBCLASS(5) | REG_CLASS_GPR | BITS16 | REGMEM | REGISTER) /* 16-bit non-acc GPR */
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#define REG32NA (GEN_SUBCLASS(5) | REG_CLASS_GPR | BITS32 | REGMEM | REGISTER) /* 32-bit non-acc GPR */
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#define REG64NA (GEN_SUBCLASS(5) | REG_CLASS_GPR | BITS64 | REGMEM | REGISTER) /* 64-bit non-acc GPR */
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/* GPRs */
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#define REG8 (REG_GPR | BITS8 )
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#define REG16 (REG_GPR | BITS16)
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#define REG32 (REG_GPR | BITS32)
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#define REG64 (REG_GPR | BITS64)
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/* accumulator: AL, AX, EAX, RAX */
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#define REG_ACCUM (REG_GPR | REG_ZERO)
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#define REG_AL (REG_ACCUM | BITS8 )
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#define REG_AX (REG_ACCUM | BITS16)
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#define REG_EAX (REG_ACCUM | BITS32)
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#define REG_RAX (REG_ACCUM | BITS64)
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/* counter: CL, CX, ECX, RDX */
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#define REG_COUNT (REG_GPR | REG_1_15 | GEN_SUBCLASS(0))
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#define REG_CL (REG_COUNT | BITS8 )
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#define REG_CX (REG_COUNT | BITS16)
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#define REG_ECX (REG_COUNT | BITS32)
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#define REG_RCX (REG_COUNT | BITS64)
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/* data: DL, DX, EDX, RDX */
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#define REG_DATA (REG_GPR | REG_1_15 | GEN_SUBCLASS(1))
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#define REG_DL (REG_DATA | BITS8 )
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#define REG_DX (REG_DATA | BITS16)
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#define REG_EDX (REG_DATA | BITS32)
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#define REG_RDX (REG_DATA | BITS64)
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/* high 8-bit regs: AH, CH, DH, BH */
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#define REG_HIGH (REG8 | REG_1_15 | GEN_SUBCLASS(2))
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/* Non-accumulator registers */
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#define REG_NA (REG_GPR | REG_NZERO)
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#define REG8NA (REG_NA | BITS8 )
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#define REG16NA (REG_NA | BITS16)
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#define REG32NA (REG_NA | BITS32)
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#define REG64NA (REG_NA | BITS64)
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/* special types of EAs */
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#define MEM_OFFS (GEN_SUBCLASS(1) | MEMORY) /* simple [address] offset - absolute! */
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#define IP_REL (GEN_SUBCLASS(2) | MEMORY) /* IP-relative offset */
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#define XMEM (GEN_SUBCLASS(3) | MEMORY) /* 128-bit vector SIB */
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#define YMEM (GEN_SUBCLASS(4) | MEMORY) /* 256-bit vector SIB */
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#define ZMEM (GEN_SUBCLASS(5) | MEMORY) /* 512-bit vector SIB */
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#define MEM_OFFS (GEN_SUBCLASS(0) | MEMORY) /* simple [address] offset - absolute! */
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#define IP_REL (GEN_SUBCLASS(1) | MEMORY) /* IP-relative offset */
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#define XMEM (GEN_SUBCLASS(2) | MEMORY) /* 128-bit vector SIB */
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#define YMEM (GEN_SUBCLASS(3) | MEMORY) /* 256-bit vector SIB */
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#define ZMEM (GEN_SUBCLASS(4) | MEMORY) /* 512-bit vector SIB */
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/* memory which matches any type of r/m operand */
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#define MEMORY_ANY (MEMORY | RM_GPR | RM_MMX | RM_XMM_L16 | RM_YMM_L16 | RM_ZMM_L16 | RM_OPMASK | RM_BND)
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/*
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* operand bits to match an instruction carrying any type of memory r/m operand
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*/
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#define MEMORY_ANY (MEMORY | RM_GPR | RM_MMX | RM_XMM | RM_YMM | RM_ZMM | \
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RM_L16 | RM_ZERO | RM_NZERO | RM_OPMASK | RM_BND)
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/* special immediate values */
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#define UNITY (GEN_SUBCLASS(0) | IMMEDIATE) /* operand equals 1 */
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@ -275,22 +329,6 @@ static inline bool is_reg_class(opflags_t class, opflags_t reg)
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#define SDWORD (GEN_SUBCLASS(3) | IMMEDIATE) /* operand is in the range -0x80000000..0x7FFFFFFF */
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#define UDWORD (GEN_SUBCLASS(4) | IMMEDIATE) /* operand is in the range 0..0xFFFFFFFF */
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/*
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* Subset of vector registers: register 0 only and registers 0-15.
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* Avoid conflicts in subclass bitfield with any of special EA types!
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*/
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#define RM_XMM_L16 (GEN_SUBCLASS(6) | RM_XMM) /* XMM r/m operand 0 ~ 15 */
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#define XMM0 (GEN_SUBCLASS(1) | GEN_SUBCLASS(6) | XMMREG) /* XMM register zero */
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#define XMM_L16 ( GEN_SUBCLASS(6) | XMMREG) /* XMM register 0 ~ 15 */
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#define RM_YMM_L16 (GEN_SUBCLASS(6) | RM_YMM) /* YMM r/m operand 0 ~ 15 */
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#define YMM0 (GEN_SUBCLASS(1) | GEN_SUBCLASS(6) | YMMREG) /* YMM register zero */
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#define YMM_L16 ( GEN_SUBCLASS(6) | YMMREG) /* YMM register 0 ~ 15 */
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#define RM_ZMM_L16 (GEN_SUBCLASS(6) | RM_ZMM) /* ZMM r/m operand 0 ~ 15 */
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#define ZMM0 (GEN_SUBCLASS(1) | GEN_SUBCLASS(6) | ZMMREG) /* ZMM register zero */
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#define ZMM_L16 ( GEN_SUBCLASS(6) | ZMMREG) /* ZMM register 0 ~ 15 */
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/* Register set sizes */
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#define RS2 GEN_REGSET(0)
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#define RS4 GEN_REGSET(1)
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@ -50,14 +50,20 @@ Codes Mnemonic Explanation
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\240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
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V field taken from operand 0..3.
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\250 this instruction uses EVEX rather than REX or VEX/XOP, with the
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V field set to 1111b.
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V field set to 11111b.
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EVEX prefixes are followed by the sequence:
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\cm\wlp\tup where cm is:
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cc 00m mmm
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c = 2 for EVEX and mmmm is the M field (EVEX.P0[3:0])
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and wlp is:
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00 wwl lpp
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\um\wlp\tup um defintion: ue 00m mmm
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u = set the U bit (EVEX.P1[2]) if mod = 3
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[.m#] mmmm = opcode map
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NOTE: if the base register is a GPR the m bit is used
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to encode bit 4 of the GPR number.
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wlp definition: df wwl lpp
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[nd] d = 1
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[nf] f = 1
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[l0] ll = 0 (.128, .lz)
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[l1] ll = 1 (.256)
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[l2] ll = 2 (.512)
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@ -82,8 +88,13 @@ EVEX prefixes are followed by the sequence:
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\270 this instruction uses VEX/XOP rather than REX, with the
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V field set to 1111b.
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VEX/XOP prefixes are followed by the sequence:
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\tmm\wlp where mm is the M field; and wlp is:
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00 wwl lpp
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\tmm\wlp tmm format: tt 0mm mmm
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[vex] tt = 0
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[xop] tt = 1
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mmmmm = M field
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wlp format: 00 wwl lpp
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[l0] ll = 0 for L = 0 (.128, .lz)
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[l1] ll = 1 for L = 1 (.256)
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[lig] ll = 2 for L don't care (always assembled as 0)
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@ -116,10 +127,8 @@ t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
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\323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
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\324 o64 indicates 64-bit operand size requiring REX prefix.
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\325 nohi instruction which always uses spl/bpl/sil/dil
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\326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
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disassembler only; for SSE instructions.
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\331 norep instruction not valid with REP prefix. Hint for
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disassembler only; for SSE instructions.
|
||||
\326 nof3 (disassembler only) not valid with 0xF3 REP prefix.
|
||||
\331 norep (disassembler only) not valid with 0xF2 or 0xF3 REP prefixes.
|
||||
\332 f2i REP prefix (0xF2 byte) used as opcode extension.
|
||||
\333 f3i REP prefix (0xF3 byte) used as opcode extension.
|
||||
\334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
|
||||
|
|
@ -130,6 +139,8 @@ t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
|
|||
\340 resb reserve <operand 0> bytes of uninitialized storage.
|
||||
Operand 0 had better be a segmentless constant.
|
||||
\341 wait this instruction needs a WAIT "prefix"
|
||||
\342 rex2.m0 REX2 prefix, map 0
|
||||
\343 rex2.m1 REX2 prefix, map 1
|
||||
\360 np no SSE prefix (== \364\331)
|
||||
\361 66 SSE prefix (== \366\331)
|
||||
\364 !osp operand-size prefix (0x66) not permitted
|
||||
|
|
|
|||
137
x86/regs.dat
137
x86/regs.dat
|
|
@ -1,6 +1,6 @@
|
|||
## --------------------------------------------------------------------------
|
||||
##
|
||||
## Copyright 1996-2009 The NASM Authors - All Rights Reserved
|
||||
##
|
||||
## Copyright 1996-2024 The NASM Authors - All Rights Reserved
|
||||
## See the file AUTHORS included with the NASM distribution for
|
||||
## the specific copyright holders.
|
||||
##
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
## copyright notice, this list of conditions and the following
|
||||
## disclaimer in the documentation and/or other materials provided
|
||||
## with the distribution.
|
||||
##
|
||||
##
|
||||
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
|
||||
## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
|
|
@ -49,93 +49,82 @@
|
|||
#
|
||||
|
||||
# General-purpose registers
|
||||
al REG_AL reg8,reg8_rex 0
|
||||
ah REG_HIGH reg8 4
|
||||
ax REG_AX reg16 0
|
||||
eax REG_EAX reg32 0
|
||||
rax REG_RAX reg64 0
|
||||
bl REG8NA reg8,reg8_rex 3
|
||||
bh REG_HIGH reg8 7
|
||||
bx REG16NA reg16 3
|
||||
ebx REG32NA reg32 3
|
||||
rbx REG64NA reg64 3
|
||||
cl REG_CL reg8,reg8_rex 1
|
||||
ch REG_HIGH reg8 5
|
||||
cx REG_CX reg16 1
|
||||
ecx REG_ECX reg32 1
|
||||
rcx REG_RCX reg64 1
|
||||
dl REG_DL reg8,reg8_rex 2
|
||||
dh REG_HIGH reg8 6
|
||||
dx REG_DX reg16 2
|
||||
edx REG_EDX reg32 2
|
||||
rdx REG_RDX reg64 2
|
||||
spl REG8NA reg8_rex 4
|
||||
sp REG16NA reg16 4
|
||||
esp REG32NA reg32 4
|
||||
rsp REG64NA reg64 4
|
||||
bpl REG8NA reg8_rex 5
|
||||
bp REG16NA reg16 5
|
||||
ebp REG32NA reg32 5
|
||||
rbp REG64NA reg64 5
|
||||
sil REG8NA reg8_rex 6
|
||||
si REG16NA reg16 6
|
||||
esi REG32NA reg32 6
|
||||
rsi REG64NA reg64 6
|
||||
dil REG8NA reg8_rex 7
|
||||
di REG16NA reg16 7
|
||||
edi REG32NA reg32 7
|
||||
rdi REG64NA reg64 7
|
||||
r8-15b REG8NA reg8_rex 8
|
||||
r8-15w REG16NA reg16 8
|
||||
r8-15d REG32NA reg32 8
|
||||
r8-15 REG64NA reg64 8
|
||||
al REG_AL reg8,reg8_rex 0
|
||||
ah REG_HIGH reg8 4
|
||||
ax REG_AX reg16 0
|
||||
eax REG_EAX reg32 0
|
||||
rax REG_RAX reg64 0
|
||||
bl REG8NA reg8,reg8_rex 3
|
||||
bh REG_HIGH reg8 7
|
||||
bx REG16NA reg16 3
|
||||
ebx REG32NA reg32 3
|
||||
rbx REG64NA reg64 3
|
||||
cl REG_CL reg8,reg8_rex 1
|
||||
ch REG_HIGH reg8 5
|
||||
cx REG_CX reg16 1
|
||||
ecx REG_ECX reg32 1
|
||||
rcx REG_RCX reg64 1
|
||||
dl REG_DL reg8,reg8_rex 2
|
||||
dh REG_HIGH reg8 6
|
||||
dx REG_DX reg16 2
|
||||
edx REG_EDX reg32 2
|
||||
rdx REG_RDX reg64 2
|
||||
spl REG8 reg8_rex 4
|
||||
sp REG16 reg16 4
|
||||
esp REG32 reg32 4
|
||||
rsp REG64 reg64 4
|
||||
bpl REG8 reg8_rex 5
|
||||
bp REG16 reg16 5
|
||||
ebp REG32 reg32 5
|
||||
rbp REG64 reg64 5
|
||||
sil REG8 reg8_rex 6
|
||||
si REG16 reg16 6
|
||||
esi REG32 reg32 6
|
||||
rsi REG64 reg64 6
|
||||
dil REG8 reg8_rex 7
|
||||
di REG16 reg16 7
|
||||
edi REG32 reg32 7
|
||||
rdi REG64 reg64 7
|
||||
r8-31b REG8 reg8_rex 8
|
||||
r8-31w REG16 reg16 8
|
||||
r8-31d REG32 reg32 8
|
||||
r8-31 REG64 reg64 8
|
||||
|
||||
# Segment registers
|
||||
es REG_ES sreg 0
|
||||
cs REG_CS sreg 1
|
||||
ss REG_SS sreg 2
|
||||
ds REG_DS sreg 3
|
||||
fs REG_FS sreg 4
|
||||
gs REG_GS sreg 5
|
||||
segr6-7 REG_SEG67 sreg 6
|
||||
es REG_ES sreg 0
|
||||
cs REG_CS sreg 1
|
||||
ss REG_SS sreg 2
|
||||
ds REG_DS sreg 3
|
||||
fs REG_FS sreg 4
|
||||
gs REG_GS sreg 5
|
||||
segr6-7 REG_SEG67 sreg 6
|
||||
|
||||
# Control registers
|
||||
cr0-15 REG_CREG creg 0
|
||||
cr0-31 REG_CREG creg 0
|
||||
|
||||
# Debug registers
|
||||
dr0-15 REG_DREG dreg 0
|
||||
dr0-31 REG_DREG dreg 0
|
||||
|
||||
# Test registers
|
||||
tr0-7 REG_TREG treg 0
|
||||
tr0-7 REG_TREG treg 0
|
||||
|
||||
# Floating-point registers
|
||||
st0 FPU0 fpureg 0
|
||||
st1-7 FPUREG fpureg 1
|
||||
st0-7 FPUREG fpureg 0
|
||||
|
||||
# MMX registers
|
||||
mm0-7 MMXREG mmxreg 0
|
||||
mm0-7 MMXREG mmxreg 0
|
||||
|
||||
# SSE registers
|
||||
xmm0 XMM0 xmmreg 0
|
||||
xmm1-15 XMM_L16 xmmreg 1
|
||||
xmm16-31 XMMREG xmmreg 16
|
||||
|
||||
# AVX registers
|
||||
ymm0 YMM0 ymmreg 0
|
||||
ymm1-15 YMM_L16 ymmreg 1
|
||||
ymm16-31 YMMREG ymmreg 16
|
||||
|
||||
# AVX512 registers
|
||||
zmm0 ZMM0 zmmreg 0
|
||||
zmm1-15 ZMM_L16 zmmreg 1
|
||||
zmm16-31 ZMMREG zmmreg 16
|
||||
# SSE/AVX registers
|
||||
xmm0-31 XMMREG xmmreg 0
|
||||
ymm0-31 YMMREG ymmreg 0
|
||||
zmm0-31 ZMMREG zmmreg 0
|
||||
|
||||
# AMX tile registers
|
||||
tmm0-7 TMMREG tmmreg 0
|
||||
tmm0-7 TMMREG tmmreg 0
|
||||
|
||||
# Opmask registers
|
||||
k0 OPMASK0 opmaskreg 0
|
||||
k1-7 OPMASKREG opmaskreg 1 TFLAG_BRC_OPT
|
||||
k0 OPMASKREG opmaskreg 0
|
||||
k1-7 OPMASKREG opmaskreg 1 TFLAG_BRC_OPT
|
||||
|
||||
# Bounds registers
|
||||
bnd0-3 BNDREG bndreg 0
|
||||
bnd0-3 BNDREG bndreg 0
|
||||
|
|
|
|||
10
x86/regs.pl
10
x86/regs.pl
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/perl
|
||||
## --------------------------------------------------------------------------
|
||||
##
|
||||
## Copyright 1996-2009 The NASM Authors - All Rights Reserved
|
||||
##
|
||||
## Copyright 1996-2024 The NASM Authors - All Rights Reserved
|
||||
## See the file AUTHORS included with the NASM distribution for
|
||||
## the specific copyright holders.
|
||||
##
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
## copyright notice, this list of conditions and the following
|
||||
## disclaimer in the documentation and/or other materials provided
|
||||
## with the distribution.
|
||||
##
|
||||
##
|
||||
## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
|
||||
## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
|
|
@ -156,8 +156,8 @@ if ( $fmt eq 'h' ) {
|
|||
printf " 0,\n"; # Dummy entry for 0
|
||||
foreach $reg ( sort(keys(%regs)) ) {
|
||||
# Print the class of the register
|
||||
printf " %-15s /* %-5s */\n",
|
||||
$regs{$reg}.',', $reg;
|
||||
printf " /* %-5s */ RN_FLAGS(%2d) | %s,\n",
|
||||
$reg, $regvals{$reg}, $regs{$reg};
|
||||
}
|
||||
print "};\n";
|
||||
} elsif ( $fmt eq 'vc' ) {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue