diff --git a/asm/assemble.c b/asm/assemble.c index a82fc9ba1..78dbb6093 100644 --- a/asm/assemble.c +++ b/asm/assemble.c @@ -1127,6 +1127,9 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits, if (ins->oprs[0].segment != NO_SEG) nasm_error(ERR_NONFATAL, "attempt to reserve non-constant" " quantity of BSS space"); + else if (ins->oprs[0].opflags & OPFLAG_FORWARD) + nasm_error(ERR_WARNING | ERR_PASS1, + "forward reference in RESx can have unpredictable results"); else length += ins->oprs[0].offset; break; diff --git a/doc/changes.src b/doc/changes.src index 73d84eb14..682c7d1ca 100644 --- a/doc/changes.src +++ b/doc/changes.src @@ -7,6 +7,34 @@ The NASM 2 series supports x86-64, and is the production version of NASM since 2007. +\S{cl-2.12.03} Version 2.12.03 + +\b Add new warnings for certain dangerous constructs which never ought + to have been allowed. In particular, the \c{RESB} family of + instructions should have been taking a critical expression all + along. + +\b Fix the EVEX (AVX-512) versions of the \c{VPBROADCAST}, \c{VPEXTR}, + and \c{VPINSR} instructions. + +\b Support contracted forms of additional instructions. As a general + rule, if an instruction has a non-destructive source immediately + after a destination register that isn't used as an input, NASM + supports omitting that source register, using the destination + register as that value. This among other things makes it easier to + convert SSE code to the equivalent AVX code: + +\c addps xmm1,xmm0 ; SSE instruction +\c vaddps ymm1,ymm1,ymm0 ; AVX official long form +\c vaddps ymm1,ymm0 ; AVX contracted form + +\b Fix Codeview malformed compiler version record. + +\b Add the \c{CLWB} and \c{PCOMMIT} instructions. Note that the + \c{PCOMMIT} instruction has been deprecated and will never be + included in a shipping product; it is included for completeness + only. + \S{cl-2.12.02} Version 2.12.02 \b Fix preprocessor errors, especially \c{%error} and \c{%warning}, @@ -16,7 +44,7 @@ since 2007. \b More Codeview debug format fixes. -\b If the MASM PTR keyword is encountered, issue a warning. This is +\b If the MASM \c{PTR} keyword is encountered, issue a warning. This is much more likely to indicate a MASM-ism encountered in NASM than it is a valid label. This warning can be suppressed with \c{-w-ptr}, the \c{[warning]} directive (see \k{opt-w}) or by the macro diff --git a/x86/insns-iflags.pl b/x86/insns-iflags.pl index 9c5abb9b7..84eda8f56 100644 --- a/x86/insns-iflags.pl +++ b/x86/insns-iflags.pl @@ -136,6 +136,7 @@ my %insns_flag_bit = ( "AVX512BW" => [ 73, "AVX-512 Byte and Word"], "AVX512IFMA" => [ 74, "AVX-512 IFMA instructions"], "AVX512VBMI" => [ 75, "AVX-512 VBMI instructions"], + "OBSOLETE" => [ 93, "Instruction removed from architecture"], "VEX" => [ 94, "VEX or XOP encoded instruction"], "EVEX" => [ 95, "EVEX encoded instruction"], diff --git a/x86/insns.dat b/x86/insns.dat index 9d01797ed..d6f5c72a6 100644 --- a/x86/insns.dat +++ b/x86/insns.dat @@ -1,6 +1,6 @@ ;; -------------------------------------------------------------------------- ;; -;; Copyright 1996-2014 The NASM Authors - All Rights Reserved +;; Copyright 1996-2016 The NASM Authors - All Rights Reserved ;; See the file AUTHORS included with the NASM distribution for ;; the specific copyright holders. ;; @@ -191,8 +191,8 @@ AND mem,imm32 [mi: hle o32 81 /4 id] 386,SM,LOCK AND rm8,imm [mi: hle 82 /4 ib] 8086,SM,LOCK,ND,NOLONG ARPL mem,reg16 [mr: 63 /r] 286,PROT,SM,NOLONG ARPL reg16,reg16 [mr: 63 /r] 286,PROT,NOLONG -BB0_RESET void [ 0f 3a] PENT,CYRIX,ND -BB1_RESET void [ 0f 3b] PENT,CYRIX,ND +BB0_RESET void [ 0f 3a] PENT,CYRIX,ND,OBSOLETE +BB1_RESET void [ 0f 3b] PENT,CYRIX,ND,OBSOLETE BOUND reg16,mem [rm: o16 62 /r] 186,NOLONG BOUND reg32,mem [rm: o32 62 /r] 386,NOLONG BSF reg16,mem [rm: o16 nof3 0f bc /r] 386,SM @@ -335,12 +335,12 @@ CMPXCHG mem,reg32 [mr: hle o32 0f b1 /r] PENT,SM,LOCK CMPXCHG reg32,reg32 [mr: o32 0f b1 /r] PENT CMPXCHG mem,reg64 [mr: hle o64 0f b1 /r] X64,SM,LOCK CMPXCHG reg64,reg64 [mr: o64 0f b1 /r] X64 -CMPXCHG486 mem,reg8 [mr: 0f a6 /r] 486,SM,UNDOC,ND,LOCK -CMPXCHG486 reg8,reg8 [mr: 0f a6 /r] 486,UNDOC,ND -CMPXCHG486 mem,reg16 [mr: o16 0f a7 /r] 486,SM,UNDOC,ND,LOCK -CMPXCHG486 reg16,reg16 [mr: o16 0f a7 /r] 486,UNDOC,ND -CMPXCHG486 mem,reg32 [mr: o32 0f a7 /r] 486,SM,UNDOC,ND,LOCK -CMPXCHG486 reg32,reg32 [mr: o32 0f a7 /r] 486,UNDOC,ND +CMPXCHG486 mem,reg8 [mr: 0f a6 /r] 486,SM,UNDOC,ND,LOCK,OBSOLETE +CMPXCHG486 reg8,reg8 [mr: 0f a6 /r] 486,UNDOC,ND,OBSOLETE +CMPXCHG486 mem,reg16 [mr: o16 0f a7 /r] 486,SM,UNDOC,ND,LOCK,OBSOLETE +CMPXCHG486 reg16,reg16 [mr: o16 0f a7 /r] 486,UNDOC,ND,OBSOLETE +CMPXCHG486 mem,reg32 [mr: o32 0f a7 /r] 486,SM,UNDOC,ND,LOCK,OBSOLETE +CMPXCHG486 reg32,reg32 [mr: o32 0f a7 /r] 486,UNDOC,ND,OBSOLETE CMPXCHG8B mem [m: hle norexw 0f c7 /1] PENT,LOCK CMPXCHG16B mem [m: o64 0f c7 /1] X64,LOCK CPUID void [ 0f a2] PENT @@ -585,10 +585,10 @@ FXTRACT void [ d9 f4] 8086,FPU FYL2X void [ d9 f1] 8086,FPU FYL2XP1 void [ d9 f9] 8086,FPU HLT void [ f4] 8086,PRIV -IBTS mem,reg16 [mr: o16 0f a7 /r] 386,SW,UNDOC,ND -IBTS reg16,reg16 [mr: o16 0f a7 /r] 386,UNDOC,ND -IBTS mem,reg32 [mr: o32 0f a7 /r] 386,SD,UNDOC,ND -IBTS reg32,reg32 [mr: o32 0f a7 /r] 386,UNDOC,ND +IBTS mem,reg16 [mr: o16 0f a7 /r] 386,SW,UNDOC,ND,OBSOLETE +IBTS reg16,reg16 [mr: o16 0f a7 /r] 386,UNDOC,ND,OBSOLETE +IBTS mem,reg32 [mr: o32 0f a7 /r] 386,SD,UNDOC,ND,OBSOLETE +IBTS reg32,reg32 [mr: o32 0f a7 /r] 386,UNDOC,ND,OBSOLETE ICEBP void [ f1] 386,ND IDIV rm8 [m: f6 /7] 8086 IDIV rm16 [m: o16 f7 /7] 8086 @@ -751,8 +751,8 @@ LLDT reg16 [m: 0f 00 /2] 286,PROT,PRIV LMSW mem [m: 0f 01 /6] 286,PRIV LMSW mem16 [m: 0f 01 /6] 286,PRIV LMSW reg16 [m: 0f 01 /6] 286,PRIV -LOADALL void [ 0f 07] 386,UNDOC,ND -LOADALL286 void [ 0f 05] 286,UNDOC,ND +LOADALL void [ 0f 07] 386,UNDOC,ND,OBSOLETE +LOADALL286 void [ 0f 05] 286,UNDOC,ND,OBSOLETE LODSB void [ ac] 8086 LODSD void [ o32 ad] 386 LODSQ void [ o64 ad] X64 @@ -1016,7 +1016,7 @@ POP rm16 [m: o16 8f /0] 8086 POP rm32 [m: o32 8f /0] 386,NOLONG POP rm64 [m: o64nw 8f /0] X64 POP reg_es [-: 07] 8086,NOLONG -POP reg_cs [-: 0f] 8086,UNDOC,ND +POP reg_cs [-: 0f] 8086,UNDOC,ND,OBSOLETE POP reg_ss [-: 17] 8086,NOLONG POP reg_ds [-: 1f] 8086,NOLONG POP reg_fs [-: 0f a1] 386 @@ -1287,7 +1287,7 @@ SKINIT void [ 0f 01 de] X64 SMI void [ f1] 386,UNDOC SMINT void [ 0f 38] P6,CYRIX,ND ; Older Cyrix chips had this; they had to move due to conflict with MMX -SMINTOLD void [ 0f 7e] 486,CYRIX,ND +SMINTOLD void [ 0f 7e] 486,CYRIX,ND,OBSOLETE SMSW mem [m: 0f 01 /4] 286 SMSW mem16 [m: 0f 01 /4] 286 SMSW reg16 [m: o16 0f 01 /4] 286 @@ -5116,6 +5116,9 @@ WRPKRU void [ 0f 01 ef] X64,FUTURE ; New memory instructions CLFLUSHOPT mem [m: 66 0f ae /7] FUTURE +CLWB mem [m: 66 0f ae /6] FUTURE +;# This one was killed before it saw the light of day +PCOMMIT void [ 66 0f ae f8] FUTURE,UNDOC,OBSOLETE ; AMD Zen v1 CLZERO void [ 0f 01 fc] FUTURE,AMD @@ -5314,4 +5317,3 @@ HINT_NOP62 rm64 [m: o64 0f 1f /6] X64,UNDOC HINT_NOP63 rm16 [m: o16 0f 1f /7] P6,UNDOC HINT_NOP63 rm32 [m: o32 0f 1f /7] P6,UNDOC HINT_NOP63 rm64 [m: o64 0f 1f /7] X64,UNDOC -