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testgen: add %ifdef ERROR error-case coverage, fix branch-operand bugs

Browse source 
Add error-case ("negative test") coverage per the user's preferred
convention: rather than a separate source file, error-triggering
instruction lines are appended to the existing per-mnemonic .asm file
under a %ifdef ERROR guard, and the harness assembles the same file
twice -- once without -DERROR (existing positive-path coverage,
unaffected) and once with -DERROR (expected to fail, per nasm-t.py's
"error": "expected" json convention, matching the pre-existing
travis/ret/ret.json pattern).

The error material comes for free from lines the generator already
knows are bit-width-incompatible:

- Lines needing 64-bit encodings (reg64/imm64 operands, hireg r8-r15,
  apxreg r16-r31, etc. -- %needs64_token / build_variant_line) are, by
  construction, exactly the lines already excluded from the 16/32-bit
  "narrow" body. They're appended to the narrow file under %ifdef
  ERROR and probed at --bits 16/32 with -DERROR; only widths where the
  block actually fails become json entries.

- Symmetrically, CALL/JMP near-indirect targets via rm16/rm32 (only
  rm64 is valid in 64-bit mode -- confirmed empirically, matches the
  NOLONG flag on those insns.xda templates) are appended to the full
  (64-bit) body under %ifdef ERROR and probed at --bits 64 with
  -DERROR.

Each candidate block is probed before being turned into a json entry,
so a line that unexpectedly *does* assemble at some width (this
generator doesn't model every mode restriction) doesn't turn into a
bogus "expected error" test; a mnemonic whose *only* surviving
coverage would be error entries is also rejected (see below), since
"this never assembles" isn't meaningful regression coverage on its
own.

While wiring this up, discovered and fixed two related bugs in the
existing branch-mnemonic handling (gen_operand()'s is_branch
substitution):

1. is_branch replaced *every* operand of a branch mnemonic with the
   ".L1" local-label text, not just genuine relative/near/short/abs
   branch-displacement operands. This produced nonsensical lines like
   "loop .L1, .L1" (LOOP's address-size-override form takes a fixed
   "cx"/"ecx"/"rcx" second operand, not a branch target) and "call
   .L1" for JMP/CALL's indirect (rm16/32/64) and far-pointer
   (imm16:imm16) forms instead of an actual register/memory operand.
   These bogus lines silently poisoned assembly for the whole
   mnemonic, and LOOP/LOOPE/LOOPNE/LOOPNZ/LOOPZ/JCXZ were silently
   dropped entirely as a result (present in the "16 dropped" list).
   Restricting the substitution to base tokens matching
   /^imm(?:8|16|32|64)$/ fixes both LOOP's operand and JMP/CALL's
   indirect/far forms, and recovers all six previously-dropped
   mnemonics with correct coverage.

2. Once (1) exposed genuine rm16/rm32 operand generation for CALL/JMP,
   a new bit-width interaction appeared: rm16/rm32 near-indirect
   targets are only valid in 16/32-bit mode (unlike ordinary reg16/32
   operands elsewhere, which work at any bit width), so a line built
   from one now broke 64-bit assembly for the whole mnemonic the same
   way a needs64 line breaks 16/32-bit assembly. Added
   branch_narrow_only() and a parallel avoid64 line flag (mirroring
   needs64) to exclude these lines from the 64-bit "full" body -- this
   is also what feeds the new symmetric 64-bit error-case coverage
   described above.

Also added a safety-net to the existing "couldn't assemble in any
mode, drop the directory" check: a directory is now only kept if it
has at least one *non*-error json entry, preventing a future bug
symmetric to (1) from silently producing a directory whose only
content is error-case entries.

Verified via full scratch regeneration (2612 mnemonics generated / 10
dropped, up from 2606/16 thanks to the LOOP-family/JCXZ fix) +
nasm-t.py run (10918/10918 PASS, 0 FAIL) + per-mnemonic non-error
.json entry-count diff against the prior committed tree (identical
except the 6 newly-recovered mnemonics, confirming no regressions).
1976/2612 mnemonics gained at least one error-case entry (3951 error
json entries total). Regenerated travis/insns/ and validated via
'make -j32 travis' (all PASS, ~27s).

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
This commit is contained in:
H. Peter Anvin (Intel) 2026-07-04 13:41:59 -07:00
parent 6de2898d8d
commit eee1384bf5
7981 changed files with 89508 additions and 54 deletions
Download patch file Download diff file Expand all files Collapse all files

169
tools/testgen/gen-insn-tests.pl
View file

@ -404,7 +404,17 @@ sub base_token {
sub gen_operand {
my ($rng, $tok, $mnem, $is_branch, $variant) = @_;
my $base = base_token($tok);
if ($is_branch) {
# Only genuine relative/near/short/abs branch-displacement operands
# (plain imm8/16/32/64, before the trailing "|near"/"|short"/"|abs"
# qualifier that base_token() already stripped) get replaced with a
# local label -- NOT every operand of a "branch mnemonic". Some
# branch mnemonics also have indirect (rm16/32/64), far-pointer
# (colon-compound "imm16:imm16"), or fixed-register (reg_cx, for
# LOOP's address-size-override form) operand forms, none of which
# are relative-displacement targets, and would otherwise get
# nonsensically replaced with the branch label too (producing
# invalid syntax like "loop .L1, .L1" instead of "loop .L1, cx").
if ($is_branch && $base =~ /^imm(?:8|16|32|64)$/) {
return '.L1';
}
if (exists $fixed{$base}) {
@ -417,6 +427,21 @@ sub gen_operand {
return undef;
}
# CALL/JMP near-indirect targets (the only branch-mnemonic templates
# with rm*-typed operands) restrict the operand-size override: rm64 is
# the only form valid in 64-bit mode -- rm16/rm32 forms genuinely only
# assemble in 16/32-bit mode (confirmed empirically: "call cx"/
# "call ecx" both fail under --bits 64, matching the NOLONG flag on
# those insns.xda templates). This is unrelated to %needs64_token
# (which flags the opposite direction -- 64-bit-*only* operands), so a
# separate helper marks lines built from these tokens as excluded from
# the 64-bit "full" body, mirroring how needs64 lines are excluded from
# the 16/32-bit "narrow" body.
sub branch_narrow_only {
my ($is_branch, $base) = @_;
return ($is_branch && $base =~ /^rm(?:16|32)$/) ? 1 : 0;
}
# Base tokens whose register pool has hireg (r8-r15 range) / apxreg
# (r16-r31 range) tiers available -- i.e. templates containing at
# least one of these are candidates for the extra register-number-
@ -632,6 +657,7 @@ sub build_dispboundary_line {
my @operands;
my $used_mem = 0;
my $needs64 = 0;
my $avoid64 = 0;
for my $tok (@$ops) {
my $base = base_token($tok);
if (!$used_mem && exists $mem_sizebits{$base}) {
@ -640,15 +666,17 @@ sub build_dispboundary_line {
$txt = "$memsize{$sizebits} $txt" if $sizebits && $memsize{$sizebits};
push @operands, $txt;
$used_mem = 1;
$avoid64 = 1 if branch_narrow_only($is_branch, $base);
next;
}
my $val = gen_operand($rng, $tok, $mnem, $is_branch);
return undef unless defined $val;
$needs64 = 1 if $needs64_token{$base};
$avoid64 = 1 if branch_narrow_only($is_branch, $base);
push @operands, $val;
}
return undef unless $used_mem;
return { text => lc($mnem) . ' ' . join(', ', @operands), needs64 => $needs64 };
return { text => lc($mnem) . ' ' . join(', ', @operands), needs64 => $needs64, avoid64 => $avoid64 };
}
# Implicitly-sized memory operand coverage.
@ -677,20 +705,23 @@ sub build_implicitsize_line {
my @operands;
my $used_mem = 0;
my $needs64 = 0;
my $avoid64 = 0;
for my $tok (@$ops) {
my $base = base_token($tok);
if (!$used_mem && ($mem_sizebits{$base} // 0)) {
push @operands, mem_operand($rng, 0);
$used_mem = 1;
$avoid64 = 1 if branch_narrow_only($is_branch, $base);
next;
}
my $val = gen_operand($rng, $tok, $mnem, $is_branch);
return undef unless defined $val;
$needs64 = 1 if $needs64_token{$base};
$avoid64 = 1 if branch_narrow_only($is_branch, $base);
push @operands, $val;
}
return undef unless $used_mem;
return { text => lc($mnem) . ' ' . join(', ', @operands), needs64 => $needs64 };
return { text => lc($mnem) . ' ' . join(', ', @operands), needs64 => $needs64, avoid64 => $avoid64 };
}
sub make_rng {
@ -768,16 +799,20 @@ for my $mnem (sort keys %by_mnemonic) {
my @operands;
my $ok = 1;
my $needs64 = 0;
my $avoid64 = 0;
for my $tok (@{ $t->{ops} }) {
my $val = gen_operand($rng, $tok, $mnem, $is_branch);
if (!defined $val) { $ok = 0; last; }
$needs64 = 1 if $needs64_token{ base_token($tok) };
my $base = base_token($tok);
$needs64 = 1 if $needs64_token{$base};
$avoid64 = 1 if branch_narrow_only($is_branch, $base);
push @operands, $val;
}
next unless $ok;
push @lines, {
text => lc($mnem) . (@operands ? ' ' . join(', ', @operands) : ''),
needs64 => $needs64,
avoid64 => $avoid64,
};
# Optional-operand ('*'/'?') coverage: also emit the
@ -791,9 +826,11 @@ for my $mnem (sort keys %by_mnemonic) {
push @lines, {
text => lc($mnem) . (@reduced ? ' ' . join(', ', @reduced) : ''),
needs64 => $needs64,
avoid64 => $avoid64,
};
}
# Register-number coverage: once per template (not once per
# --variants instance), also try building an all-hireg
# (r8-r15/xmm8-15/...) and an all-apxreg (r16-r31/xmm16-31)
@ -848,7 +885,17 @@ for my $mnem (sort keys %by_mnemonic) {
for my $t (@dedup_all) {
for my $disp (1, 64) {
my $dl = build_dispboundary_line($rng, $mnem, $t->{ops}, $is_branch, $disp);
push @extra_dispboundary, $dl if defined $dl;
# avoid64 candidates (CALL/JMP rm16/rm32 near-indirect
# targets -- see branch_narrow_only()) are dropped here
# rather than fed into the bits=64 probe: they're
# guaranteed to fail at 64-bit, and folding them into this
# bucket would either cost the whole bucket its otherwise-
# valid candidates (probe rejects the merge) or need a
# second parallel probe path for no real benefit, since
# this supplementary boundary coverage isn't the base
# per-mnemonic content the 64-bit error-case block (below)
# is built from.
push @extra_dispboundary, $dl if defined $dl && !$dl->{avoid64};
}
}
@ -861,12 +908,21 @@ for my $mnem (sort keys %by_mnemonic) {
# which this generator doesn't parse directly (see comment above).
for my $t (@dedup_all) {
my $dl = build_implicitsize_line($rng, $mnem, $t->{ops}, $is_branch);
push @extra_implicitsize, $dl if defined $dl;
push @extra_implicitsize, $dl if defined $dl && !$dl->{avoid64};
}
next unless @lines; # nothing we knew how to generate
my @narrow_lines = grep { !$_->{needs64} } @lines;
# Lines that only assemble in 16/32-bit mode (currently just
# CALL/JMP rm16/rm32 near-indirect targets -- branch_narrow_only())
# must symmetrically be excluded from the 64-bit "full" body: they
# aren't flagged needs64 (they don't require 64-bit -- the opposite
# holds, they're incompatible with it), so they'd otherwise poison
# bits=64 assembly for the *entire* file the same way a needs64
# line would poison bits=16/32.
my @lines64 = grep { !$_->{avoid64} } @lines;
my $dirname = "$out_dir/" . lc($mnem);
make_path($dirname);
@ -923,7 +979,7 @@ for my $mnem (sort keys %by_mnemonic) {
return $ok;
};
my @full_lines = @lines;
my @full_lines = @lines64;
for my $cat (\@extra_hireg, \@extra_apxreg, \@extra_mask, \@extra_maskz,
\@extra_broadcast, \@extra_saeer, \@extra_dispboundary,
\@extra_implicitsize) {
@ -945,6 +1001,47 @@ for my $mnem (sort keys %by_mnemonic) {
close($nfh);
}
# Error-case coverage: lines that only assemble in 64-bit mode
# (reg64/imm64 operands, hireg r8-r15, apxreg r16-r31, etc. -- see
# %needs64_token / build_variant_line) are, by construction, exactly
# the lines excluded from the 16/32-bit "narrow" body above. Rather
# than inventing a separate error-only source file, append them to
# the *same* narrow file under a %ifdef ERROR guard (per the user's
# preferred convention: one .asm file, assembled twice -- with and
# without -DERROR). Without -DERROR the block is invisible and
# narrow-mode coverage is unaffected; with -DERROR the block is
# included and attempting to assemble it at --bits 16/32 should
# fail with a mode/operand-mismatch diagnostic, which is exactly
# the negative-test coverage we want. Each bit width is probed
# independently below and only kept if it actually fails, so a line
# that unexpectedly *does* assemble at some width (this generator
# doesn't model every mode restriction) doesn't turn into a bogus
# "expected error" test.
my @error_lines = grep { $_->{needs64} } @full_lines;
my $has_narrow_file = ($asmfile_narrow ne $asmfile_full);
if ($has_narrow_file && @error_lines) {
open(my $efh, '>>', "$dirname/$asmfile_narrow") or die $!;
print $efh "\n%ifdef ERROR\n";
print $efh join('', map { "\t$_->{text}\n" } @error_lines);
print $efh "%endif\n";
close($efh);
}
# Symmetric case: lines that only assemble in 16/32-bit mode
# (CALL/JMP rm16/rm32 near-indirect targets -- branch_narrow_only())
# are excluded from @full_lines above; append them to the *full*
# (64-bit) body under the same %ifdef ERROR convention, so
# attempting to assemble them at --bits 64 with -DERROR is
# exercised as an expected-error case too.
my @error64_lines = grep { $_->{avoid64} } @lines;
if (@error64_lines) {
open(my $e6fh, '>>', "$dirname/$asmfile_full") or die $!;
print $e6fh "\n%ifdef ERROR\n";
print $e6fh join('', map { "\t$_->{text}\n" } @error64_lines);
print $e6fh "%endif\n";
close($e6fh);
}
my @json_entries;
for my $bits (16, 32, 64) {
my $asmfile = ($bits == 64 || !@narrow_lines) ? $asmfile_full : $asmfile_narrow;
@ -979,9 +1076,47 @@ for my $mnem (sort keys %by_mnemonic) {
}
}
if (!@json_entries) {
# Error-case coverage: probe the %ifdef ERROR block(s) appended
# above with -DERROR defined, and only turn each into a json
# "expected error" entry for the (source file, bit width) pairs
# where it actually fails to assemble.
my $probe_error_bits = sub {
my ($src, @bitlist) = @_;
for my $bits (@bitlist) {
my $errbin = lc($mnem) . ".errprobe$bits.bin";
my $errstderr = lc($mnem) . ".stderr${bits}err";
my $relsrc = "$dirref/$src";
my $cmd = sprintf('%s --bits %d -DERROR -f bin %s %s -o %s.tmp 2>%s',
$nasm_bin, $bits, $warn_opts, $relsrc,
"$dirname/$errbin", "$dirname/$errstderr");
system($cmd);
my $rc = $? >> 8;
unlink("$dirname/$errbin.tmp");
my $fails = ($rc != 0);
unlink("$dirname/$errstderr");
if ($fails) {
push @json_entries, {
id => lc($mnem) . $bits . 'err',
bits => $bits,
source => $src,
opts => "-DERROR $warn_opts",
stderr => $errstderr,
is_error => 1,
};
}
}
};
$probe_error_bits->($asmfile_narrow, 16, 32) if $has_narrow_file && @error_lines;
$probe_error_bits->($asmfile_full, 64) if @error64_lines;
if (!grep { !$_->{is_error} } @json_entries) {
# Couldn't assemble in any mode -- drop the whole directory,
# don't leave a dangling/empty test case behind.
# don't leave a dangling/empty test case behind. (Error-case
# entries alone don't count: a directory whose only "coverage"
# is "this asm never assembles" isn't meaningful regression
# coverage and would only mask a real generation bug -- see
# the is_branch operand-substitution fix above, discovered via
# exactly this scenario.)
unlink("$dirname/$asmfile_full");
unlink("$dirname/$asmfile_narrow") if $asmfile_narrow ne $asmfile_full;
rmdir($dirname);
@ -995,6 +1130,22 @@ for my $mnem (sort keys %by_mnemonic) {
for my $e (@json_entries) {
print $jf ",\n" unless $first;
$first = 0;
if ($e->{is_error}) {
printf $jf <<"JSON", $mnem, $e->{id}, $e->{source}, $e->{bits}, $e->{opts}, $dirname, $e->{stderr};
{
"description": "Pseudorandom error-case test for %s",
"id": "%s",
"format": "bin",
"source": "%s",
"option": "--bits %d %s -I./%s/",
"target": [
{ "stderr": "%s" }
],
"error": "expected"
}
JSON
next;
}
my $stderr_target = $e->{stderr}
? qq(,\n { "stderr": "$e->{stderr}" })
: '';

24
travis/insns/aadd/aadd.json
View file

@ -9,4 +9,28 @@
{ "output": "aadd.bin64", "match": "aadd.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for AADD",
"id": "aadd16err",
"format": "bin",
"source": "aadd_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aadd/",
"target": [
{ "stderr": "aadd.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AADD",
"id": "aadd32err",
"format": "bin",
"source": "aadd_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aadd/",
"target": [
{ "stderr": "aadd.stderr32err" }
],
"error": "expected"
}
]

11
travis/insns/aadd/aadd.stderr16err Normal file
View file

@ -0,0 +1,11 @@
./travis/insns/aadd/aadd_narrow.asm:1: error: instruction not supported in 16-bit mode
./travis/insns/aadd/aadd_narrow.asm:2: error: instruction not supported in 16-bit mode
./travis/insns/aadd/aadd_narrow.asm:5: error: instruction not supported in 16-bit mode
./travis/insns/aadd/aadd_narrow.asm:6: error: instruction not supported in 16-bit mode
./travis/insns/aadd/aadd_narrow.asm:7: error: instruction not supported in 16-bit mode
./travis/insns/aadd/aadd_narrow.asm:8: error: instruction not supported in 16-bit mode
./travis/insns/aadd/aadd_narrow.asm:9: error: instruction not supported in 16-bit mode
./travis/insns/aadd/aadd_narrow.asm:10: error: instruction not supported in 16-bit mode
./travis/insns/aadd/aadd_narrow.asm:11: error: instruction not supported in 16-bit mode
./travis/insns/aadd/aadd_narrow.asm:12: error: instruction not supported in 16-bit mode
./travis/insns/aadd/aadd_narrow.asm:13: error: instruction not supported in 16-bit mode

11
travis/insns/aadd/aadd.stderr32err Normal file
View file

@ -0,0 +1,11 @@
./travis/insns/aadd/aadd_narrow.asm:1: error: instruction not supported in 32-bit mode
./travis/insns/aadd/aadd_narrow.asm:2: error: instruction not supported in 32-bit mode
./travis/insns/aadd/aadd_narrow.asm:5: error: instruction not supported in 32-bit mode
./travis/insns/aadd/aadd_narrow.asm:6: error: instruction not supported in 32-bit mode
./travis/insns/aadd/aadd_narrow.asm:7: error: instruction not supported in 32-bit mode
./travis/insns/aadd/aadd_narrow.asm:8: error: instruction not supported in 32-bit mode
./travis/insns/aadd/aadd_narrow.asm:9: error: instruction not supported in 32-bit mode
./travis/insns/aadd/aadd_narrow.asm:10: error: instruction not supported in 32-bit mode
./travis/insns/aadd/aadd_narrow.asm:11: error: instruction not supported in 32-bit mode
./travis/insns/aadd/aadd_narrow.asm:12: error: instruction not supported in 32-bit mode
./travis/insns/aadd/aadd_narrow.asm:13: error: instruction not supported in 32-bit mode

12
travis/insns/aadd/aadd_narrow.asm
View file

@ -1,2 +1,14 @@
aadd dword [0xe1b], ebx
aadd dword [0x7dc], ecx
%ifdef ERROR
aadd qword [0xeca], rcx
aadd qword [0x4e4], rcx
aadd dword [0xbc9], r13d
aadd qword [0xa2a], r10
aadd dword [0xcad], r16d
aadd qword [0x5c3], r17
aadd qword [eax+1], rbx
aadd qword [eax+64], rcx
aadd [0x5d8], rdi
%endif

24
travis/insns/aand/aand.json
View file

@ -9,4 +9,28 @@
{ "output": "aand.bin64", "match": "aand.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for AAND",
"id": "aand16err",
"format": "bin",
"source": "aand_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aand/",
"target": [
{ "stderr": "aand.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AAND",
"id": "aand32err",
"format": "bin",
"source": "aand_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aand/",
"target": [
{ "stderr": "aand.stderr32err" }
],
"error": "expected"
}
]

11
travis/insns/aand/aand.stderr16err Normal file
View file

@ -0,0 +1,11 @@
./travis/insns/aand/aand_narrow.asm:1: error: instruction not supported in 16-bit mode
./travis/insns/aand/aand_narrow.asm:2: error: instruction not supported in 16-bit mode
./travis/insns/aand/aand_narrow.asm:5: error: instruction not supported in 16-bit mode
./travis/insns/aand/aand_narrow.asm:6: error: instruction not supported in 16-bit mode
./travis/insns/aand/aand_narrow.asm:7: error: instruction not supported in 16-bit mode
./travis/insns/aand/aand_narrow.asm:8: error: instruction not supported in 16-bit mode
./travis/insns/aand/aand_narrow.asm:9: error: instruction not supported in 16-bit mode
./travis/insns/aand/aand_narrow.asm:10: error: instruction not supported in 16-bit mode
./travis/insns/aand/aand_narrow.asm:11: error: instruction not supported in 16-bit mode
./travis/insns/aand/aand_narrow.asm:12: error: instruction not supported in 16-bit mode
./travis/insns/aand/aand_narrow.asm:13: error: instruction not supported in 16-bit mode

11
travis/insns/aand/aand.stderr32err Normal file
View file

@ -0,0 +1,11 @@
./travis/insns/aand/aand_narrow.asm:1: error: instruction not supported in 32-bit mode
./travis/insns/aand/aand_narrow.asm:2: error: instruction not supported in 32-bit mode
./travis/insns/aand/aand_narrow.asm:5: error: instruction not supported in 32-bit mode
./travis/insns/aand/aand_narrow.asm:6: error: instruction not supported in 32-bit mode
./travis/insns/aand/aand_narrow.asm:7: error: instruction not supported in 32-bit mode
./travis/insns/aand/aand_narrow.asm:8: error: instruction not supported in 32-bit mode
./travis/insns/aand/aand_narrow.asm:9: error: instruction not supported in 32-bit mode
./travis/insns/aand/aand_narrow.asm:10: error: instruction not supported in 32-bit mode
./travis/insns/aand/aand_narrow.asm:11: error: instruction not supported in 32-bit mode
./travis/insns/aand/aand_narrow.asm:12: error: instruction not supported in 32-bit mode
./travis/insns/aand/aand_narrow.asm:13: error: instruction not supported in 32-bit mode

12
travis/insns/aand/aand_narrow.asm
View file

@ -1,2 +1,14 @@
aand dword [0x9d7], edi
aand dword [0xa64], ebx
%ifdef ERROR
aand qword [0x371], rbp
aand qword [0xf0b], rbx
aand dword [0x32c], r14d
aand qword [0x765], r9
aand dword [0x205], r28d
aand qword [0x3bd], r23
aand qword [eax+1], rdx
aand qword [eax+64], rsi
aand [0x77b], rdx
%endif

24
travis/insns/adc/adc.json
View file

@ -32,4 +32,28 @@
{ "stderr": "adc.stderr64" }
]
}
,
{
"description": "Pseudorandom error-case test for ADC",
"id": "adc16err",
"format": "bin",
"source": "adc_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/adc/",
"target": [
{ "stderr": "adc.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for ADC",
"id": "adc32err",
"format": "bin",
"source": "adc_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/adc/",
"target": [
{ "stderr": "adc.stderr32err" }
],
"error": "expected"
}
]

32
travis/insns/adc/adc.stderr16err Normal file
View file

@ -0,0 +1,32 @@
./travis/insns/adc/adc_narrow.asm:9: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:10: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:11: error: invalid operands in 16-bit mode
./travis/insns/adc/adc_narrow.asm:12: error: invalid operands in 16-bit mode
./travis/insns/adc/adc_narrow.asm:13: error: invalid operands in 16-bit mode
./travis/insns/adc/adc_narrow.asm:14: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:15: error: invalid operands in 16-bit mode
./travis/insns/adc/adc_narrow.asm:16: error: invalid operands in 16-bit mode
./travis/insns/adc/adc_narrow.asm:17: error: invalid operands in 16-bit mode
./travis/insns/adc/adc_narrow.asm:18: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:19: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:20: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:21: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:22: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:23: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:24: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:25: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:26: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:27: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:28: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:29: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:30: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:31: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:32: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:33: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:34: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:35: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:36: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:39: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:40: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:41: error: instruction not supported in 16-bit mode
./travis/insns/adc/adc_narrow.asm:42: error: instruction not supported in 16-bit mode

32
travis/insns/adc/adc.stderr32err Normal file
View file

@ -0,0 +1,32 @@
./travis/insns/adc/adc_narrow.asm:9: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:10: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:11: error: invalid operands in 32-bit mode
./travis/insns/adc/adc_narrow.asm:12: error: invalid operands in 32-bit mode
./travis/insns/adc/adc_narrow.asm:13: error: invalid operands in 32-bit mode
./travis/insns/adc/adc_narrow.asm:14: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:15: error: invalid operands in 32-bit mode
./travis/insns/adc/adc_narrow.asm:16: error: invalid operands in 32-bit mode
./travis/insns/adc/adc_narrow.asm:17: error: invalid operands in 32-bit mode
./travis/insns/adc/adc_narrow.asm:18: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:19: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:20: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:21: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:22: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:23: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:24: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:25: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:26: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:27: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:28: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:29: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:30: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:31: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:32: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:33: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:34: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:35: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:36: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:39: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:40: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:41: error: instruction not supported in 32-bit mode
./travis/insns/adc/adc_narrow.asm:42: error: instruction not supported in 32-bit mode

37
travis/insns/adc/adc_narrow.asm
View file

@ -4,3 +4,40 @@
adc bp, bp
adc eax, ecx
adc ebx, ecx
%ifdef ERROR
adc rax, rdi
adc qword [0x926], rsi
adc r15b, r8b
adc r11w, r9w
adc r11d, r14d
adc r9, r13
adc r28b, r16b
adc r16w, r27w
adc r17d, r24d
adc r26, r16
adc qword [eax+1], rsi
adc qword [eax+64], rbx
adc rdi, qword [eax+1]
adc rdx, qword [eax+64]
adc qword [eax+1], -25
adc qword [eax+64], -121
adc qword [eax+1], -506139423
adc qword [eax+64], -173191687
adc rax, rax, qword [eax+1]
adc rdx, rdx, qword [eax+64]
adc rdi, qword [eax+1], rdx
adc rdi, qword [eax+64], rsi
adc rdi, qword [eax+1], 24
adc rsi, qword [eax+64], -73
adc rsi, qword [eax+1], -428886289
adc rsi, qword [eax+64], 6139295
adc [0x31c], rdx
adc rdx, [0x342]
adc [0x92a], -90
adc [0x7a2], 41191012
adc rbp, rbp, [0x4f1]
adc rbp, [0x906], rbp
adc rdx, [0x7d0], 59
adc rdi, [0x7e4], 220977984
%endif

24
travis/insns/adcx/adcx.json
View file

@ -9,4 +9,28 @@
{ "output": "adcx.bin64", "match": "adcx.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for ADCX",
"id": "adcx16err",
"format": "bin",
"source": "adcx_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/adcx/",
"target": [
{ "stderr": "adcx.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for ADCX",
"id": "adcx32err",
"format": "bin",
"source": "adcx_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/adcx/",
"target": [
{ "stderr": "adcx.stderr32err" }
],
"error": "expected"
}
]

21
travis/insns/adcx/adcx.stderr16err Normal file
View file

@ -0,0 +1,21 @@
./travis/insns/adcx/adcx_narrow.asm:3: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:5: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:8: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:9: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:10: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:11: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:12: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:13: error: invalid operands in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:14: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:15: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:16: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:17: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:18: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:19: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:20: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:21: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:22: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:23: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:24: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:25: error: instruction not supported in 16-bit mode
./travis/insns/adcx/adcx_narrow.asm:26: error: instruction not supported in 16-bit mode

21
travis/insns/adcx/adcx.stderr32err Normal file
View file

@ -0,0 +1,21 @@
./travis/insns/adcx/adcx_narrow.asm:3: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:5: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:8: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:9: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:10: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:11: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:12: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:13: error: invalid operands in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:14: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:15: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:16: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:17: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:18: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:19: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:20: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:21: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:22: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:23: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:24: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:25: error: instruction not supported in 32-bit mode
./travis/insns/adcx/adcx_narrow.asm:26: error: instruction not supported in 32-bit mode

22
travis/insns/adcx/adcx_narrow.asm
View file

@ -3,3 +3,25 @@
adcx ebp, esi, eax
adcx esi, eax
adcx eax, esi, ecx
%ifdef ERROR
adcx rdi, rax
adcx rdi, rax
adcx rsi, rbx, rdi
adcx rbx, rdi
adcx rdx, rdx, qword [0x715]
adcx r13d, r14d
adcx r11, r12
adcx r9d, r11d, r14d
adcx r8, r12, r9
adcx r17d, r29d
adcx r17, r29
adcx r18d, r26d, r16d
adcx r20, r23, r31
adcx rdi, qword [eax+1]
adcx rbx, qword [eax+64]
adcx rdi, rax, qword [eax+1]
adcx rax, rbx, qword [eax+64]
adcx rbx, [0x3eb]
adcx rdx, rdx, [0xffe]
%endif

24
travis/insns/add/add.json
View file

@ -32,4 +32,28 @@
{ "stderr": "add.stderr64" }
]
}
,
{
"description": "Pseudorandom error-case test for ADD",
"id": "add16err",
"format": "bin",
"source": "add_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/add/",
"target": [
{ "stderr": "add.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for ADD",
"id": "add32err",
"format": "bin",
"source": "add_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/add/",
"target": [
{ "stderr": "add.stderr32err" }
],
"error": "expected"
}
]

32
travis/insns/add/add.stderr16err Normal file
View file

@ -0,0 +1,32 @@
./travis/insns/add/add_narrow.asm:9: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:10: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:11: error: invalid operands in 16-bit mode
./travis/insns/add/add_narrow.asm:12: error: invalid operands in 16-bit mode
./travis/insns/add/add_narrow.asm:13: error: invalid operands in 16-bit mode
./travis/insns/add/add_narrow.asm:14: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:15: error: invalid operands in 16-bit mode
./travis/insns/add/add_narrow.asm:16: error: invalid operands in 16-bit mode
./travis/insns/add/add_narrow.asm:17: error: invalid operands in 16-bit mode
./travis/insns/add/add_narrow.asm:18: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:19: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:20: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:21: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:22: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:23: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:24: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:25: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:26: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:27: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:28: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:29: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:30: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:31: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:32: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:33: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:34: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:35: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:36: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:39: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:40: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:41: error: instruction not supported in 16-bit mode
./travis/insns/add/add_narrow.asm:42: error: instruction not supported in 16-bit mode

32
travis/insns/add/add.stderr32err Normal file
View file

@ -0,0 +1,32 @@
./travis/insns/add/add_narrow.asm:9: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:10: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:11: error: invalid operands in 32-bit mode
./travis/insns/add/add_narrow.asm:12: error: invalid operands in 32-bit mode
./travis/insns/add/add_narrow.asm:13: error: invalid operands in 32-bit mode
./travis/insns/add/add_narrow.asm:14: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:15: error: invalid operands in 32-bit mode
./travis/insns/add/add_narrow.asm:16: error: invalid operands in 32-bit mode
./travis/insns/add/add_narrow.asm:17: error: invalid operands in 32-bit mode
./travis/insns/add/add_narrow.asm:18: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:19: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:20: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:21: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:22: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:23: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:24: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:25: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:26: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:27: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:28: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:29: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:30: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:31: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:32: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:33: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:34: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:35: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:36: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:39: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:40: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:41: error: instruction not supported in 32-bit mode
./travis/insns/add/add_narrow.asm:42: error: instruction not supported in 32-bit mode

37
travis/insns/add/add_narrow.asm
View file

@ -4,3 +4,40 @@
add di, di
add dword [0xa9d], ecx
add esi, ebp
%ifdef ERROR
add rax, rcx
add rbp, rdi
add r14b, r13b
add r14w, r12w
add r12d, r15d
add r12, r15
add r20b, r24b
add r19w, r16w
add r22d, r27d
add r25, r21
add qword [eax+1], rbp
add qword [eax+64], rbx
add rcx, qword [eax+1]
add rcx, qword [eax+64]
add qword [eax+1], -7
add qword [eax+64], -32
add qword [eax+1], -196667217
add qword [eax+64], -49947754
add rsi, rdi, qword [eax+1]
add rsi, rcx, qword [eax+64]
add rdi, qword [eax+1], rsi
add rax, qword [eax+64], rax
add rbp, qword [eax+1], 68
add rcx, qword [eax+64], 53
add rdi, qword [eax+1], 455876284
add rsi, qword [eax+64], -93805067
add [0x9c6], rax
add rax, [0x46d]
add [0x23e], 26
add [0xdf9], -30949254
add rbp, rbx, [0xe78]
add rdi, [0xf51], rsi
add rsi, [0x8fe], -1
add rdx, [0x5d5], 232948762
%endif

24
travis/insns/addpd/addpd.json
View file

@ -31,4 +31,28 @@
{ "output": "addpd.bin64", "match": "addpd.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for ADDPD",
"id": "addpd16err",
"format": "bin",
"source": "addpd_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/addpd/",
"target": [
{ "stderr": "addpd.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for ADDPD",
"id": "addpd32err",
"format": "bin",
"source": "addpd_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/addpd/",
"target": [
{ "stderr": "addpd.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/addpd/addpd.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/addpd/addpd_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/addpd/addpd.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/addpd/addpd_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/addpd/addpd_narrow.asm
View file

@ -1,2 +1,6 @@
addpd xmm3, xmm5
addpd xmm5, xmm2
%ifdef ERROR
addpd xmm9, xmm8
%endif

24
travis/insns/addps/addps.json
View file

@ -31,4 +31,28 @@
{ "output": "addps.bin64", "match": "addps.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for ADDPS",
"id": "addps16err",
"format": "bin",
"source": "addps_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/addps/",
"target": [
{ "stderr": "addps.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for ADDPS",
"id": "addps32err",
"format": "bin",
"source": "addps_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/addps/",
"target": [
{ "stderr": "addps.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/addps/addps.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/addps/addps_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/addps/addps.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/addps/addps_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/addps/addps_narrow.asm
View file

@ -1,2 +1,6 @@
addps xmm4, xmm1
addps xmm3, xmm2
%ifdef ERROR
addps xmm14, xmm12
%endif

24
travis/insns/addsd/addsd.json
View file

@ -31,4 +31,28 @@
{ "output": "addsd.bin64", "match": "addsd.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for ADDSD",
"id": "addsd16err",
"format": "bin",
"source": "addsd_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/addsd/",
"target": [
{ "stderr": "addsd.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for ADDSD",
"id": "addsd32err",
"format": "bin",
"source": "addsd_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/addsd/",
"target": [
{ "stderr": "addsd.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/addsd/addsd.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/addsd/addsd_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/addsd/addsd.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/addsd/addsd_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/addsd/addsd_narrow.asm
View file

@ -1,2 +1,6 @@
addsd xmm2, xmm7
addsd xmm3, xmm0
%ifdef ERROR
addsd xmm12, xmm9
%endif

24
travis/insns/addss/addss.json
View file

@ -31,4 +31,28 @@
{ "output": "addss.bin64", "match": "addss.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for ADDSS",
"id": "addss16err",
"format": "bin",
"source": "addss_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/addss/",
"target": [
{ "stderr": "addss.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for ADDSS",
"id": "addss32err",
"format": "bin",
"source": "addss_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/addss/",
"target": [
{ "stderr": "addss.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/addss/addss.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/addss/addss_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/addss/addss.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/addss/addss_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/addss/addss_narrow.asm
View file

@ -1,2 +1,6 @@
addss xmm2, xmm3
addss xmm4, xmm2
%ifdef ERROR
addss xmm15, xmm12
%endif

24
travis/insns/addsubpd/addsubpd.json
View file

@ -31,4 +31,28 @@
{ "output": "addsubpd.bin64", "match": "addsubpd.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for ADDSUBPD",
"id": "addsubpd16err",
"format": "bin",
"source": "addsubpd_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/addsubpd/",
"target": [
{ "stderr": "addsubpd.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for ADDSUBPD",
"id": "addsubpd32err",
"format": "bin",
"source": "addsubpd_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/addsubpd/",
"target": [
{ "stderr": "addsubpd.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/addsubpd/addsubpd.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/addsubpd/addsubpd_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/addsubpd/addsubpd.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/addsubpd/addsubpd_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/addsubpd/addsubpd_narrow.asm
View file

@ -1,2 +1,6 @@
addsubpd xmm6, xmm3
addsubpd xmm5, xmm2
%ifdef ERROR
addsubpd xmm8, xmm12
%endif

24
travis/insns/addsubps/addsubps.json
View file

@ -31,4 +31,28 @@
{ "output": "addsubps.bin64", "match": "addsubps.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for ADDSUBPS",
"id": "addsubps16err",
"format": "bin",
"source": "addsubps_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/addsubps/",
"target": [
{ "stderr": "addsubps.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for ADDSUBPS",
"id": "addsubps32err",
"format": "bin",
"source": "addsubps_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/addsubps/",
"target": [
{ "stderr": "addsubps.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/addsubps/addsubps.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/addsubps/addsubps_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/addsubps/addsubps.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/addsubps/addsubps_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/addsubps/addsubps_narrow.asm
View file

@ -1,2 +1,6 @@
addsubps xmm6, oword [0xd91]
addsubps xmm3, oword [0x8fe]
%ifdef ERROR
addsubps xmm8, xmm12
%endif

24
travis/insns/adox/adox.json
View file

@ -9,4 +9,28 @@
{ "output": "adox.bin64", "match": "adox.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for ADOX",
"id": "adox16err",
"format": "bin",
"source": "adox_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/adox/",
"target": [
{ "stderr": "adox.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for ADOX",
"id": "adox32err",
"format": "bin",
"source": "adox_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/adox/",
"target": [
{ "stderr": "adox.stderr32err" }
],
"error": "expected"
}
]

21
travis/insns/adox/adox.stderr16err Normal file
View file

@ -0,0 +1,21 @@
./travis/insns/adox/adox_narrow.asm:3: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:5: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:8: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:9: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:10: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:11: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:12: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:13: error: invalid operands in 16-bit mode
./travis/insns/adox/adox_narrow.asm:14: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:15: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:16: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:17: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:18: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:19: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:20: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:21: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:22: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:23: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:24: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:25: error: instruction not supported in 16-bit mode
./travis/insns/adox/adox_narrow.asm:26: error: instruction not supported in 16-bit mode

21
travis/insns/adox/adox.stderr32err Normal file
View file

@ -0,0 +1,21 @@
./travis/insns/adox/adox_narrow.asm:3: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:5: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:8: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:9: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:10: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:11: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:12: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:13: error: invalid operands in 32-bit mode
./travis/insns/adox/adox_narrow.asm:14: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:15: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:16: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:17: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:18: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:19: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:20: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:21: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:22: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:23: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:24: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:25: error: instruction not supported in 32-bit mode
./travis/insns/adox/adox_narrow.asm:26: error: instruction not supported in 32-bit mode

22
travis/insns/adox/adox_narrow.asm
View file

@ -3,3 +3,25 @@
adox eax, edx, dword [0x1df]
adox edx, dword [0x1df]
adox eax, ebx, dword [0xe7e]
%ifdef ERROR
adox rbx, qword [0x467]
adox rbp, rax
adox rdx, rcx, rax
adox rcx, rax
adox rbx, rdx, qword [0x1f1]
adox r10d, r8d
adox r15, r14
adox r14d, r11d, r10d
adox r8, r9, r10
adox r21d, r17d
adox r23, r21
adox r18d, r25d, r21d
adox r17, r22, r17
adox rcx, qword [eax+1]
adox rdx, qword [eax+64]
adox rsi, rax, qword [eax+1]
adox rdi, rsi, qword [eax+64]
adox rbp, [0x542]
adox rax, rax, [0x92d]
%endif

24
travis/insns/aesdec/aesdec.json
View file

@ -31,4 +31,28 @@
{ "output": "aesdec.bin64", "match": "aesdec.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for AESDEC",
"id": "aesdec16err",
"format": "bin",
"source": "aesdec_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesdec/",
"target": [
{ "stderr": "aesdec.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AESDEC",
"id": "aesdec32err",
"format": "bin",
"source": "aesdec_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesdec/",
"target": [
{ "stderr": "aesdec.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/aesdec/aesdec.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesdec/aesdec_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/aesdec/aesdec.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesdec/aesdec_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/aesdec/aesdec_narrow.asm
View file

@ -1,2 +1,6 @@
aesdec xmm0, oword [0x639]
aesdec xmm4, xmm5
%ifdef ERROR
aesdec xmm14, xmm8
%endif

24
travis/insns/aesdec128kl/aesdec128kl.json
View file

@ -31,4 +31,28 @@
{ "output": "aesdec128kl.bin64", "match": "aesdec128kl.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for AESDEC128KL",
"id": "aesdec128kl16err",
"format": "bin",
"source": "aesdec128kl_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesdec128kl/",
"target": [
{ "stderr": "aesdec128kl.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AESDEC128KL",
"id": "aesdec128kl32err",
"format": "bin",
"source": "aesdec128kl_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesdec128kl/",
"target": [
{ "stderr": "aesdec128kl.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/aesdec128kl/aesdec128kl.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesdec128kl/aesdec128kl_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/aesdec128kl/aesdec128kl.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesdec128kl/aesdec128kl_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/aesdec128kl/aesdec128kl_narrow.asm
View file

@ -1,2 +1,6 @@
aesdec128kl xmm5, [0x9f0]
aesdec128kl xmm3, [0x2fa]
%ifdef ERROR
aesdec128kl xmm8, [0xb21]
%endif

24
travis/insns/aesdec256kl/aesdec256kl.json
View file

@ -31,4 +31,28 @@
{ "output": "aesdec256kl.bin64", "match": "aesdec256kl.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for AESDEC256KL",
"id": "aesdec256kl16err",
"format": "bin",
"source": "aesdec256kl_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesdec256kl/",
"target": [
{ "stderr": "aesdec256kl.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AESDEC256KL",
"id": "aesdec256kl32err",
"format": "bin",
"source": "aesdec256kl_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesdec256kl/",
"target": [
{ "stderr": "aesdec256kl.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/aesdec256kl/aesdec256kl.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesdec256kl/aesdec256kl_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/aesdec256kl/aesdec256kl.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesdec256kl/aesdec256kl_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/aesdec256kl/aesdec256kl_narrow.asm
View file

@ -1,2 +1,6 @@
aesdec256kl xmm3, zword [0xef2]
aesdec256kl xmm4, zword [0xff0]
%ifdef ERROR
aesdec256kl xmm13, zword [0x67d]
%endif

24
travis/insns/aesdeclast/aesdeclast.json
View file

@ -31,4 +31,28 @@
{ "output": "aesdeclast.bin64", "match": "aesdeclast.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for AESDECLAST",
"id": "aesdeclast16err",
"format": "bin",
"source": "aesdeclast_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesdeclast/",
"target": [
{ "stderr": "aesdeclast.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AESDECLAST",
"id": "aesdeclast32err",
"format": "bin",
"source": "aesdeclast_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesdeclast/",
"target": [
{ "stderr": "aesdeclast.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/aesdeclast/aesdeclast.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesdeclast/aesdeclast_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/aesdeclast/aesdeclast.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesdeclast/aesdeclast_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/aesdeclast/aesdeclast_narrow.asm
View file

@ -1,2 +1,6 @@
aesdeclast xmm6, xmm7
aesdeclast xmm6, oword [0x5f8]
%ifdef ERROR
aesdeclast xmm13, xmm9
%endif

24
travis/insns/aesenc/aesenc.json
View file

@ -31,4 +31,28 @@
{ "output": "aesenc.bin64", "match": "aesenc.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for AESENC",
"id": "aesenc16err",
"format": "bin",
"source": "aesenc_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesenc/",
"target": [
{ "stderr": "aesenc.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AESENC",
"id": "aesenc32err",
"format": "bin",
"source": "aesenc_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesenc/",
"target": [
{ "stderr": "aesenc.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/aesenc/aesenc.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesenc/aesenc_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/aesenc/aesenc.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesenc/aesenc_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/aesenc/aesenc_narrow.asm
View file

@ -1,2 +1,6 @@
aesenc xmm7, xmm2
aesenc xmm3, xmm0
%ifdef ERROR
aesenc xmm9, xmm13
%endif

24
travis/insns/aesenc128kl/aesenc128kl.json
View file

@ -31,4 +31,28 @@
{ "output": "aesenc128kl.bin64", "match": "aesenc128kl.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for AESENC128KL",
"id": "aesenc128kl16err",
"format": "bin",
"source": "aesenc128kl_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesenc128kl/",
"target": [
{ "stderr": "aesenc128kl.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AESENC128KL",
"id": "aesenc128kl32err",
"format": "bin",
"source": "aesenc128kl_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesenc128kl/",
"target": [
{ "stderr": "aesenc128kl.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/aesenc128kl/aesenc128kl.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesenc128kl/aesenc128kl_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/aesenc128kl/aesenc128kl.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesenc128kl/aesenc128kl_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/aesenc128kl/aesenc128kl_narrow.asm
View file

@ -1,2 +1,6 @@
aesenc128kl xmm5, [0x843]
aesenc128kl xmm2, [0xc76]
%ifdef ERROR
aesenc128kl xmm9, [0xc45]
%endif

24
travis/insns/aesenc256kl/aesenc256kl.json
View file

@ -31,4 +31,28 @@
{ "output": "aesenc256kl.bin64", "match": "aesenc256kl.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for AESENC256KL",
"id": "aesenc256kl16err",
"format": "bin",
"source": "aesenc256kl_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesenc256kl/",
"target": [
{ "stderr": "aesenc256kl.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AESENC256KL",
"id": "aesenc256kl32err",
"format": "bin",
"source": "aesenc256kl_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesenc256kl/",
"target": [
{ "stderr": "aesenc256kl.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/aesenc256kl/aesenc256kl.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesenc256kl/aesenc256kl_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/aesenc256kl/aesenc256kl.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesenc256kl/aesenc256kl_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/aesenc256kl/aesenc256kl_narrow.asm
View file

@ -1,2 +1,6 @@
aesenc256kl xmm6, zword [0x6ff]
aesenc256kl xmm2, zword [0x11a]
%ifdef ERROR
aesenc256kl xmm15, zword [0xf6e]
%endif

24
travis/insns/aesenclast/aesenclast.json
View file

@ -31,4 +31,28 @@
{ "output": "aesenclast.bin64", "match": "aesenclast.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for AESENCLAST",
"id": "aesenclast16err",
"format": "bin",
"source": "aesenclast_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesenclast/",
"target": [
{ "stderr": "aesenclast.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AESENCLAST",
"id": "aesenclast32err",
"format": "bin",
"source": "aesenclast_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesenclast/",
"target": [
{ "stderr": "aesenclast.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/aesenclast/aesenclast.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesenclast/aesenclast_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/aesenclast/aesenclast.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesenclast/aesenclast_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/aesenclast/aesenclast_narrow.asm
View file

@ -1,2 +1,6 @@
aesenclast xmm6, oword [0x7b6]
aesenclast xmm4, oword [0x8f3]
%ifdef ERROR
aesenclast xmm10, xmm8
%endif

24
travis/insns/aesimc/aesimc.json
View file

@ -31,4 +31,28 @@
{ "output": "aesimc.bin64", "match": "aesimc.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for AESIMC",
"id": "aesimc16err",
"format": "bin",
"source": "aesimc_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesimc/",
"target": [
{ "stderr": "aesimc.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AESIMC",
"id": "aesimc32err",
"format": "bin",
"source": "aesimc_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aesimc/",
"target": [
{ "stderr": "aesimc.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/aesimc/aesimc.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesimc/aesimc_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/aesimc/aesimc.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aesimc/aesimc_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/aesimc/aesimc_narrow.asm
View file

@ -1,2 +1,6 @@
aesimc xmm6, oword [0x810]
aesimc xmm4, oword [0xa82]
%ifdef ERROR
aesimc xmm15, xmm12
%endif

24
travis/insns/aeskeygenassist/aeskeygenassist.json
View file

@ -31,4 +31,28 @@
{ "output": "aeskeygenassist.bin64", "match": "aeskeygenassist.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for AESKEYGENASSIST",
"id": "aeskeygenassist16err",
"format": "bin",
"source": "aeskeygenassist_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aeskeygenassist/",
"target": [
{ "stderr": "aeskeygenassist.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AESKEYGENASSIST",
"id": "aeskeygenassist32err",
"format": "bin",
"source": "aeskeygenassist_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/aeskeygenassist/",
"target": [
{ "stderr": "aeskeygenassist.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/aeskeygenassist/aeskeygenassist.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aeskeygenassist/aeskeygenassist_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/aeskeygenassist/aeskeygenassist.stderr32err Normal file
View file

@ -0,0 +1 @@
./travis/insns/aeskeygenassist/aeskeygenassist_narrow.asm:5: error: invalid operands in 32-bit mode

4
travis/insns/aeskeygenassist/aeskeygenassist_narrow.asm
View file

@ -1,2 +1,6 @@
aeskeygenassist xmm4, xmm0, 0x14
aeskeygenassist xmm5, xmm3, 0xfd
%ifdef ERROR
aeskeygenassist xmm14, xmm11, 0x2d
%endif

24
travis/insns/and/and.json
View file

@ -32,4 +32,28 @@
{ "stderr": "and.stderr64" }
]
}
,
{
"description": "Pseudorandom error-case test for AND",
"id": "and16err",
"format": "bin",
"source": "and_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/and/",
"target": [
{ "stderr": "and.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for AND",
"id": "and32err",
"format": "bin",
"source": "and_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/and/",
"target": [
{ "stderr": "and.stderr32err" }
],
"error": "expected"
}
]

32
travis/insns/and/and.stderr16err Normal file
View file

@ -0,0 +1,32 @@
./travis/insns/and/and_narrow.asm:9: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:10: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:11: error: invalid operands in 16-bit mode
./travis/insns/and/and_narrow.asm:12: error: invalid operands in 16-bit mode
./travis/insns/and/and_narrow.asm:13: error: invalid operands in 16-bit mode
./travis/insns/and/and_narrow.asm:14: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:15: error: invalid operands in 16-bit mode
./travis/insns/and/and_narrow.asm:16: error: invalid operands in 16-bit mode
./travis/insns/and/and_narrow.asm:17: error: invalid operands in 16-bit mode
./travis/insns/and/and_narrow.asm:18: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:19: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:20: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:21: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:22: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:23: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:24: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:25: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:26: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:27: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:28: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:29: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:30: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:31: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:32: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:33: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:34: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:35: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:36: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:39: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:40: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:41: error: instruction not supported in 16-bit mode
./travis/insns/and/and_narrow.asm:42: error: instruction not supported in 16-bit mode

32
travis/insns/and/and.stderr32err Normal file
View file

@ -0,0 +1,32 @@
./travis/insns/and/and_narrow.asm:9: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:10: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:11: error: invalid operands in 32-bit mode
./travis/insns/and/and_narrow.asm:12: error: invalid operands in 32-bit mode
./travis/insns/and/and_narrow.asm:13: error: invalid operands in 32-bit mode
./travis/insns/and/and_narrow.asm:14: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:15: error: invalid operands in 32-bit mode
./travis/insns/and/and_narrow.asm:16: error: invalid operands in 32-bit mode
./travis/insns/and/and_narrow.asm:17: error: invalid operands in 32-bit mode
./travis/insns/and/and_narrow.asm:18: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:19: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:20: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:21: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:22: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:23: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:24: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:25: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:26: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:27: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:28: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:29: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:30: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:31: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:32: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:33: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:34: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:35: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:36: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:39: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:40: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:41: error: instruction not supported in 32-bit mode
./travis/insns/and/and_narrow.asm:42: error: instruction not supported in 32-bit mode

37
travis/insns/and/and_narrow.asm
View file

@ -4,3 +4,40 @@
and bx, dx
and edx, esi
and edi, edx
%ifdef ERROR
and rax, rax
and rbx, rcx
and r15b, r10b
and r13w, r15w
and r14d, r9d
and r9, r13
and r23b, r18b
and r16w, r25w
and r18d, r19d
and r27, r16
and qword [eax+1], rcx
and qword [eax+64], rax
and rsi, qword [eax+1]
and rbx, qword [eax+64]
and qword [eax+1], 44
and qword [eax+64], -89
and qword [eax+1], -275284148
and qword [eax+64], 263899614
and rsi, rbx, qword [eax+1]
and rdi, rdx, qword [eax+64]
and rax, qword [eax+1], rbp
and rax, qword [eax+64], rbx
and rax, qword [eax+1], -60
and rax, qword [eax+64], -62
and rcx, qword [eax+1], -506441116
and rbp, qword [eax+64], 188036657
and [0x96b], rbx
and rsi, [0xc67]
and [0xc3a], 17
and [0x801], -308360386
and rsi, rcx, [0x705]
and rcx, [0x237], rbp
and rsi, [0x255], -7
and rcx, [0x22a], 468030773
%endif

24
travis/insns/andn/andn.json
View file

@ -31,4 +31,28 @@
{ "output": "andn.bin64", "match": "andn.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for ANDN",
"id": "andn16err",
"format": "bin",
"source": "andn_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/andn/",
"target": [
{ "stderr": "andn.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for ANDN",
"id": "andn32err",
"format": "bin",
"source": "andn_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/andn/",
"target": [
{ "stderr": "andn.stderr32err" }
],
"error": "expected"
}
]

10
travis/insns/andn/andn.stderr16err Normal file
View file

@ -0,0 +1,10 @@
./travis/insns/andn/andn_narrow.asm:12: error: instruction not supported in 16-bit mode
./travis/insns/andn/andn_narrow.asm:13: error: instruction not supported in 16-bit mode
./travis/insns/andn/andn_narrow.asm:14: error: instruction not supported in 16-bit mode
./travis/insns/andn/andn_narrow.asm:15: error: invalid operands in non-64-bit mode
./travis/insns/andn/andn_narrow.asm:16: error: instruction not supported in 16-bit mode
./travis/insns/andn/andn_narrow.asm:17: error: instruction not supported in 16-bit mode
./travis/insns/andn/andn_narrow.asm:18: error: instruction not supported in 16-bit mode
./travis/insns/andn/andn_narrow.asm:19: error: instruction not supported in 16-bit mode
./travis/insns/andn/andn_narrow.asm:20: error: instruction not supported in 16-bit mode
./travis/insns/andn/andn_narrow.asm:21: error: instruction not supported in 16-bit mode

10
travis/insns/andn/andn.stderr32err Normal file
View file

@ -0,0 +1,10 @@
./travis/insns/andn/andn_narrow.asm:12: error: instruction not supported in 32-bit mode
./travis/insns/andn/andn_narrow.asm:13: error: instruction not supported in 32-bit mode
./travis/insns/andn/andn_narrow.asm:14: error: instruction not supported in 32-bit mode
./travis/insns/andn/andn_narrow.asm:15: error: invalid operands in non-64-bit mode
./travis/insns/andn/andn_narrow.asm:16: error: instruction not supported in 32-bit mode
./travis/insns/andn/andn_narrow.asm:17: error: instruction not supported in 32-bit mode
./travis/insns/andn/andn_narrow.asm:18: error: instruction not supported in 32-bit mode
./travis/insns/andn/andn_narrow.asm:19: error: instruction not supported in 32-bit mode
./travis/insns/andn/andn_narrow.asm:20: error: instruction not supported in 32-bit mode
./travis/insns/andn/andn_narrow.asm:21: error: instruction not supported in 32-bit mode

13
travis/insns/andn/andn_narrow.asm
View file

@ -7,3 +7,16 @@
andn k5, k4, k1
andn k5, k1
andn k1, k1, k7
%ifdef ERROR
andn rcx, rbp, rcx
andn rcx, rcx
andn rbx, rbp, qword [0xc5c]
andn r10d, r15d, r13d
andn r14, r10, r15
andn r19d, r18d, r28d
andn r16, r21, r29
andn rbp, rdx, qword [eax+1]
andn rax, rcx, qword [eax+64]
andn rdx, rcx, [0x49c]
%endif

24
travis/insns/andnpd/andnpd.json
View file

@ -31,4 +31,28 @@
{ "output": "andnpd.bin64", "match": "andnpd.bin64.t" }
]
}
,
{
"description": "Pseudorandom error-case test for ANDNPD",
"id": "andnpd16err",
"format": "bin",
"source": "andnpd_narrow.asm",
"option": "--bits 16 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/andnpd/",
"target": [
{ "stderr": "andnpd.stderr16err" }
],
"error": "expected"
}
,
{
"description": "Pseudorandom error-case test for ANDNPD",
"id": "andnpd32err",
"format": "bin",
"source": "andnpd_narrow.asm",
"option": "--bits 32 -DERROR -w-ea-absolute -w-implicit-abs-deprecated -I./travis/insns/andnpd/",
"target": [
{ "stderr": "andnpd.stderr32err" }
],
"error": "expected"
}
]

1
travis/insns/andnpd/andnpd.stderr16err Normal file
View file

@ -0,0 +1 @@
./travis/insns/andnpd/andnpd_narrow.asm:5: error: invalid operands in 16-bit mode

1
travis/insns/andnpd/andnpd.stderr32err Normal file
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@ -0,0 +1 @@
./travis/insns/andnpd/andnpd_narrow.asm:5: error: invalid operands in 32-bit mode

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