mirror of
https://github.com/netwide-assembler/nasm
synced 2026-08-26 16:23:04 -04:00
7f69cf689c
This is a mostly automated, partially AI-assisted migration of tests from the test/ directory into the travis framework. Running tests manually in the test/ directory is still supported, but move common include files into travis/test and add a default -I option to Makefile.in in the test/ directory. The incbin test fails for pre-existing reasons; for now it contains an stderr file with the errors. The problem is that INCBIN is both a macro and a special instruction (not even a directive...), but there currently is no way to handle prefixes, *especially* TIMES, in multi-line macros. This is a separate problem and needs to be dealt with as such. Reorganize the travis directory so that each test or collection of tests are in a separate subdirectory of travis/, and travis itself lives in tools/travis to avoid creating deeper paths. Add support for recording compression options in the travis .json files, so that compressed files can be recreated with the same options: because of the generally repetitive nature of the binary output test files, the parameters used for xz compression can matter enormously. These are combined into a single huge commit to avoid adding large binary files into the repository that then would immediately be obsoleted, but still retained in git. Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
45 lines
1,001 B
NASM
45 lines
1,001 B
NASM
bits 64
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blendvpd xmm2,xmm1,xmm0
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vblendvpd xmm2,xmm1,xmm0,xmm0
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vblendvpd xmm2,xmm1,xmm0
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vblendvpd ymm2,ymm1,ymm0,ymm0
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vblendvpd ymm2,ymm1,ymm0
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vcvtsi2sd xmm9,xmm10,ecx
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vcvtsi2sd xmm9,xmm10,rcx
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vcvtsi2sd xmm9,xmm10,dword [rdi]
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vcvtsi2sd xmm9,xmm10,qword [rdi]
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vpextrb [rax],xmm1,0x33
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vpextrw [rax],xmm1,0x33
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vpextrd [rax],xmm1,0x33
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vpextrq [rax],xmm1,0x33
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vpextrb rax,xmm1,0x33
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vpextrw rax,xmm1,0x33
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vpextrd rax,xmm1,0x33
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vpextrq rax,xmm1,0x33
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vpextrb eax,xmm1,0x33
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vpextrw eax,xmm1,0x33
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vpextrd eax,xmm1,0x33
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; vpextrq eax,xmm1,0x33
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pextrw rax,xmm0,0x33
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vcvtpd2ps xmm0,xmm1
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vcvtpd2ps xmm0,oword [rsi]
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vcvtpd2ps xmm0,ymm1
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vcvtpd2ps xmm0,yword [rsi]
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; vcvtpd2ps xmm0,[rsi]
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vcvtpd2dq xmm0,xmm1
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vcvtpd2dq xmm0,oword [rsi]
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vcvtpd2dq xmm0,ymm1
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vcvtpd2dq xmm0,yword [rsi]
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; vcvtpd2dq xmm0,[rsi]
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vcvttpd2dq xmm0,xmm1
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vcvttpd2dq xmm0,oword [rsi]
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vcvttpd2dq xmm0,ymm1
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vcvttpd2dq xmm0,yword [rsi]
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; vcvttpd2dq xmm0,[rsi]
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