mirror of
https://github.com/netwide-assembler/nasm
synced 2026-08-26 16:23:04 -04:00
941aa2ba16
Extend gen-insn-tests.pl to synthesize, for every distinct template across a mnemonic's entire template set that has a modrm-memory- capable operand (mem*, rm*, xmmrm*/ymmrm256/zmmrm512, mmxrm*), two additional candidate lines using [eax+1] and [eax+64] addressing in place of that operand's usual bare-displacement or register form. Whether an instruction has a disp8-encodable form (or, for EVEX, what its compressed-displacement scale factor is) is instruction-specific, so rather than computing the exact boundary per instruction these two fixed offsets are used as a baseline: +1 is unambiguously disp8- encodable everywhere, and +64 lands past the disp8 boundary for byte-granular encodings while still being a clean multiple of the larger EVEX compressed-displacement scales. [eax+N] (rather than a bare displacement, or a bit-width-specific base register) is used because it's valid addressing syntax at every --bits width via the 0x67 address-size prefix, confirmed empirically. Candidates are routed through the same staged, cumulative probe as the hireg/apxreg/EVEX-decorator buckets, so one bad candidate (e.g. an instruction with memory-operand restrictions this generator doesn't model) can't cost a mnemonic its pre-existing coverage. Regenerated travis/insns/ (2606 mnemonics, 16 dropped, unchanged from before; 1987 mnemonics gained at least one disp-boundary line). Validated: nasm-t.py run against a scratch regeneration is 6955/6955 PASS/0 FAIL with per-mnemonic bit-width success counts identical to the previous committed baseline, and make -j32 travis passes in ~26s. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> |
||
|---|---|---|
| .. | ||
| prefetch.asm | ||
| prefetch.bin16.t | ||
| prefetch.bin32.t | ||
| prefetch.bin64.t | ||
| prefetch.json | ||
| prefetch_narrow.asm | ||