nasm/travis/insns/prefetchwt1
H. Peter Anvin (Intel) 5422294119 testgen: add implicitly-sized memory operand coverage
For instruction operand tokens that carry an explicit size in their own
name (mem8/16/32/64/..., rm8/16/32/64, xmmrm.../ymmrm256/zmmrm512,
mmxrm/mmxrm64), the generator previously always emitted an explicit size
keyword (e.g. "dword", "oword") for the memory operand. This never
exercised NASM's SM-flag-driven implicit-size-inference path, where the
size of an ambiguous memory operand is inferred from a paired
already-sized operand (typically a same-width register) in the same
instruction template (e.g. ADD reg32,rm32 or MOVBE reg32,mem32 don't
need an explicit size keyword).

Add build_implicitsize_line(), which replaces the first memory-capable
operand whose base token has a nonzero %mem_sizebits entry with a bare
(size-keyword-free) memory operand, leaving all other operands as
normally generated. As with the other coverage buckets (hireg, apxreg,
mask/maskz/broadcast/saeer, disp8/32 boundary), the candidate line is
routed through the shared cumulative staged probe and only kept if it
actually assembles for that instruction -- this avoids needing to parse
and replicate NASM's own SM/AR flag-driven operand-size-disambiguation
logic.

Note: for tokens with no size in their own name (plain "mem"), the
existing mem_operand($rng, 0) generator path already omits the size
keyword unconditionally, so that half of implicit-size coverage was
already exercised prior to this change; only explicitly-sized tokens
needed the new candidate.

Verified via full scratch regeneration (2606 mnemonics / 16 dropped,
unchanged) + nasm-t.py run (6955/6955 PASS, 0 FAIL) + per-mnemonic
.json entry-count diff against the prior committed tree (zero
differences, confirming no bit-width regressions). 1922/2606
mnemonics gained new implicit-size coverage lines. Regenerated
travis/insns/ and validated via 'make -j32 travis' (all PASS, ~26s).

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
2026-07-04 12:38:36 -07:00
..
prefetchwt1.asm testgen: add implicitly-sized memory operand coverage 2026-07-04 12:38:36 -07:00
prefetchwt1.bin16.t tools/testgen: pseudorandom instruction test generator 2026-07-01 23:42:14 -07:00
prefetchwt1.bin32.t tools/testgen: pseudorandom instruction test generator 2026-07-01 23:42:14 -07:00
prefetchwt1.bin64.t testgen: add implicitly-sized memory operand coverage 2026-07-04 12:38:36 -07:00
prefetchwt1.json testgen: add modrm-memory disp8/disp32 boundary coverage 2026-07-04 12:21:31 -07:00
prefetchwt1_narrow.asm testgen: add modrm-memory disp8/disp32 boundary coverage 2026-07-04 12:21:31 -07:00