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https://github.com/netwide-assembler/nasm
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MOVDDUP tuple type uses a compression shift for the disp8 addressing scheme. The shift depends on the vector lenght and is defined as 8 for 128 bits, 32 for 256 bits and 64 for 512 bits. Current implementation doesn't work for the 128 bit vector case since the expression used evaluates to 16 instead of 8. Fix it with a special if check before the current expression is returned. Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
89 lines
1.8 KiB
C
89 lines
1.8 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/* Copyright 1996-2024 The NASM Authors - All Rights Reserved */
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/*
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* disp8.h header file for disp8.c
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*/
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#ifndef NASM_DISP8_H
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#define NASM_DISP8_H
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#include "nasm.h"
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/*
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* Find shift value for compressed displacement (disp8 << shift)
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*/
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static inline unsigned int get_disp8_shift(const insn *ins)
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{
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bool evex_b;
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unsigned int evex_w;
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unsigned int vectlen;
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enum ttypes tuple = ins->evex_tuple;
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if (likely(!tuple))
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return 0;
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evex_b = !!(ins->evex & EVEX_B);
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evex_w = !!(ins->evex & EVEX_W);
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/* XXX: consider RC/SAE here?! */
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vectlen = getfield(EVEX_LL, ins->evex);
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switch (tuple) {
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/* Full, half vector unless broadcast */
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case FV:
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return evex_b ? 2 + evex_w : vectlen + 4;
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case HV:
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return evex_b ? 2 + evex_w : vectlen + 3;
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/* Full vector length */
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case FVM:
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return vectlen + 4;
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/* Fixed tuple lengths */
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case T1S8:
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return 0;
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case T1S16:
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return 1;
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case T1F32:
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return 2;
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case T1F64:
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return 3;
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case M128:
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return 4;
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/* One scalar */
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case T1S:
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return 2 + evex_w;
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/* 2, 4, 8 32/64-bit elements */
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case T2:
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return 3 + evex_w;
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case T4:
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return 4 + evex_w;
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case T8:
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return 5 + evex_w;
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/* Half, quarter, eigth mem */
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case HVM:
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return vectlen + 3;
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case QVM:
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return vectlen + 2;
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case OVM:
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return vectlen + 1;
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/* MOVDDUP */
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case DUP:
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/*
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* 128-bit vector case doesn't follow the same formula as 256- and
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* 512-bit vectors.
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*/
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if (!vectlen)
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return 3;
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return vectlen + 4;
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default:
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return 0;
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}
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}
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#endif /* NASM_DISP8_H */
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