mirror of
https://github.com/netwide-assembler/nasm
synced 2026-08-26 16:23:04 -04:00
096c82e141
This also underscores the missing "to" forms of some instructions, but that is not a regression of any kind; in fact seems to have been there since the very beginning. It is probably so that we should use the 2-operand forms as the preferred disassembly forms, but that's a totally different task. Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
141 lines
3.4 KiB
NASM
141 lines
3.4 KiB
NASM
;Testname=test; Arguments=-fbin -ofpu.bin; Files=stdout stderr fpu.bin
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; relaxed encodings for FPU instructions, which NASM should support
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; -----------------------------------------------------------------
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%define void
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%define reg_fpu0 st0
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%define reg_fpu st1
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%macro src 2
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%1 %2
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%1 reg_fpu0,%2
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%endmacro
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%macro dst 2
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%1 to %2
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%1 %2,reg_fpu0
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%endmacro
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%macro dsp 2
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%1 %2
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%1 %2,reg_fpu0
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%1
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%endmacro
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; no operands instead of one operand:
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; F(U)COM(P), FCOM2, FCOMP3, FCOMP5
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FCOM void
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FCOMP void
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FUCOM void
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FUCOMP void
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; FCOM2 void
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; FCOMP3 void
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; FCOMP5 void
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; FLD, FST, FSTP, FSTP1, FSTP8, FSTP9
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FLD void
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FST void
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FSTP void
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; FSTP1 void
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; FSTP8 void
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; FSTP9 void
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; FXCH, FXCH4, FXCH7, FFREE, FFREEP
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FXCH void
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; FXCH4 void
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; FXCH7 void
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FFREE void
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FFREEP void
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; no operands instead of two operands:
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; FADD(P), FMUL(P), FSUBR(P), FSUB(P), FDIVR(P), FDIV(P)
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FADD void
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FADDP void
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FMUL void
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FMULP void
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FSUBR void
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FSUBRP void
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FSUB void
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FSUBP void
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FDIVR void
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FDIVRP void
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FDIV void
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FDIVP void
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; one operand instead of two operands:
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; FADD, FMUL, FSUB, FSUBR, FDIV, FDIVR
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src FADD , reg_fpu
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src FMUL , reg_fpu
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src FSUB , reg_fpu
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src FSUBR , reg_fpu
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src FDIV , reg_fpu
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src FDIVR , reg_fpu
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; FADD, FMUL, FSUBR, FSUB, FDIVR, FDIV (with TO qualifier)
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dst FADD , reg_fpu
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dst FMUL , reg_fpu
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dst FSUBR , reg_fpu
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dst FSUB , reg_fpu
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dst FDIVR , reg_fpu
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dst FDIV , reg_fpu
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; FADDP, FMULP, FSUBRP, FSUBP, FDIVRP, FDIVP
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dsp FADDP , reg_fpu
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dsp FMULP , reg_fpu
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dsp FSUBRP , reg_fpu
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dsp FSUBP , reg_fpu
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dsp FDIVRP , reg_fpu
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dsp FDIVP , reg_fpu
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; FCMOV(N)B, FCMOV(N)E, FCMOV(N)BE, FCMOV(N)U, and F(U)COMI(P)
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src FCMOVB , reg_fpu
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src FCMOVNB , reg_fpu
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src FCMOVE , reg_fpu
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src FCMOVNE , reg_fpu
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src FCMOVBE , reg_fpu
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src FCMOVNBE , reg_fpu
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src FCMOVU , reg_fpu
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src FCMOVNU , reg_fpu
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src FCOMI , reg_fpu
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src FCOMIP , reg_fpu
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src FUCOMI , reg_fpu
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src FUCOMIP , reg_fpu
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; two operands instead of one operand:
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; these don't really exist, and thus are _NOT_ supported:
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; FCOM reg_fpu,reg_fpu0
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; FCOM reg_fpu0,reg_fpu
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; FUCOM reg_fpu,reg_fpu0
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; FUCOM reg_fpu0,reg_fpu
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; FCOMP reg_fpu,reg_fpu0
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; FCOMP reg_fpu0,reg_fpu
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; FUCOMP reg_fpu,reg_fpu0
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; FUCOMP reg_fpu0,reg_fpu
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; FCOM2 reg_fpu,reg_fpu0
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; FCOM2 reg_fpu0,reg_fpu
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; FCOMP3 reg_fpu,reg_fpu0
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; FCOMP3 reg_fpu0,reg_fpu
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; FCOMP5 reg_fpu,reg_fpu0
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; FCOMP5 reg_fpu0,reg_fpu
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; FXCH reg_fpu,reg_fpu0
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; FXCH reg_fpu0,reg_fpu
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; FXCH4 reg_fpu,reg_fpu0
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; FXCH4 reg_fpu0,reg_fpu
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; FXCH7 reg_fpu,reg_fpu0
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; FXCH7 reg_fpu0,reg_fpu
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; EOF
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