nasm/x86
H. Peter Anvin 48f7170772 insns.pl: sanity-check that instruction encodings match operands
Error out if an encoding position is invalid, like an "r" operand
matches an "xmmrm" operand.

Document the instruction encoding symbols; there are too many of them
by now.

Add symbols 'n' and 'w' meaning immediates that are supposed to be
encoded as if they were 'm' memory addresses and 'v' register numbers,
respectively; this is necessary to indicate a validation exception.

Remove broken ARPL "memory-like" encoding. It probably never worked
anyway.

This verification caught two bugs already:

- VPMASKMOV[DQ] cannot omit the second operand.

- Incorrect operand encoding order for VREDUCESH.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
2025-09-30 12:06:11 -07:00
..
bytecode.txt insns.pl: sanity-check that instruction encodings match operands 2025-09-30 12:06:11 -07:00
iflags.ph add AMX instruction TDPFP16PS 2025-09-24 19:52:27 +08:00
insns-iflags.ph insns: add PROT flag if either EVEX or LONG is set 2024-08-23 13:15:46 -07:00
insns.dat insns.pl: sanity-check that instruction encodings match operands 2025-09-30 12:06:11 -07:00
insns.pl insns.pl: sanity-check that instruction encodings match operands 2025-09-30 12:06:11 -07:00
preinsns.pl Fixes for JMP|CALL near, RETF, and segment instructions 2025-09-19 18:55:54 -07:00
regs.dat ndisasm: make the assembler (hopefully) work again 2025-08-30 16:16:43 -07:00
regs.pl ndisasm: make the assembler (hopefully) work again 2025-08-30 16:16:43 -07:00
rex2.pl x86: add Perl script for rex2 compatibility testing (not yet used) 2025-03-04 08:43:09 -08:00
x86const.h apx: modify the tokenizer to be able to handle {dfv=...} 2024-07-27 17:57:08 -07:00