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hw/arm: Add Axiado SoC AX3000

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This patch adds new model for Axiado SoC AX3000 which supports
    4 Cortex-A53 ARM64 CPUs
    Arm Generic Interrupt Controller v3
    4 Cadence UARTs

Signed-off-by: Kuan-Jui Chiu <kchiu@axiado.com>
Message-id: 20260713073033.3883619-2-kchiu@axiado.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: Kconfig for the SoC shouldn't depend on ARM]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Kuan-Jui Chiu 2026-08-11 20:14:11 +01:00 • committed by Peter Maydell
parent 8ae365bdc8
commit 33a71a68c6
5 changed files with 266 additions and 0 deletions
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7
MAINTAINERS
View file

@ -1300,6 +1300,13 @@ M: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
S: Maintained
F: rust/hw/char/pl011/
Axiado SoCs and EVKs
M: Kuan-Jui Chiu <kchiu@axiado.com>
L: qemu-arm@nongnu.org
S: Maintained
F: hw/arm/ax3000*.c
F: include/hw/arm/ax3000*.h
AVR Machines
-------------

6
hw/arm/Kconfig
View file

@ -725,3 +725,9 @@ config ARMSSE
select UNIMP
select SSE_COUNTER
select SSE_TIMER
config AXIADO_SOC
bool
select ARM_GIC
select CADENCE # UART
select UNIMP

182
hw/arm/ax3000-soc.c Normal file
View file

@ -0,0 +1,182 @@
/*
* Axiado SoC AX3000
*
* Author: Kuan-Jui Chiu <kchiu@axiado.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "system/address-spaces.h"
#include "hw/arm/bsa.h"
#include "hw/arm/ax3000-soc.h"
#include "hw/misc/unimp.h"
#include "system/system.h"
#include "qobject/qlist.h"
#include "qom/object.h"
#include "hw/core/boards.h"
static void ax3000_init(Object *obj)
{
Ax3000SoCState *s = AX3000_SOC(obj);
Ax3000SoCClass *sc = AX3000_SOC_GET_CLASS(s);
for (int i = 0; i < sc->num_cpus; i++) {
g_autofree char *name = g_strdup_printf("cpu%d", i);
object_initialize_child(obj, name, &s->cpu[i],
ARM_CPU_TYPE_NAME("cortex-a53"));
}
object_initialize_child(obj, "gic", &s->gic, gicv3_class_name());
for (int i = 0; i < AX3000_NUM_UARTS; i++) {
g_autofree char *name = g_strdup_printf("uart%d", i);
object_initialize_child(obj, name, &s->uart[i], TYPE_CADENCE_UART);
}
}
static void ax3000_realize(DeviceState *dev, Error **errp)
{
Ax3000SoCState *s = AX3000_SOC(dev);
Ax3000SoCClass *sc = AX3000_SOC_GET_CLASS(s);
SysBusDevice *gic_sbd = SYS_BUS_DEVICE(&s->gic);
DeviceState *gic_dev = DEVICE(&s->gic);
QList *redist_region_count;
SysBusDevice *sdhci0_sbd;
DeviceState *card;
/* CPUs */
for (int i = 0; i < sc->num_cpus; i++) {
object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 8000000,
&error_abort);
if (object_property_find(OBJECT(&s->cpu[i]), "has_el3")) {
object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3",
false, &error_abort);
}
if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
return;
}
}
/* GIC */
qdev_prop_set_uint32(gic_dev, "num-cpu", sc->num_cpus);
qdev_prop_set_uint32(gic_dev, "num-irq",
AX3000_NUM_IRQS + GIC_INTERNAL);
redist_region_count = qlist_new();
qlist_append_int(redist_region_count, sc->num_cpus);
qdev_prop_set_array(gic_dev, "redist-region-count", redist_region_count);
if (!sysbus_realize(gic_sbd, errp)) {
return;
}
sysbus_mmio_map(gic_sbd, 0, AX3000_GIC_DIST_BASE);
sysbus_mmio_map(gic_sbd, 1, AX3000_GIC_REDIST_BASE);
/*
* Mapping from the output timer irq lines from the CPU to the
* GIC PPI inputs.
*/
const int timer_irqs[] = {
[GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ
};
/*
* Wire the outputs from each CPU's generic timer and the GICv3
* maintenance interrupt signal to the appropriate GIC PPI inputs, and
* the GIC's IRQ/FIQ interrupt outputs to the CPU's inputs.
*/
for (int i = 0; i < sc->num_cpus; i++) {
DeviceState *cpu_dev = DEVICE(&s->cpu[i]);
int intidbase = AX3000_NUM_IRQS + i * GIC_INTERNAL;
qemu_irq irq;
for (int j = 0; j < ARRAY_SIZE(timer_irqs); j++) {
irq = qdev_get_gpio_in(gic_dev, intidbase + timer_irqs[j]);
qdev_connect_gpio_out(cpu_dev, j, irq);
}
irq = qdev_get_gpio_in(gic_dev, intidbase + ARCH_GIC_MAINT_IRQ);
qdev_connect_gpio_out_named(cpu_dev, "gicv3-maintenance-interrupt",
0, irq);
sysbus_connect_irq(gic_sbd, i,
qdev_get_gpio_in(cpu_dev, ARM_CPU_IRQ));
sysbus_connect_irq(gic_sbd, i + sc->num_cpus,
qdev_get_gpio_in(cpu_dev, ARM_CPU_FIQ));
sysbus_connect_irq(gic_sbd, i + 2 * sc->num_cpus,
qdev_get_gpio_in(cpu_dev, ARM_CPU_VIRQ));
sysbus_connect_irq(gic_sbd, i + 3 * sc->num_cpus,
qdev_get_gpio_in(cpu_dev, ARM_CPU_VFIQ));
}
/* DRAM */
const struct {
hwaddr addr;
size_t size;
const char *name;
} dram_table[] = {
{ AX3000_DRAM0_BASE, AX3000_DRAM0_SIZE, "dram0" },
{ AX3000_DRAM1_BASE, AX3000_DRAM1_SIZE, "dram1" }
};
for (int i = 0; i < AX3000_NUM_BANKS; i++) {
memory_region_init_ram(&s->dram[i], OBJECT(s), dram_table[i].name,
dram_table[i].size, &error_fatal);
memory_region_add_subregion(get_system_memory(), dram_table[i].addr,
&s->dram[i]);
}
/* UARTs */
const struct {
hwaddr addr;
unsigned int irq;
} serial_table[] = {
{ AX3000_UART0_BASE, AX3000_UART0_IRQ },
{ AX3000_UART1_BASE, AX3000_UART1_IRQ },
{ AX3000_UART2_BASE, AX3000_UART2_IRQ },
{ AX3000_UART3_BASE, AX3000_UART3_IRQ }
};
for (int i = 0; i < AX3000_NUM_UARTS; i++) {
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
qdev_get_gpio_in(gic_dev, serial_table[i].irq));
}
/* Timer control */
create_unimplemented_device("ax3000.timerctrl", AX3000_TIMER_CTRL, 32);
}
static void ax3000_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
Ax3000SoCClass *sc = AX3000_SOC_CLASS(oc);
dc->desc = "Axiado SoC AX3000";
dc->realize = ax3000_realize;
sc->num_cpus = AX3000_NUM_CPUS;
}
static const TypeInfo axiado_soc_types[] = {
{
.name = TYPE_AX3000_SOC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ax3000SoCState),
.instance_init = ax3000_init,
.class_init = ax3000_class_init,
}
};
DEFINE_TYPES(axiado_soc_types)

3
hw/arm/meson.build
View file

@ -110,6 +110,9 @@ arm_common_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
arm_common_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
arm_common_ss.add(when: ['CONFIG_AXIADO_SOC', 'TARGET_AARCH64'], if_true: files(
'ax3000-soc.c'))
arm_common_ss.add(files('boot.c'))
hw_common_arch += {'arm': arm_common_ss}

68
include/hw/arm/ax3000-soc.h Normal file
View file

@ -0,0 +1,68 @@
/*
* Axiado SoC AX3000
*
* Author: Kuan-Jui Chiu <kchiu@axiado.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef AXIADO_AX3000_H
#define AXIADO_AX3000_H
#include "cpu.h"
#include "hw/intc/arm_gicv3_common.h"
#include "hw/char/cadence_uart.h"
#include "hw/core/sysbus.h"
#include "qemu/units.h"
#define TYPE_AX3000_SOC "ax3000"
OBJECT_DECLARE_TYPE(Ax3000SoCState, Ax3000SoCClass, AX3000_SOC)
#define AX3000_DRAM0_BASE 0x3C000000
#define AX3000_DRAM0_SIZE (1088 * MiB)
#define AX3000_DRAM1_BASE 0x400000000
#define AX3000_DRAM1_SIZE (2 * GiB)
#define AX3000_GIC_DIST_BASE 0x80300000
#define AX3000_GIC_DIST_SIZE (64 * KiB)
#define AX3000_GIC_REDIST_BASE 0x80380000
#define AX3000_GIC_REDIST_SIZE (512 * KiB)
#define AX3000_UART0_BASE 0x80520000
#define AX3000_UART1_BASE 0x805a0000
#define AX3000_UART2_BASE 0x80620000
#define AX3000_UART3_BASE 0x80520800
#define AX3000_TIMER_CTRL 0x8A020000
#define AX3000_PLL_BASE 0x80000000
enum Ax3000Configuration {
AX3000_NUM_CPUS = 4,
AX3000_NUM_IRQS = 224,
AX3000_NUM_BANKS = 2,
AX3000_NUM_UARTS = 4,
};
typedef struct Ax3000SoCState {
SysBusDevice parent;
ARMCPU cpu[AX3000_NUM_CPUS];
GICv3State gic;
MemoryRegion dram[AX3000_NUM_BANKS];
CadenceUARTState uart[AX3000_NUM_UARTS];
} Ax3000SoCState;
typedef struct Ax3000SoCClass {
SysBusDeviceClass parent;
uint32_t num_cpus;
} Ax3000SoCClass;
enum Ax3000Irqs {
AX3000_UART0_IRQ = 112,
AX3000_UART1_IRQ = 113,
AX3000_UART2_IRQ = 114,
AX3000_UART3_IRQ = 170,
};
#endif /* AXIADO_AX3000_H */