uefi-ref/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu.git synced 2026-08-26 22:23:12 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv/cpu: add CPU unrealize callback

Browse source 
Next patch is going to dynamically allocate debug trigger arrays during
realize() time.  We need a way of freeing them during unrealize(), which
doesn't exist at this moment.

There's a lot going on in that patch already so we're adding the
callback infrastructure beforehand.

Suggested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260617131710.1855353-2-daniel.barboza@oss.qualcomm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2026-06-17 10:17:08 -03:00 • committed by Alistair Francis
parent deda107b1c
commit 820552a92e
2 changed files with 11 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

9
target/riscv/cpu.c
View file

@ -1009,6 +1009,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
mcc->parent_realize(dev, errp);
}
static void riscv_cpu_unrealize(DeviceState *dev)
{
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
mcc->parent_unrealize(dev);
}
bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu)
{
if (tcg_enabled()) {
@ -2664,6 +2671,8 @@ static void riscv_cpu_common_class_init(ObjectClass *c, const void *data)
device_class_set_parent_realize(dc, riscv_cpu_realize,
&mcc->parent_realize);
device_class_set_parent_unrealize(dc, riscv_cpu_unrealize,
&mcc->parent_unrealize);
resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
&mcc->parent_phases);

2
target/riscv/cpu.h
View file

@ -576,6 +576,7 @@ typedef struct RISCVCPUDef {
/**
* RISCVCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_unrealize: The parent class' unrealize handler.
* @parent_phases: The parent class' reset phase handlers.
*
* A RISCV CPU model.
@ -584,6 +585,7 @@ struct RISCVCPUClass {
CPUClass parent_class;
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
ResettablePhases parent_phases;
RISCVCPUDef *def;
};