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target/arm: load on canonical tag loads ext bits

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Loading tags from canonically tagged regions should use the canonical
tags (extension bits), not allocation tags. See AArch64_MemTagRead().

Signed-off-by: Gabriel Brookman <brookmangabriel@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260529-feat-mte4-v7-9-ccbd3c14eb3c@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Gabriel Brookman 2026-05-29 12:52:49 -07:00 • committed by Peter Maydell
parent 5bd4fa5c6c
commit 8912ceced8
3 changed files with 16 additions and 6 deletions
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4
target/arm/tcg/helper-a64-defs.h
View file

@ -102,14 +102,14 @@ DEF_HELPER_FLAGS_3(mte_check, TCG_CALL_NO_WG, i64, env, i32, i64)
DEF_HELPER_FLAGS_3(mte_check_zva, TCG_CALL_NO_WG, i64, env, i32, i64)
DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32)
DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64)
DEF_HELPER_FLAGS_4(ldg, TCG_CALL_NO_WG, i64, env, i64, i64, i32)
DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64)
DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64)
DEF_HELPER_FLAGS_2(stg_stub, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64)
DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64)
DEF_HELPER_FLAGS_2(st2g_stub, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_3(ldgm, TCG_CALL_NO_WG, i64, env, i64, i32)
DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64)
DEF_HELPER_FLAGS_3(stzgm_tags, TCG_CALL_NO_WG, void, env, i64, i64)

14
target/arm/tcg/mte_helper.c
View file

@ -304,7 +304,7 @@ int load_tag1(uint64_t ptr, uint8_t *mem)
return extract32(*mem, ofs, 4);
}
uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt)
uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt, uint32_t mtx)
{
int mmu_idx = arm_env_mmu_index(env);
uint8_t *mem;
@ -317,6 +317,9 @@ uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt)
/* Load if page supports tags. */
if (mem) {
rtag = load_tag1(ptr, mem);
} else if (mtx) {
uint64_t bit55 = extract64(ptr, 55, 1);
rtag = 0xF * bit55;
}
return address_with_allocation_tag(xt, rtag);
@ -458,7 +461,7 @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
}
}
uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr, uint32_t mtx)
{
int mmu_idx = arm_env_mmu_index(env);
uintptr_t ra = GETPC();
@ -476,6 +479,13 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
/* The tag is squashed to zero if the page does not support tags. */
if (!tag_mem) {
/* Load canonical value if mtx is set (untagged memory region) */
if (mtx) {
bool bit55 = extract64(ptr, 55, 1);
ret = extract64(-bit55, 0, 1 << gm_bs);
shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
return ret << shift;
}
return 0;
}

4
target/arm/tcg/translate-a64.c
View file

@ -4801,7 +4801,7 @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
tcg_rt = cpu_reg(s, a->rt);
if (s->ata[0]) {
gen_helper_ldgm(tcg_rt, tcg_env, addr);
gen_helper_ldgm(tcg_rt, tcg_env, addr, tcg_constant_i32(s->mtx));
} else {
MMUAccessType acc = MMU_DATA_LOAD;
int size = 4 << s->gm_blocksize;
@ -4836,7 +4836,7 @@ static bool trans_LDG(DisasContext *s, arg_ldst_tag *a)
tcg_gen_andi_i64(addr, addr, -TAG_GRANULE);
tcg_rt = cpu_reg(s, a->rt);
if (s->ata[0]) {
gen_helper_ldg(tcg_rt, tcg_env, addr, tcg_rt);
gen_helper_ldg(tcg_rt, tcg_env, addr, tcg_rt, tcg_constant_i32(s->mtx));
} else {
/*
* Tag access disabled: we must check for aborts on the load