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tests/qtest: Add K230 DDR controller tests
Add qtests for DDRC and PHY reset values, register access policy, the software-update handshake, and PHY register ownership. Exercise PHY training and mailbox acknowledgement through the DFI initialization sequence. Include negative coverage to ensure DFI cannot complete before PHY training or enter Normal mode before completion is enabled. Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Suggested-by: Chao Liu <chao.liu@processmission.com> Signed-off-by: Junze Cao <caojunze424@gmail.com> Message-ID: <20260807-k230-ddr-v2-v2-3-c531308ae819@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Junze Cao
Alistair Francis
parent
4309ee8e91
commit
98911b604b
3 changed files with 229 additions and 1 deletions
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@ -1851,6 +1851,7 @@ F: include/hw/misc/k230_ddr.h
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F: include/hw/riscv/k230.h
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F: include/hw/watchdog/k230_wdt.h
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F: tests/functional/riscv64/test_k230.py
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F: tests/qtest/k230-ddr-test.c
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F: tests/qtest/k230-wdt-test.c
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RX Machines
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226
tests/qtest/k230-ddr-test.c
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226
tests/qtest/k230-ddr-test.c
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@ -0,0 +1,226 @@
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/*
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* QTest testcase for the K230 DDR controller and PHY
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*
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* Exercises register access, reset, PHY ownership, training mailbox, and DFI
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* initialization.
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*
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* Copyright (c) 2026 Junze Cao <caojunze424@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#define K230_DDRC_BASE UINT64_C(0x98000000)
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#define K230_DDR_PHY_BASE UINT64_C(0x9a000000)
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#define K230_DDRC_MSTR 0x000
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#define K230_DDRC_STAT 0x004
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#define K230_DDRC_DRAMTMG4 0x110
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#define K230_DDRC_DFIMISC 0x1b0
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#define K230_DDRC_DFISTAT 0x1bc
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#define K230_DDRC_SWCTL 0x320
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#define K230_DDRC_SWSTAT 0x324
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#define K230_DDRC_STAT_OPERATING_MODE_MASK 0x7
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#define K230_DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK 0x1
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#define K230_DDR_PHY_CSR(index) \
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(K230_DDR_PHY_BASE + (uint64_t)(index) * sizeof(uint32_t))
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#define K230_DDR_PHY_ATX_IMPEDANCE 0x00043
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#define K230_DDR_PHY_TX_IMPEDANCE_CTRL1 0x10049
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#define K230_DDR_PHY_VREF_IN_GLOBAL 0x200b2
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#define K230_DDR_PHY_MICRO_CONT_MUX_SEL 0xd0000
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#define K230_DDR_PHY_TRAINING_STATUS 0xd0004
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#define K230_DDR_PHY_TRAINING_ACK 0xd0031
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#define K230_DDR_PHY_TRAINING_MESSAGE 0xd0032
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#define K230_DDR_PHY_TRAINING_TRIGGER 0xd0099
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static void complete_phy_training(QTestState *qts)
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{
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qtest_writel(qts,
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K230_DDR_PHY_CSR(K230_DDR_PHY_MICRO_CONT_MUX_SEL), 1);
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qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_TRIGGER), 9);
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qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_TRIGGER), 1);
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qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_TRIGGER), 0);
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}
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static void test_reset_and_register_access(void)
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{
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QTestState *qts = qtest_init("-machine k230");
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_MSTR),
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==, 0x01040000);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT),
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==, 0x00000000);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DRAMTMG4),
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==, 0x05040405);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC),
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==, 0x00000001);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWCTL),
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==, 0x00000001);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT),
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==, 0x00000001);
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g_assert_cmphex(qtest_readl(qts,
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K230_DDR_PHY_CSR(K230_DDR_PHY_ATX_IMPEDANCE)),
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==, 0x03ff);
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g_assert_cmphex(qtest_readl(qts,
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K230_DDR_PHY_CSR(K230_DDR_PHY_TX_IMPEDANCE_CTRL1)),
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==, 0x0fff);
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g_assert_cmphex(qtest_readl(qts,
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K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL)),
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==, 0x0200);
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qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_MSTR, 0x01040008);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_MSTR),
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==, 0x01040008);
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qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_STAT, 0xffffffff);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT),
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==, 0x00000000);
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qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL),
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0xffffffff);
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g_assert_cmphex(qtest_readl(qts,
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K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL)),
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==, 0x7fff);
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qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DRAMTMG4, 0);
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qtest_system_reset(qts);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_MSTR),
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==, 0x01040000);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DRAMTMG4),
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==, 0x05040405);
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g_assert_cmphex(qtest_readl(qts,
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K230_DDR_PHY_CSR(K230_DDR_PHY_VREF_IN_GLOBAL)),
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==, 0x0200);
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qtest_quit(qts);
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}
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static void test_software_update_handshake(void)
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{
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QTestState *qts = qtest_init("-machine k230");
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qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_SWCTL, 0);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT),
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==, 0);
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qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_SWCTL, 1);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT),
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==, 1);
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qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT, 0);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_SWSTAT),
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==, 1);
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qtest_quit(qts);
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}
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static void test_phy_ownership(void)
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{
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QTestState *qts = qtest_init("-machine k230");
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uint64_t atx = K230_DDR_PHY_CSR(K230_DDR_PHY_ATX_IMPEDANCE);
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uint64_t mux = K230_DDR_PHY_CSR(K230_DDR_PHY_MICRO_CONT_MUX_SEL);
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qtest_writel(qts, atx, 0x155);
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g_assert_cmphex(qtest_readl(qts, atx), ==, 0x155);
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qtest_writel(qts, mux, 1);
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qtest_writel(qts, atx, 0x2aa);
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g_assert_cmphex(qtest_readl(qts, atx), ==, 0x155);
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qtest_writel(qts, mux, 0);
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qtest_writel(qts, atx, 0x2aa);
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g_assert_cmphex(qtest_readl(qts, atx), ==, 0x2aa);
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qtest_quit(qts);
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}
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static void test_dfi_prerequisites(void)
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{
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QTestState *qts = qtest_init("-machine k230");
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qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0x20);
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g_assert_cmphex(qtest_readl(qts,
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K230_DDRC_BASE + K230_DDRC_DFISTAT) &
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K230_DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK,
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==, 0);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT) &
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K230_DDRC_STAT_OPERATING_MODE_MASK,
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==, 0);
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qtest_quit(qts);
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}
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static void test_dfi_complete_enable(void)
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{
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QTestState *qts = qtest_init("-machine k230");
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complete_phy_training(qts);
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qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0x20);
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g_assert_cmphex(qtest_readl(qts,
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K230_DDRC_BASE + K230_DDRC_DFISTAT) &
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K230_DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK,
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==, 1);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT) &
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K230_DDRC_STAT_OPERATING_MODE_MASK,
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==, 0);
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qtest_quit(qts);
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}
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static void test_training_and_dfi_handshake(void)
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{
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QTestState *qts = qtest_init("-machine k230");
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complete_phy_training(qts);
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g_assert_cmphex(qtest_readl(qts,
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K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_STATUS)),
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==, 0);
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g_assert_cmphex(qtest_readl(qts,
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K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_MESSAGE)),
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==, 0x07);
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qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_ACK), 0);
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g_assert_cmphex(qtest_readl(qts,
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K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_STATUS)),
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==, 1);
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qtest_writel(qts, K230_DDR_PHY_CSR(K230_DDR_PHY_TRAINING_ACK), 1);
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qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0x20);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_DFISTAT),
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==, 1);
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qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 0);
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qtest_writel(qts, K230_DDRC_BASE + K230_DDRC_DFIMISC, 1);
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g_assert_cmphex(qtest_readl(qts, K230_DDRC_BASE + K230_DDRC_STAT) & 0x7,
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==, 1);
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qtest_quit(qts);
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}
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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qtest_add_func("/k230-ddr/reset-and-register-access",
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test_reset_and_register_access);
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qtest_add_func("/k230-ddr/software-update-handshake",
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test_software_update_handshake);
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qtest_add_func("/k230-ddr/phy-ownership", test_phy_ownership);
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qtest_add_func("/k230-ddr/dfi-prerequisites", test_dfi_prerequisites);
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qtest_add_func("/k230-ddr/dfi-complete-enable",
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test_dfi_complete_enable);
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qtest_add_func("/k230-ddr/training-and-dfi-handshake",
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test_training_and_dfi_handshake);
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return g_test_run();
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}
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@ -299,7 +299,8 @@ qtests_riscv64 = ['riscv-csr-test'] + \
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(config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and
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config_all_devices.has_key('CONFIG_RISCV_IOMMU') ?
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['iommu-riscv-test'] : []) + \
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(config_all_devices.has_key('CONFIG_K230') ? ['k230-wdt-test'] : [])
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(config_all_devices.has_key('CONFIG_K230') ?
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['k230-ddr-test', 'k230-wdt-test'] : [])
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qtests_hexagon = ['boot-serial-test', 'l2vic-test', 'qct-qtimer-test']
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