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i386/kvm: Add save/restore support for CET MSRs
CET (architectural) MSRs include:
MSR_IA32_U_CET - user mode CET control bits.
MSR_IA32_S_CET - supervisor mode CET control bits.
MSR_IA32_PL{0,1,2,3}_SSP - linear addresses of SSPs for user/kernel modes.
MSR_IA32_INT_SSP_TAB - linear address of interrupt SSP table
Since FRED also needs to save/restore MSR_IA32_PL0_SSP, to avoid duplicate
operations, make FRED only save/restore MSR_IA32_PL0_SSP when CET-SHSTK
is not enumerated.
And considerring MSR_IA32_SSP_TBL_ADDR is only presented on 64 bit
processor, wrap it with TARGET_X86_64 macro.
For other MSRs, add save/restore support directly.
Tested-by: Farrah Chen <farrah.chen@intel.com>
Suggested-by: Xin Li (Intel) <xin@zytor.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Co-developed-by: Chao Gao <chao.gao@intel.com>
Signed-off-by: Chao Gao <chao.gao@intel.com>
Co-developed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20251211060801.3600039-15-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Yang Weijiang
Paolo Bonzini
parent
0fa1025904
commit
b6f85c5e45
2 changed files with 98 additions and 19 deletions
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@ -543,7 +543,7 @@ typedef enum X86Seg {
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#define MSR_IA32_XFD 0x000001c4
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#define MSR_IA32_XFD_ERR 0x000001c5
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/* FRED MSRs */
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/* FRED MSRs (MSR_IA32_FRED_SSP0 is defined as MSR_IA32_PL0_SSP in CET MSRs) */
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#define MSR_IA32_FRED_RSP0 0x000001cc /* Stack level 0 regular stack pointer */
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#define MSR_IA32_FRED_RSP1 0x000001cd /* Stack level 1 regular stack pointer */
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#define MSR_IA32_FRED_RSP2 0x000001ce /* Stack level 2 regular stack pointer */
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@ -554,9 +554,6 @@ typedef enum X86Seg {
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#define MSR_IA32_FRED_SSP3 0x000001d3 /* Stack level 3 shadow stack pointer in ring 0 */
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#define MSR_IA32_FRED_CONFIG 0x000001d4 /* FRED Entrypoint and interrupt stack level */
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/* FRED and CET MSR */
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#define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer (aka MSR_IA32_FRED_SSP0 for FRED) */
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#define MSR_IA32_BNDCFGS 0x00000d90
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#define MSR_IA32_XSS 0x00000da0
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#define MSR_IA32_UMWAIT_CONTROL 0xe1
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@ -583,6 +580,15 @@ typedef enum X86Seg {
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#define MSR_APIC_START 0x00000800
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#define MSR_APIC_END 0x000008ff
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/* CET MSRs */
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#define MSR_IA32_U_CET 0x000006a0 /* user mode cet */
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#define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */
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#define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */
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#define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */
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#define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */
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#define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */
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#define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */
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#define XSTATE_FP_BIT 0
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#define XSTATE_SSE_BIT 1
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#define XSTATE_YMM_BIT 2
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@ -1973,8 +1979,16 @@ typedef struct CPUArchState {
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uint64_t fred_config;
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#endif
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/* MSR used for both FRED and CET (SHSTK) */
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uint64_t pl0_ssp;
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/* CET MSRs */
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uint64_t u_cet;
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uint64_t s_cet;
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uint64_t pl0_ssp; /* also used for FRED */
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uint64_t pl1_ssp;
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uint64_t pl2_ssp;
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uint64_t pl3_ssp;
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#ifdef TARGET_X86_64
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uint64_t int_ssp_table;
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#endif
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uint64_t tsc_adjust;
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uint64_t tsc_deadline;
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@ -4009,11 +4009,14 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState level)
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kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, env->fred_ssp2);
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kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, env->fred_ssp3);
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kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, env->fred_config);
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/*
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* Aka MSR_IA32_FRED_SSP0. This MSR is accessible even if
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* CET shadow stack is not supported.
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*/
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kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, env->pl0_ssp);
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if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK)) {
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/*
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* Aka MSR_IA32_FRED_SSP0. This MSR is accessible even if
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* CET shadow stack is not supported.
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*/
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kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, env->pl0_ssp);
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}
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}
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}
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#endif
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@ -4267,6 +4270,26 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState level)
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}
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}
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if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK ||
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env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT) {
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kvm_msr_entry_add(cpu, MSR_IA32_U_CET, env->u_cet);
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kvm_msr_entry_add(cpu, MSR_IA32_S_CET, env->s_cet);
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if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) {
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kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, env->pl0_ssp);
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kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, env->pl1_ssp);
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kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, env->pl2_ssp);
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kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, env->pl3_ssp);
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#ifdef TARGET_X86_64
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if (lm_capable_kernel) {
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kvm_msr_entry_add(cpu, MSR_IA32_INT_SSP_TAB,
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env->int_ssp_table);
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}
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#endif
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}
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}
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return kvm_buf_set_msrs(cpu);
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}
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@ -4501,11 +4524,14 @@ static int kvm_get_msrs(X86CPU *cpu)
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kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, 0);
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kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, 0);
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kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, 0);
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/*
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* Aka MSR_IA32_FRED_SSP0. This MSR is accessible even if
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* CET shadow stack is not supported.
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*/
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kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, 0);
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if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK)) {
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/*
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* Aka MSR_IA32_FRED_SSP0. This MSR is accessible even if
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* CET shadow stack is not supported.
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*/
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kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, 0);
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}
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}
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}
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#endif
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@ -4663,6 +4689,25 @@ static int kvm_get_msrs(X86CPU *cpu)
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}
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}
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if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK ||
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env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT) {
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kvm_msr_entry_add(cpu, MSR_IA32_U_CET, 0);
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kvm_msr_entry_add(cpu, MSR_IA32_S_CET, 0);
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if (env->features[FEAT_7_0_EDX] & CPUID_7_0_ECX_CET_SHSTK) {
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kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, 0);
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kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, 0);
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kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, 0);
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kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, 0);
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#ifdef TARGET_X86_64
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if (lm_capable_kernel) {
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kvm_msr_entry_add(cpu, MSR_IA32_INT_SSP_TAB, 0);
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}
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#endif
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}
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}
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ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
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if (ret < 0) {
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return ret;
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@ -4757,9 +4802,6 @@ static int kvm_get_msrs(X86CPU *cpu)
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case MSR_IA32_FRED_CONFIG:
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env->fred_config = msrs[i].data;
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break;
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case MSR_IA32_PL0_SSP: /* aka MSR_IA32_FRED_SSP0 */
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env->pl0_ssp = msrs[i].data;
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break;
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#endif
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case MSR_IA32_TSC:
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env->tsc = msrs[i].data;
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@ -5013,6 +5055,29 @@ static int kvm_get_msrs(X86CPU *cpu)
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case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
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env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
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break;
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case MSR_IA32_U_CET:
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env->u_cet = msrs[i].data;
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break;
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case MSR_IA32_S_CET:
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env->s_cet = msrs[i].data;
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break;
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case MSR_IA32_PL0_SSP: /* aka MSR_IA32_FRED_SSP0 */
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env->pl0_ssp = msrs[i].data;
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break;
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case MSR_IA32_PL1_SSP:
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env->pl1_ssp = msrs[i].data;
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break;
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case MSR_IA32_PL2_SSP:
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env->pl2_ssp = msrs[i].data;
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break;
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case MSR_IA32_PL3_SSP:
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env->pl3_ssp = msrs[i].data;
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break;
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#ifdef TARGET_X86_64
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case MSR_IA32_INT_SSP_TAB:
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env->int_ssp_table = msrs[i].data;
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break;
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#endif
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case MSR_K7_HWCR:
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env->msr_hwcr = msrs[i].data;
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break;
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