uefi-ref/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu.git synced 2026-08-26 22:23:12 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/hexagon: handle misaligned load/store cause codes in cpu_loop

Browse source 
Add a linux-user cpu_loop handler for HEX_CAUSE_MISALIGNED_LOAD and
HEX_CAUSE_MISALIGNED_STORE, raising SIGBUS for consistency with
hexswi.c's sysemu handling, even though linux-user's own alignment
check in accel/tcg/user-exec.c currently raises SIGBUS before
Hexagon's cause-code machinery is reached.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
This commit is contained in:
Brian Cain 2026-07-13 18:09:51 -07:00
parent 8aea63e965
commit d7a6df755b
1 changed files with 5 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

5
linux-user/hexagon/cpu_loop.c
View file

@ -76,6 +76,11 @@ void cpu_loop(CPUHexagonState *env)
force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC,
env->gpr[HEX_REG_PC]);
break;
case HEX_CAUSE_MISALIGNED_LOAD:
case HEX_CAUSE_MISALIGNED_STORE:
force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,
env->gpr[HEX_REG_PC]);
break;
default:
EXCP_DUMP(env, "\nqemu: unhandled CPU precise exception "
"cause code 0x%x - aborting\n",