mirror of
https://gitlab.com/qemu-project/qemu.git
synced 2026-08-26 22:23:12 -04:00
Compare commits
No commits in common. "master" and "v11.1.0-rc2" have entirely different histories.
master
...
v11.1.0-rc
734 changed files with 9590 additions and 29915 deletions
|
|
@ -14,7 +14,7 @@
|
|||
- echo "TAG:$TAG"
|
||||
- echo "COMMON_TAG:$COMMON_TAG"
|
||||
- docker build --tag "$TAG" --cache-from "$TAG" --cache-from "$COMMON_TAG"
|
||||
--build-arg BUILDKIT_INLINE_CACHE=1 --provenance=false
|
||||
--build-arg BUILDKIT_INLINE_CACHE=1
|
||||
-f "tests/docker/dockerfiles/$NAME.docker" "."
|
||||
- docker push "$TAG"
|
||||
after_script:
|
||||
|
|
|
|||
|
|
@ -12,5 +12,5 @@ NINJA='/opt/homebrew/bin/ninja'
|
|||
PACKAGING_COMMAND='brew'
|
||||
PIP3='/opt/homebrew/bin/pip3'
|
||||
PKGS='bash bc bindgen bison bzip2 capstone ccache cmocka coreutils ctags curl dbus diffutils dtc flex gcovr gettext git glib gnu-sed gnutls gtk+3 gtk-vnc jemalloc jpeg-turbo json-c libcbor libepoxy libffi libgcrypt libiscsi libnfs libpng libslirp libssh libtasn1 libusb llvm lzo make meson mtools ncurses nettle ninja pixman pkg-config python-setuptools python3 rpm2cpio rust sdl2 sdl2_image snappy socat sparse spice-protocol swtpm tesseract usbredir vde vte3 vulkan-tools xorriso zlib zstd'
|
||||
PYPI_PKGS='sphinx sphinx-rtd-theme tomli'
|
||||
PYPI_PKGS='PyYAML numpy pillow sphinx sphinx-rtd-theme tomli'
|
||||
PYTHON='/opt/homebrew/bin/python3'
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ check-rust-tools-nightly:
|
|||
- source scripts/ci/gitlab-ci-section
|
||||
- section_start test "Running Rust code checks"
|
||||
- cd build
|
||||
- pyvenv/bin/meson devenv -w ../ ${CARGO-cargo} fmt --check
|
||||
- pyvenv/bin/meson devenv -w ../rust ${CARGO-cargo} fmt --check
|
||||
- make clippy
|
||||
- make rustdoc
|
||||
- section_end test
|
||||
|
|
@ -69,7 +69,7 @@ check-rust-tools-nightly:
|
|||
when: on_success
|
||||
expire_in: 2 days
|
||||
paths:
|
||||
- target/doc
|
||||
- rust/target/doc
|
||||
|
||||
check-build-units:
|
||||
extends: .base_job_template
|
||||
|
|
|
|||
80
MAINTAINERS
80
MAINTAINERS
|
|
@ -250,12 +250,6 @@ M: Brian Cain <brian.cain@oss.qualcomm.com>
|
|||
R: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
|
||||
S: Supported
|
||||
F: target/hexagon/
|
||||
F: hw/intc/hex-l2vic.c
|
||||
F: include/hw/intc/hex-l2vic.h
|
||||
F: tests/qtest/l2vic-test.c
|
||||
F: hw/timer/qct-qtimer.c
|
||||
F: include/hw/timer/qct-qtimer.h
|
||||
F: tests/qtest/qct-qtimer-test.c
|
||||
X: target/hexagon/idef-parser/
|
||||
X: target/hexagon/gen_idef_parser_funcs.py
|
||||
F: linux-user/hexagon/
|
||||
|
|
@ -268,7 +262,6 @@ F: gdbstub/gdb-xml/hexagon*.xml
|
|||
F: docs/system/target-hexagon.rst
|
||||
F: docs/system/hexagon/
|
||||
F: docs/devel/hexagon-sys.rst
|
||||
F: docs/devel/hexagon-l2vic.rst
|
||||
T: git https://github.com/qualcomm/qemu.git hex-next
|
||||
|
||||
Hexagon idef-parser
|
||||
|
|
@ -497,7 +490,6 @@ F: tests/functional/aarch64/test_kvm.py
|
|||
PPC KVM CPUs
|
||||
M: Nicholas Piggin <npiggin@gmail.com>
|
||||
R: Harsh Prateek Bora <harshpb@linux.ibm.com>
|
||||
R: Amit Machhiwal <amachhiw@linux.ibm.com>
|
||||
S: Odd Fixes
|
||||
F: target/ppc/kvm.c
|
||||
|
||||
|
|
@ -621,7 +613,6 @@ R: Wei Liu <wei.liu@kernel.org>
|
|||
R: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
|
||||
S: Supported
|
||||
F: target/i386/mshv/
|
||||
F: hw/i386/mshv/
|
||||
|
||||
X86 Instruction Emulator
|
||||
M: Roman Bolshakov <rbolshakov@ddn.com>
|
||||
|
|
@ -1309,15 +1300,6 @@ M: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
|
|||
S: Maintained
|
||||
F: rust/hw/char/pl011/
|
||||
|
||||
Axiado SoCs and EVKs
|
||||
M: Kuan-Jui Chiu <kchiu@axiado.com>
|
||||
L: qemu-arm@nongnu.org
|
||||
S: Maintained
|
||||
F: hw/arm/ax3000*.c
|
||||
F: hw/*/axiado*.c
|
||||
F: include/hw/arm/ax3000*.h
|
||||
F: include/hw/*/axiado*.h
|
||||
|
||||
AVR Machines
|
||||
-------------
|
||||
|
||||
|
|
@ -1663,7 +1645,6 @@ F: tests/functional/ppc/test_40p.py
|
|||
sPAPR (pseries)
|
||||
M: Nicholas Piggin <npiggin@gmail.com>
|
||||
M: Harsh Prateek Bora <harshpb@linux.ibm.com>
|
||||
R: Amit Machhiwal <amachhiw@linux.ibm.com>
|
||||
L: qemu-ppc@nongnu.org
|
||||
S: Odd Fixes
|
||||
F: hw/*/spapr*
|
||||
|
|
@ -1765,22 +1746,6 @@ F: include/hw/ppc/vof*
|
|||
F: pc-bios/vof/*
|
||||
F: pc-bios/vof*
|
||||
|
||||
PowerPC RAS (Reliability, Availability and Serviceability)
|
||||
M: Aditya Gupta <adityag@linux.ibm.com>
|
||||
R: Sourabh Jain <sourabhjain@linux.ibm.com>
|
||||
R: Hari Bathini <hbathini@linux.ibm.com>
|
||||
R: Shivang Upadhyay <shivangu@linux.ibm.com>
|
||||
L: qemu-ppc@nongnu.org
|
||||
S: Maintained
|
||||
F: hw/ppc/spapr_events.c
|
||||
F: hw/ppc/spapr_fadump.c
|
||||
F: hw/ppc/spapr_pci_vfio.c
|
||||
F: hw/ppc/spapr_rtas.c
|
||||
F: hw/ppc/pnv_mpipl.c
|
||||
F: include/hw/ppc/spapr_fadump.h
|
||||
F: include/hw/ppc/pnv_mpipl.h
|
||||
F: tests/functional/ppc64/test_fadump.py
|
||||
|
||||
RISC-V Machines
|
||||
---------------
|
||||
OpenTitan
|
||||
|
|
@ -1862,21 +1827,12 @@ M: Chao Liu <chao.liu@processmission.com>
|
|||
L: qemu-riscv@nongnu.org
|
||||
S: Maintained
|
||||
F: docs/system/riscv/k230.rst
|
||||
F: hw/misc/k230_ddr.c
|
||||
F: hw/riscv/k230.c
|
||||
F: hw/watchdog/k230_wdt.c
|
||||
F: hw/dma/k230_gsdma.c
|
||||
F: hw/misc/k230_decomp_gzip.c
|
||||
F: include/hw/misc/k230_ddr.h
|
||||
F: include/hw/riscv/k230.h
|
||||
F: include/hw/watchdog/k230_wdt.h
|
||||
F: include/hw/dma/k230_gsdma.h
|
||||
F: include/hw/misc/k230_decomp_gzip.h
|
||||
F: tests/functional/riscv64/test_k230.py
|
||||
F: tests/qtest/k230-ddr-test.c
|
||||
F: tests/qtest/k230-wdt-test.c
|
||||
F: tests/qtest/k230-gsdma-test.c
|
||||
F: tests/qtest/k230-decomp-gzip-test.c
|
||||
|
||||
RX Machines
|
||||
-----------
|
||||
|
|
@ -2121,7 +2077,6 @@ Machine core
|
|||
M: Philippe Mathieu-Daudé <philmd@mailo.com>
|
||||
R: Zhao Liu <zhao1.liu@intel.com>
|
||||
S: Maintained
|
||||
F: hw/core/cpu-internal.h
|
||||
F: hw/core/cpu-common.c
|
||||
F: hw/core/cpu-system.c
|
||||
F: hw/core/machine-qmp-cmds.c
|
||||
|
|
@ -2205,7 +2160,6 @@ F: docs/specs/edu.rst
|
|||
|
||||
IDE
|
||||
M: John Snow <jsnow@redhat.com>
|
||||
M: Denis V. Lunev <den@openvz.org>
|
||||
L: qemu-block@nongnu.org
|
||||
S: Odd Fixes
|
||||
F: include/hw/ide/
|
||||
|
|
@ -2879,19 +2833,6 @@ F: include/hw/acpi/vmgenid.h
|
|||
F: docs/specs/vmgenid.rst
|
||||
F: tests/qtest/vmgenid-test.c
|
||||
|
||||
VM Launch Update
|
||||
M: Ani Sinha <anisinha@redhat.com>
|
||||
M: Gerd Hoffman <kraxel@redhat.com>
|
||||
S: Maintained
|
||||
F: hw/misc/vmlaunchupdate.c
|
||||
F: include/hw/misc/vmlaunchupdate.h
|
||||
F: include/standard-headers/misc/vmlaunchupdate.h
|
||||
F: docs/specs/vmlaunchupdate.rst
|
||||
F: tests/functional/aarch64/test_vm_launch_update_aarch.py
|
||||
F: tests/functional/x86_64/test_vm_launch_update.py
|
||||
F: tests/qtest/launchupdate-test.c
|
||||
F: tests/data/igvm/*
|
||||
|
||||
LED
|
||||
M: Philippe Mathieu-Daudé <philmd@mailo.com>
|
||||
S: Maintained
|
||||
|
|
@ -3427,6 +3368,23 @@ F: scripts/coccinelle/remove_local_err.cocci
|
|||
F: scripts/coccinelle/use-error_fatal.cocci
|
||||
F: scripts/coccinelle/errp-guard.cocci
|
||||
|
||||
Firmware Assisted Dump (fadump) for sPAPR (pseries)
|
||||
M: Aditya Gupta <adityag@linux.ibm.com>
|
||||
R: Sourabh Jain <sourabhjain@linux.ibm.com>
|
||||
S: Maintained
|
||||
F: include/hw/ppc/spapr_fadump.h
|
||||
F: hw/ppc/spapr_fadump.c
|
||||
F: tests/functional/ppc64/test_fadump.py
|
||||
|
||||
Memory-Preserving Initial Program Load (MPIPL) for PowerNV
|
||||
M: Aditya Gupta <adityag@linux.ibm.com>
|
||||
R: Hari Bathini <hbathini@linux.ibm.com>
|
||||
R: Sourabh <sourabhjain@linux.ibm.com>
|
||||
S: Maintained
|
||||
F: include/hw/ppc/pnv_mpipl.h
|
||||
F: hw/ppc/pnv_mpipl.c
|
||||
F: tests/functional/ppc64/test_fadump.py
|
||||
|
||||
GDB stub
|
||||
M: Alex Bennée <alex.bennee@linaro.org>
|
||||
R: Philippe Mathieu-Daudé <philmd@mailo.com>
|
||||
|
|
@ -3460,7 +3418,6 @@ F: system/ioport.c
|
|||
F: system/memory.c
|
||||
F: system/memory_mapping.c
|
||||
F: system/physmem.c
|
||||
F: system/physmem-qmp-cmds.c
|
||||
F: system/memory_ldst*
|
||||
F: system/memory-internal.h
|
||||
F: system/ram-block-attributes.c
|
||||
|
|
@ -3900,7 +3857,6 @@ Migration dirty limit and dirty page rate
|
|||
M: Hyman Huang <infra.ai.cloud@bitdeer.com>
|
||||
S: Maintained
|
||||
F: system/dirtylimit.c
|
||||
F: system/dirtylimit-hmp-cmds.c
|
||||
F: include/system/dirtylimit.h
|
||||
F: migration/dirtyrate.c
|
||||
F: migration/dirtyrate.h
|
||||
|
|
@ -4142,7 +4098,7 @@ F: tests/uefi-test-tools/
|
|||
IGVM Firmware
|
||||
M: Gerd Hoffmann <kraxel@redhat.com>
|
||||
M: Stefano Garzarella <sgarzare@redhat.com>
|
||||
M: Ani Sinha <anisinha@redhat.com>
|
||||
R: Ani Sinha <anisinha@redhat.com>
|
||||
S: Maintained
|
||||
F: backends/igvm*.c
|
||||
F: docs/system/igvm.rst
|
||||
|
|
|
|||
2
VERSION
2
VERSION
|
|
@ -1 +1 @@
|
|||
11.1.50
|
||||
11.0.92
|
||||
|
|
|
|||
|
|
@ -39,8 +39,6 @@
|
|||
#include "system/mshv.h"
|
||||
#include "system/mshv_int.h"
|
||||
#include "system/reset.h"
|
||||
#include "migration/qemu-file-types.h"
|
||||
#include "migration/register.h"
|
||||
#include "trace.h"
|
||||
#include <err.h>
|
||||
#include <sys/ioctl.h>
|
||||
|
|
@ -60,29 +58,53 @@ static int init_mshv(int *mshv_fd)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int mshv_load_cleanup(void *opaque)
|
||||
/* freeze 1 to pause, 0 to resume */
|
||||
static int set_time_freeze(int vm_fd, int freeze)
|
||||
{
|
||||
CPUState *cpu;
|
||||
int ret;
|
||||
struct hv_input_set_partition_property in = {0};
|
||||
in.property_code = HV_PARTITION_PROPERTY_TIME_FREEZE;
|
||||
in.property_value = freeze;
|
||||
|
||||
ret = mshv_arch_set_partition_msrs(first_cpu);
|
||||
struct mshv_root_hvcall args = {0};
|
||||
args.code = HVCALL_SET_PARTITION_PROPERTY;
|
||||
args.in_sz = sizeof(in);
|
||||
args.in_ptr = (uint64_t)∈
|
||||
|
||||
ret = mshv_hvcall(vm_fd, &args);
|
||||
if (ret < 0) {
|
||||
error_report("Failed to set partition MSRs: %s", strerror(-ret));
|
||||
error_report("Failed to set time freeze");
|
||||
return -1;
|
||||
}
|
||||
|
||||
CPU_FOREACH(cpu) {
|
||||
ret = mshv_arch_set_mp_state(cpu);
|
||||
if (ret < 0) {
|
||||
error_report("Failed to set mp state for vCPU %d: %s",
|
||||
cpu->cpu_index, strerror(-ret));
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pause_vm(int vm_fd)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = set_time_freeze(vm_fd, 1);
|
||||
if (ret < 0) {
|
||||
error_report("Failed to pause partition: %s", strerror(errno));
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int resume_vm(int vm_fd)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = set_time_freeze(vm_fd, 0);
|
||||
if (ret < 0) {
|
||||
error_report("Failed to resume partition: %s", strerror(errno));
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_host_partition_property(int mshv_fd, uint32_t property_code,
|
||||
uint64_t *value)
|
||||
|
|
@ -181,14 +203,6 @@ static int create_partition(int mshv_fd, int *vm_fd)
|
|||
|
||||
/* enable all */
|
||||
disabled_xsave_features.as_uint64 = 0;
|
||||
/*
|
||||
* AMX TILE XSAVE state (XTILE_DATA) is 8KB, which exceeds the
|
||||
* current fixed 4KB XSAVE buffer size.
|
||||
*/
|
||||
disabled_xsave_features.amx_tile_support = 1;
|
||||
disabled_xsave_features.amx_bf16_support = 1;
|
||||
disabled_xsave_features.amx_int8_support = 1;
|
||||
disabled_xsave_features.amx_fp16_support = 1;
|
||||
|
||||
/*
|
||||
* query host for supported processor features and disable unsupported
|
||||
|
|
@ -306,6 +320,9 @@ static int create_vm(int mshv_fd, int *vm_fd)
|
|||
return -1;
|
||||
}
|
||||
|
||||
/* Always create a frozen partition */
|
||||
pause_vm(*vm_fd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -519,10 +536,6 @@ static int mshv_init_vcpu(CPUState *cpu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static SaveVMHandlers savevm_mshv = {
|
||||
.load_cleanup = mshv_load_cleanup,
|
||||
};
|
||||
|
||||
static int mshv_init(AccelState *as, MachineState *ms)
|
||||
{
|
||||
MshvState *s;
|
||||
|
|
@ -552,6 +565,13 @@ static int mshv_init(AccelState *as, MachineState *ms)
|
|||
return -1;
|
||||
}
|
||||
|
||||
ret = resume_vm(vm_fd);
|
||||
if (ret < 0) {
|
||||
close(mshv_fd);
|
||||
close(vm_fd);
|
||||
return -1;
|
||||
}
|
||||
|
||||
s->vm = vm_fd;
|
||||
s->fd = mshv_fd;
|
||||
|
||||
|
|
@ -571,10 +591,6 @@ static int mshv_init(AccelState *as, MachineState *ms)
|
|||
0, "mshv-memory");
|
||||
memory_listener_register(&mshv_io_listener, &address_space_io);
|
||||
|
||||
register_savevm_live("mshv", 0, 1, &savevm_mshv, s);
|
||||
|
||||
mshv_clock_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -612,13 +628,6 @@ static int mshv_cpu_exec(CPUState *cpu)
|
|||
cpu->vcpu_dirty = false;
|
||||
}
|
||||
|
||||
/* Corresponding store-release is in cpu_exit. */
|
||||
if (qatomic_load_acquire(&cpu->exit_request)) {
|
||||
trace_mshv_interrupt_exit_request(cpu->cpu_index);
|
||||
ret = EXCP_INTERRUPT;
|
||||
break;
|
||||
}
|
||||
|
||||
ret = mshv_run_vcpu(mshv_state->vm, cpu, &mshv_msg, &exit_reason);
|
||||
if (ret < 0) {
|
||||
error_report("Failed to run on vcpu %d", cpu->cpu_index);
|
||||
|
|
@ -646,13 +655,17 @@ static int mshv_cpu_exec(CPUState *cpu)
|
|||
}
|
||||
|
||||
/*
|
||||
* We need a dummy handler to make SIG_IPI a deliverable signal. The kernel
|
||||
* handler will be woken up by the caught signal and instruct the hypervisor
|
||||
* to suspend execution (the concrete mechanism differs between schedulers)
|
||||
* and return to userspace.
|
||||
* The signal handler is triggered when QEMU's main thread receives a SIG_IPI
|
||||
* (SIGUSR1). This signal causes the current CPU thread to be kicked, forcing a
|
||||
* VM exit on the CPU. The VM exit generates an exit reason that breaks the loop
|
||||
* (see mshv_cpu_exec). If the exit is due to a Ctrl+A+x command, the system
|
||||
* will shut down. For other cases, the system will continue running.
|
||||
*/
|
||||
static void dummy_handler(int sig)
|
||||
static void sa_ipi_handler(int sig)
|
||||
{
|
||||
/* TODO: call IOCTL to set_immediate_exit, once implemented. */
|
||||
|
||||
qemu_cpu_kick_self();
|
||||
}
|
||||
|
||||
static void init_signal(CPUState *cpu)
|
||||
|
|
@ -662,7 +675,7 @@ static void init_signal(CPUState *cpu)
|
|||
sigset_t set;
|
||||
|
||||
memset(&sigact, 0, sizeof(sigact));
|
||||
sigact.sa_handler = dummy_handler;
|
||||
sigact.sa_handler = sa_ipi_handler;
|
||||
sigaction(SIG_IPI, &sigact, NULL);
|
||||
|
||||
pthread_sigmask(SIG_BLOCK, NULL, &set);
|
||||
|
|
@ -838,7 +851,6 @@ static void mshv_accel_ops_class_init(ObjectClass *oc, const void *data)
|
|||
ops->synchronize_state = mshv_cpu_synchronize;
|
||||
ops->synchronize_pre_loadvm = mshv_cpu_synchronize_pre_loadvm;
|
||||
ops->cpus_are_resettable = mshv_cpus_are_resettable;
|
||||
ops->cpu_thread_is_idle = mshv_vcpu_thread_is_idle;
|
||||
ops->handle_interrupt = generic_handle_interrupt;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
mshv_start_vcpu_thread(const char* thread, uint32_t cpu) "thread=%s cpu_index=%d"
|
||||
mshv_interrupt_exit_request(uint32_t cpu) "cpu_index=%d"
|
||||
|
||||
mshv_set_memory(bool add, uint64_t gpa, uint64_t size, uint64_t user_addr, bool readonly, int ret) "add=%d gpa=0x%" PRIx64 " size=0x%" PRIx64 " user=0x%" PRIx64 " readonly=%d result=%d"
|
||||
mshv_mem_ioeventfd_add(uint64_t addr, uint32_t size, uint32_t data) "addr=0x%" PRIx64 " size=%d data=0x%x"
|
||||
|
|
|
|||
|
|
@ -387,22 +387,14 @@ static void record_save(DisasContextBase *db, vaddr pc,
|
|||
* Either the first or second page may be I/O. If it is the second,
|
||||
* then the first byte we need to record will be at a non-zero offset.
|
||||
* In either case, we should not need to record but a single insn.
|
||||
*
|
||||
* A read may re-read bytes that are already recorded: a target may
|
||||
* fetch a whole aligned word to decode an insn (e.g. riscv Ziccif),
|
||||
* then probe the following insn, which lies within that same word.
|
||||
* Such a read extends the record only by the bytes past its end.
|
||||
*/
|
||||
if (db->record_len == 0) {
|
||||
db->record_start = offset;
|
||||
db->record_len = size;
|
||||
} else {
|
||||
int end = offset - db->record_start + size;
|
||||
|
||||
assert(offset >= db->record_start);
|
||||
assert(offset <= db->record_start + db->record_len);
|
||||
assert(end <= sizeof(db->record));
|
||||
db->record_len = MAX(db->record_len, end);
|
||||
assert(offset == db->record_start + db->record_len);
|
||||
assert(db->record_len + size <= sizeof(db->record));
|
||||
db->record_len += size;
|
||||
}
|
||||
|
||||
memcpy(db->record + (offset - db->record_start), from, size);
|
||||
|
|
|
|||
|
|
@ -52,8 +52,6 @@ static void igvm_reset_hold(Object *obj, ResetType type)
|
|||
|
||||
trace_igvm_reset_hold(type);
|
||||
|
||||
/* cleanup existing memory regions first */
|
||||
qigvm_cleanup_memory(igvm);
|
||||
qigvm_process_file(igvm, ms, false, &error_fatal);
|
||||
}
|
||||
|
||||
|
|
@ -67,7 +65,6 @@ static void igvm_complete(UserCreatable *uc, Error **errp)
|
|||
IgvmCfg *igvm = IGVM_CFG(uc);
|
||||
|
||||
igvm->file = qigvm_file_init(igvm->filename, errp);
|
||||
QTAILQ_INIT(&igvm->memory_regions);
|
||||
}
|
||||
|
||||
OBJECT_DEFINE_TYPE_WITH_INTERFACES(IgvmCfg, igvm_cfg, IGVM_CFG, OBJECT,
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
#include "qapi/error.h"
|
||||
#include "qemu/error-report.h"
|
||||
#include "qemu/target-info-qapi.h"
|
||||
#include "migration/vmstate.h"
|
||||
#include "system/igvm.h"
|
||||
#include "system/igvm-cfg.h"
|
||||
#include "system/igvm-internal.h"
|
||||
|
|
@ -179,8 +178,7 @@ static int qigvm_handler(QIgvm *ctx, IgvmVariableHeaderType raw_type,
|
|||
if (handlers[handler].type != type) {
|
||||
continue;
|
||||
}
|
||||
header_handle = igvm_get_header(ctx->cfg->file,
|
||||
handlers[handler].section,
|
||||
header_handle = igvm_get_header(ctx->file, handlers[handler].section,
|
||||
ctx->current_header_index);
|
||||
if (header_handle < 0) {
|
||||
error_setg(
|
||||
|
|
@ -189,7 +187,7 @@ static int qigvm_handler(QIgvm *ctx, IgvmVariableHeaderType raw_type,
|
|||
(int)header_handle);
|
||||
return -1;
|
||||
}
|
||||
header_data = igvm_get_buffer(ctx->cfg->file, header_handle);
|
||||
header_data = igvm_get_buffer(ctx->file, header_handle);
|
||||
if (header_data != NULL) {
|
||||
header_data += sizeof(IGVM_VHS_VARIABLE_HEADER);
|
||||
result = handlers[handler].handler(ctx, header_data, errp);
|
||||
|
|
@ -200,7 +198,7 @@ static int qigvm_handler(QIgvm *ctx, IgvmVariableHeaderType raw_type,
|
|||
header_handle, type);
|
||||
result = -1;
|
||||
}
|
||||
igvm_free_buffer(ctx->cfg->file, header_handle);
|
||||
igvm_free_buffer(ctx->file, header_handle);
|
||||
return result;
|
||||
}
|
||||
|
||||
|
|
@ -221,7 +219,7 @@ static void *qigvm_prepare_memory(QIgvm *ctx, uint64_t addr, uint64_t size,
|
|||
int region_identifier, Error **errp)
|
||||
{
|
||||
ERRP_GUARD();
|
||||
IgvmMemoryRegion *imr = NULL;
|
||||
MemoryRegion *igvm_pages = NULL;
|
||||
Int128 gpa_region_size;
|
||||
MemoryRegionSection mrs =
|
||||
memory_region_find(get_system_memory(), addr, size);
|
||||
|
|
@ -255,27 +253,23 @@ static void *qigvm_prepare_memory(QIgvm *ctx, uint64_t addr, uint64_t size,
|
|||
*/
|
||||
g_autofree char *region_name =
|
||||
g_strdup_printf("igvm.%X", region_identifier);
|
||||
imr = g_new0(IgvmMemoryRegion, 1);
|
||||
imr->mr = g_new0(MemoryRegion, 1);
|
||||
igvm_pages = g_new0(MemoryRegion, 1);
|
||||
if (ctx->machine_state->cgs &&
|
||||
ctx->machine_state->cgs->require_guest_memfd) {
|
||||
if (!memory_region_init_ram_guest_memfd(imr->mr, NULL,
|
||||
if (!memory_region_init_ram_guest_memfd(igvm_pages, NULL,
|
||||
region_name, size, errp)) {
|
||||
g_free(imr->mr);
|
||||
g_free(imr);
|
||||
g_free(igvm_pages);
|
||||
return NULL;
|
||||
}
|
||||
} else {
|
||||
if (!memory_region_init_ram(imr->mr, NULL, region_name, size,
|
||||
if (!memory_region_init_ram(igvm_pages, NULL, region_name, size,
|
||||
errp)) {
|
||||
g_free(imr->mr);
|
||||
g_free(imr);
|
||||
g_free(igvm_pages);
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
memory_region_add_subregion(get_system_memory(), addr, imr->mr);
|
||||
QTAILQ_INSERT_TAIL(&ctx->cfg->memory_regions, imr, next);
|
||||
return memory_region_get_ram_ptr(imr->mr);
|
||||
memory_region_add_subregion(get_system_memory(), addr, igvm_pages);
|
||||
return memory_region_get_ram_ptr(igvm_pages);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -350,8 +344,7 @@ static int qigvm_process_mem_region(QIgvm *ctx, unsigned start_index,
|
|||
|
||||
for (page_index = 0; page_index < page_count; page_index++) {
|
||||
data_handle = igvm_get_header_data(
|
||||
ctx->cfg->file, IGVM_HEADER_SECTION_DIRECTIVE,
|
||||
page_index + start_index);
|
||||
ctx->file, IGVM_HEADER_SECTION_DIRECTIVE, page_index + start_index);
|
||||
if (data_handle == IGVMAPI_NO_DATA) {
|
||||
/* No data indicates a zero page */
|
||||
memset(®ion[page_index * page_size], 0, page_size);
|
||||
|
|
@ -364,7 +357,7 @@ static int qigvm_process_mem_region(QIgvm *ctx, unsigned start_index,
|
|||
return -1;
|
||||
} else {
|
||||
zero = false;
|
||||
data_size = igvm_get_buffer_size(ctx->cfg->file, data_handle);
|
||||
data_size = igvm_get_buffer_size(ctx->file, data_handle);
|
||||
if (data_size < page_size) {
|
||||
memset(®ion[page_index * page_size], 0, page_size);
|
||||
} else if (data_size > page_size) {
|
||||
|
|
@ -374,14 +367,14 @@ static int qigvm_process_mem_region(QIgvm *ctx, unsigned start_index,
|
|||
page_index + start_index);
|
||||
return -1;
|
||||
}
|
||||
data = igvm_get_buffer(ctx->cfg->file, data_handle);
|
||||
data = igvm_get_buffer(ctx->file, data_handle);
|
||||
if (data == NULL) {
|
||||
error_setg(errp, "IGVM: No buffer for handle %d", data_handle);
|
||||
igvm_free_buffer(ctx->cfg->file, data_handle);
|
||||
igvm_free_buffer(ctx->file, data_handle);
|
||||
return -1;
|
||||
}
|
||||
memcpy(®ion[page_index * page_size], data, data_size);
|
||||
igvm_free_buffer(ctx->cfg->file, data_handle);
|
||||
igvm_free_buffer(ctx->file, data_handle);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -418,8 +411,7 @@ static int qigvm_process_mem_page(QIgvm *ctx,
|
|||
ctx->region_start = page_data->gpa;
|
||||
ctx->region_start_index = ctx->current_header_index;
|
||||
} else {
|
||||
if (!qigvm_page_attrs_equal(ctx->cfg->file,
|
||||
ctx->current_header_index,
|
||||
if (!qigvm_page_attrs_equal(ctx->file, ctx->current_header_index,
|
||||
page_data,
|
||||
&ctx->region_prev_page_data) ||
|
||||
((ctx->region_prev_page_data.gpa +
|
||||
|
|
@ -482,8 +474,7 @@ static int qigvm_directive_vp_context(QIgvm *ctx, const uint8_t *header_data,
|
|||
return 0;
|
||||
}
|
||||
|
||||
data_handle = igvm_get_header_data(ctx->cfg->file,
|
||||
IGVM_HEADER_SECTION_DIRECTIVE,
|
||||
data_handle = igvm_get_header_data(ctx->file, IGVM_HEADER_SECTION_DIRECTIVE,
|
||||
ctx->current_header_index);
|
||||
if (data_handle < 0) {
|
||||
error_setg(errp, "Invalid VP context in IGVM file. Error code: %X",
|
||||
|
|
@ -491,7 +482,7 @@ static int qigvm_directive_vp_context(QIgvm *ctx, const uint8_t *header_data,
|
|||
return -1;
|
||||
}
|
||||
|
||||
data = (uint8_t *)igvm_get_buffer(ctx->cfg->file, data_handle);
|
||||
data = (uint8_t *)igvm_get_buffer(ctx->file, data_handle);
|
||||
if (data == NULL) {
|
||||
error_setg(errp, "IGVM: No buffer for handle %d", data_handle);
|
||||
result = -1;
|
||||
|
|
@ -500,8 +491,7 @@ static int qigvm_directive_vp_context(QIgvm *ctx, const uint8_t *header_data,
|
|||
|
||||
if (ctx->machine_state->cgs) {
|
||||
result = ctx->cgsc->set_guest_state(
|
||||
vp_context->gpa, data,
|
||||
igvm_get_buffer_size(ctx->cfg->file, data_handle),
|
||||
vp_context->gpa, data, igvm_get_buffer_size(ctx->file, data_handle),
|
||||
CGS_PAGE_TYPE_VMSA, vp_context->vp_index, errp);
|
||||
} else if (target_arch() == SYS_EMU_TARGET_X86_64) {
|
||||
result = qigvm_x86_set_vp_context(data, vp_context->vp_index, errp);
|
||||
|
|
@ -514,7 +504,7 @@ static int qigvm_directive_vp_context(QIgvm *ctx, const uint8_t *header_data,
|
|||
}
|
||||
|
||||
exit:
|
||||
igvm_free_buffer(ctx->cfg->file, data_handle);
|
||||
igvm_free_buffer(ctx->file, data_handle);
|
||||
if (result < 0) {
|
||||
return result;
|
||||
}
|
||||
|
|
@ -873,8 +863,7 @@ static int qigvm_supported_platform_compat_mask(QIgvm *ctx, Error **errp)
|
|||
uint32_t compatibility_mask_sev_snp = 0;
|
||||
uint32_t compatibility_mask = 0;
|
||||
|
||||
header_count = igvm_header_count(ctx->cfg->file,
|
||||
IGVM_HEADER_SECTION_PLATFORM);
|
||||
header_count = igvm_header_count(ctx->file, IGVM_HEADER_SECTION_PLATFORM);
|
||||
if (header_count < 0) {
|
||||
error_setg(errp,
|
||||
"Invalid platform header count in IGVM file. Error code: %X",
|
||||
|
|
@ -885,11 +874,11 @@ static int qigvm_supported_platform_compat_mask(QIgvm *ctx, Error **errp)
|
|||
for (header_index = 0; header_index < (unsigned)header_count;
|
||||
header_index++) {
|
||||
IgvmVariableHeaderType typ = igvm_get_header_type(
|
||||
ctx->cfg->file, IGVM_HEADER_SECTION_PLATFORM, header_index);
|
||||
ctx->file, IGVM_HEADER_SECTION_PLATFORM, header_index);
|
||||
typ = igvm_vht_type(typ);
|
||||
if (typ == IGVM_VHT_SUPPORTED_PLATFORM) {
|
||||
header_handle = igvm_get_header(
|
||||
ctx->cfg->file, IGVM_HEADER_SECTION_PLATFORM, header_index);
|
||||
ctx->file, IGVM_HEADER_SECTION_PLATFORM, header_index);
|
||||
if (header_handle < 0) {
|
||||
error_setg(errp,
|
||||
"Invalid platform header in IGVM file. "
|
||||
|
|
@ -898,11 +887,11 @@ static int qigvm_supported_platform_compat_mask(QIgvm *ctx, Error **errp)
|
|||
return -1;
|
||||
}
|
||||
platform =
|
||||
(IGVM_VHS_SUPPORTED_PLATFORM *)(igvm_get_buffer(ctx->cfg->file,
|
||||
(IGVM_VHS_SUPPORTED_PLATFORM *)(igvm_get_buffer(ctx->file,
|
||||
header_handle));
|
||||
if (platform == NULL) {
|
||||
error_setg(errp, "IGVM: No buffer for handle %d", header_handle);
|
||||
igvm_free_buffer(ctx->cfg->file, header_handle);
|
||||
igvm_free_buffer(ctx->file, header_handle);
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
@ -933,7 +922,7 @@ static int qigvm_supported_platform_compat_mask(QIgvm *ctx, Error **errp)
|
|||
} else if (platform->platform_type == IGVM_PLATFORM_TYPE_NATIVE) {
|
||||
compatibility_mask = platform->compatibility_mask;
|
||||
}
|
||||
igvm_free_buffer(ctx->cfg->file, header_handle);
|
||||
igvm_free_buffer(ctx->file, header_handle);
|
||||
}
|
||||
}
|
||||
/* Choose the strongest supported isolation technology */
|
||||
|
|
@ -1010,7 +999,7 @@ int qigvm_process_file(IgvmCfg *cfg, MachineState *machine_state,
|
|||
error_setg(errp, "No IGVM file loaded.");
|
||||
return -1;
|
||||
}
|
||||
ctx.cfg = cfg;
|
||||
ctx.file = cfg->file;
|
||||
trace_igvm_process_file(cfg->file, onlyVpContext);
|
||||
|
||||
ctx.machine_state = machine_state;
|
||||
|
|
@ -1032,8 +1021,7 @@ int qigvm_process_file(IgvmCfg *cfg, MachineState *machine_state,
|
|||
goto cleanup;
|
||||
}
|
||||
|
||||
header_count = igvm_header_count(ctx.cfg->file,
|
||||
IGVM_HEADER_SECTION_DIRECTIVE);
|
||||
header_count = igvm_header_count(ctx.file, IGVM_HEADER_SECTION_DIRECTIVE);
|
||||
if (header_count <= 0) {
|
||||
error_setg(
|
||||
errp, "Invalid directive header count in IGVM file. Error code: %X",
|
||||
|
|
@ -1047,8 +1035,7 @@ int qigvm_process_file(IgvmCfg *cfg, MachineState *machine_state,
|
|||
ctx.current_header_index < (unsigned)header_count;
|
||||
ctx.current_header_index++) {
|
||||
IgvmVariableHeaderType raw_type = igvm_get_header_type(
|
||||
ctx.cfg->file, IGVM_HEADER_SECTION_DIRECTIVE,
|
||||
ctx.current_header_index);
|
||||
ctx.file, IGVM_HEADER_SECTION_DIRECTIVE, ctx.current_header_index);
|
||||
if (!onlyVpContext || igvm_vht_type(raw_type) == IGVM_VHT_VP_CONTEXT) {
|
||||
if (qigvm_handler(&ctx, raw_type, errp) < 0) {
|
||||
goto cleanup_parameters;
|
||||
|
|
@ -1066,7 +1053,7 @@ int qigvm_process_file(IgvmCfg *cfg, MachineState *machine_state,
|
|||
}
|
||||
|
||||
header_count =
|
||||
igvm_header_count(ctx.cfg->file, IGVM_HEADER_SECTION_INITIALIZATION);
|
||||
igvm_header_count(ctx.file, IGVM_HEADER_SECTION_INITIALIZATION);
|
||||
if (header_count < 0) {
|
||||
error_setg(
|
||||
errp,
|
||||
|
|
@ -1079,8 +1066,7 @@ int qigvm_process_file(IgvmCfg *cfg, MachineState *machine_state,
|
|||
ctx.current_header_index < (unsigned)header_count;
|
||||
ctx.current_header_index++) {
|
||||
IgvmVariableHeaderType type =
|
||||
igvm_get_header_type(ctx.cfg->file,
|
||||
IGVM_HEADER_SECTION_INITIALIZATION,
|
||||
igvm_get_header_type(ctx.file, IGVM_HEADER_SECTION_INITIALIZATION,
|
||||
ctx.current_header_index);
|
||||
if (qigvm_handler(&ctx, type, errp) < 0) {
|
||||
goto cleanup_parameters;
|
||||
|
|
@ -1110,22 +1096,3 @@ cleanup_parameters:
|
|||
cleanup:
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* cleanup any memory regions created by qigvm_prepare_memory()
|
||||
*/
|
||||
void qigvm_cleanup_memory(IgvmCfg *cfg)
|
||||
{
|
||||
IgvmMemoryRegion *imr, *tmp;
|
||||
|
||||
QTAILQ_FOREACH_SAFE(imr, &cfg->memory_regions, next, tmp)
|
||||
{
|
||||
trace_qigvm_cleanup_memory(imr->mr->name);
|
||||
memory_region_del_subregion(get_system_memory(), imr->mr);
|
||||
vmstate_unregister_ram(imr->mr, NULL);
|
||||
QTAILQ_REMOVE(&cfg->memory_regions, imr, next);
|
||||
/* this triggers MemoryRegion cleanup */
|
||||
object_unparent(OBJECT(imr->mr));
|
||||
g_free(imr);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -33,4 +33,3 @@ igvm_reset_hold(int type) "type=%u"
|
|||
igvm_reset_exit(int type) "type=%u"
|
||||
igvm_file_loaded(const char *fn, int32_t handle) "fn=%s, handle=0x%x"
|
||||
igvm_process_file(int32_t handle, bool context_only) "handle=0x%x context-only=%d"
|
||||
qigvm_cleanup_memory(const char* name) "freeing mr %s"
|
||||
|
|
|
|||
|
|
@ -194,8 +194,6 @@ int block_latency_histogram_set(BlockAcctStats *stats, enum BlockAcctType type,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
qemu_mutex_lock(&stats->lock);
|
||||
|
||||
hist->nbins = new_nbins;
|
||||
g_free(hist->boundaries);
|
||||
hist->boundaries = g_new(uint64_t, hist->nbins - 1);
|
||||
|
|
@ -208,8 +206,6 @@ int block_latency_histogram_set(BlockAcctStats *stats, enum BlockAcctType type,
|
|||
g_free(hist->bins);
|
||||
hist->bins = g_new0(uint64_t, hist->nbins);
|
||||
|
||||
qemu_mutex_unlock(&stats->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -217,16 +213,12 @@ void block_latency_histograms_clear(BlockAcctStats *stats)
|
|||
{
|
||||
int i;
|
||||
|
||||
qemu_mutex_lock(&stats->lock);
|
||||
|
||||
for (i = 0; i < BLOCK_MAX_IOTYPE; i++) {
|
||||
BlockLatencyHistogram *hist = &stats->latency_histogram[i];
|
||||
g_free(hist->bins);
|
||||
g_free(hist->boundaries);
|
||||
memset(hist, 0, sizeof(*hist));
|
||||
}
|
||||
|
||||
qemu_mutex_unlock(&stats->lock);
|
||||
}
|
||||
|
||||
static void block_account_one_io(BlockAcctStats *stats, BlockAcctCookie *cookie,
|
||||
|
|
@ -318,9 +310,10 @@ double block_acct_queue_depth(BlockAcctTimedStats *stats,
|
|||
uint64_t sum, elapsed;
|
||||
|
||||
assert(type < BLOCK_MAX_IOTYPE);
|
||||
assert(qemu_mutex_trylock(&stats->stats->lock) == -EBUSY);
|
||||
|
||||
qemu_mutex_lock(&stats->stats->lock);
|
||||
sum = timed_average_sum(&stats->latency[type], &elapsed);
|
||||
qemu_mutex_unlock(&stats->stats->lock);
|
||||
|
||||
return (double) sum / elapsed;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -202,8 +202,7 @@ static int cloop_open(BlockDriverState *bs, QDict *options, int flags,
|
|||
s->current_block = s->n_blocks;
|
||||
|
||||
s->sectors_per_block = s->block_size/512;
|
||||
/* Cast to uint64_t to prevent uint32_t overflow */
|
||||
bs->total_sectors = (uint64_t)s->n_blocks * s->sectors_per_block;
|
||||
bs->total_sectors = s->n_blocks * s->sectors_per_block;
|
||||
qemu_co_mutex_init(&s->lock);
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -612,7 +612,7 @@ uint64_t bdrv_dirty_bitmap_serialization_coverage(int serialized_chunk_size,
|
|||
const BdrvDirtyBitmap *bitmap)
|
||||
{
|
||||
uint64_t granularity = bdrv_dirty_bitmap_granularity(bitmap);
|
||||
uint64_t limit = granularity * ((uint64_t)serialized_chunk_size << 3);
|
||||
uint64_t limit = granularity * (serialized_chunk_size << 3);
|
||||
|
||||
assert(QEMU_IS_ALIGNED(limit,
|
||||
bdrv_dirty_bitmap_serialization_align(bitmap)));
|
||||
|
|
|
|||
36
block/dmg.c
36
block/dmg.c
|
|
@ -312,21 +312,6 @@ static int dmg_read_mish_block(BDRVDMGState *s, DmgHeaderState *ds,
|
|||
goto fail;
|
||||
}
|
||||
|
||||
/*
|
||||
* Uncompressed chunk length must match sector count. Compressed chunks
|
||||
* are validated during dmg_read_chunk() since the uncompressed size is
|
||||
* not known ahead of time.
|
||||
*/
|
||||
if (s->types[i] == UDRW) {
|
||||
if (s->sectorcounts[i] != DIV_ROUND_UP(s->lengths[i], 512)) {
|
||||
error_report("length %" PRIu64 " for chunk %" PRIu32
|
||||
" is inconsistent with sector count %" PRIu64,
|
||||
s->lengths[i], i, s->sectorcounts[i]);
|
||||
ret = -EINVAL;
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
update_max_chunk_size(s, i, &ds->max_compressed_size,
|
||||
&ds->max_sectors_per_chunk);
|
||||
offset += 40;
|
||||
|
|
@ -574,12 +559,6 @@ static int dmg_open(BlockDriverState *bs, QDict *options, int flags,
|
|||
goto fail;
|
||||
}
|
||||
|
||||
/* There must be at least one chunk */
|
||||
if (s->n_chunks == 0) {
|
||||
ret = -EINVAL;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* initialize zlib engine */
|
||||
s->compressed_chunk = qemu_try_blockalign(bs->file->bs,
|
||||
ds.max_compressed_size + 1);
|
||||
|
|
@ -630,10 +609,7 @@ static inline int is_sector_in_chunk(BDRVDMGState *s,
|
|||
static inline uint32_t search_chunk(BDRVDMGState *s, uint64_t sector_num)
|
||||
{
|
||||
/* binary search */
|
||||
uint32_t chunk1 = 0, chunk2 = s->n_chunks - 1, chunk3;
|
||||
if (s->n_chunks == 0) {
|
||||
goto err; /* should never happen */
|
||||
}
|
||||
uint32_t chunk1 = 0, chunk2 = s->n_chunks, chunk3;
|
||||
while (chunk1 <= chunk2) {
|
||||
chunk3 = (chunk1 + chunk2) / 2;
|
||||
if (s->sectors[chunk3] > sector_num) {
|
||||
|
|
@ -737,16 +713,6 @@ dmg_read_chunk(BlockDriverState *bs, uint64_t sector_num)
|
|||
if (ret < 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Zero the unread part of the last sector when chunk length is
|
||||
* unaligned to avoid exposing uninitialized memory. Valid image
|
||||
* files may never hit this case, but cover it to be safe.
|
||||
*/
|
||||
if (s->lengths[chunk] & 511) {
|
||||
size_t trailing_bytes = 512 - (s->lengths[chunk] & 511);
|
||||
memset(s->uncompressed_chunk + s->lengths[chunk], 0, trailing_bytes);
|
||||
}
|
||||
break;
|
||||
case UDZE: /* zeros */
|
||||
case UDIG: /* ignore */
|
||||
|
|
|
|||
|
|
@ -859,18 +859,6 @@ fuse_co_init(FuseExport *exp, struct fuse_init_out *out,
|
|||
uint32_t supported_flags = FUSE_ASYNC_READ | FUSE_ASYNC_DIO;
|
||||
uint32_t flags2 = 0;
|
||||
|
||||
if (!exp->growable) {
|
||||
/*
|
||||
* Back when libfuse was used, it would always set this flag and thus
|
||||
* the kernel did not execute a truncate itself and passed along O_TRUNC
|
||||
* to user space. Continue setting the flag for backwards compatibility
|
||||
* when the export is not growable to avoid issues with O_TRUNC, i.e.
|
||||
* blockdev-based exports running into ENOTSUP and file-based exports
|
||||
* with growable=off to be truncated and then stuck with size 0.
|
||||
*/
|
||||
supported_flags = FUSE_ATOMIC_O_TRUNC;
|
||||
}
|
||||
|
||||
if (in->major != 7) {
|
||||
error_report("FUSE major version mismatch: We have 7, but kernel has %"
|
||||
PRIu32, in->major);
|
||||
|
|
|
|||
|
|
@ -125,17 +125,10 @@ void qmp_block_dirty_bitmap_add(const char *node, const char *name,
|
|||
disabled = false;
|
||||
}
|
||||
|
||||
if (persistent) {
|
||||
if (!bdrv_is_writable(bs)) {
|
||||
error_setg(errp, "Cannot add a persistent bitmap to "
|
||||
"read-only or inactive node '%s'",
|
||||
bdrv_get_node_name(bs));
|
||||
return;
|
||||
}
|
||||
|
||||
if (!bdrv_can_store_new_dirty_bitmap(bs, name, granularity, errp)) {
|
||||
return;
|
||||
}
|
||||
if (persistent &&
|
||||
!bdrv_can_store_new_dirty_bitmap(bs, name, granularity, errp))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
bitmap = bdrv_create_dirty_bitmap(bs, granularity, name, errp);
|
||||
|
|
@ -165,11 +158,11 @@ BdrvDirtyBitmap *block_dirty_bitmap_remove(const char *node, const char *name,
|
|||
return NULL;
|
||||
}
|
||||
|
||||
if (bdrv_dirty_bitmap_check(bitmap, BDRV_BITMAP_BUSY, errp)) {
|
||||
if (bdrv_dirty_bitmap_check(bitmap, BDRV_BITMAP_BUSY | BDRV_BITMAP_RO,
|
||||
errp)) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Dropping a bitmap needs no write access unless it is actually stored. */
|
||||
if (bdrv_dirty_bitmap_get_persistence(bitmap) &&
|
||||
bdrv_remove_persistent_dirty_bitmap(bs, name, errp) < 0)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -535,8 +535,6 @@ static void bdrv_query_blk_stats(BlockDeviceStats *ds, BlockBackend *blk)
|
|||
BlockAcctTimedStats *ts = NULL;
|
||||
BlockLatencyHistogram *hgram;
|
||||
|
||||
qemu_mutex_lock(&stats->lock);
|
||||
|
||||
ds->rd_bytes = stats->nr_bytes[BLOCK_ACCT_READ];
|
||||
ds->wr_bytes = stats->nr_bytes[BLOCK_ACCT_WRITE];
|
||||
ds->zone_append_bytes = stats->nr_bytes[BLOCK_ACCT_ZONE_APPEND];
|
||||
|
|
@ -626,7 +624,6 @@ static void bdrv_query_blk_stats(BlockDeviceStats *ds, BlockBackend *blk)
|
|||
= bdrv_latency_histogram_stats(&hgram[BLOCK_ACCT_ZONE_APPEND]);
|
||||
ds->flush_latency_histogram
|
||||
= bdrv_latency_histogram_stats(&hgram[BLOCK_ACCT_FLUSH]);
|
||||
qemu_mutex_unlock(&stats->lock);
|
||||
}
|
||||
|
||||
static BlockStats * GRAPH_RDLOCK
|
||||
|
|
|
|||
|
|
@ -1487,15 +1487,6 @@ int coroutine_fn qcow2_co_remove_persistent_dirty_bitmap(BlockDriverState *bs,
|
|||
goto out;
|
||||
}
|
||||
|
||||
if (!can_write(bs)) {
|
||||
error_setg(errp, "Cannot remove persistent bitmap '%s': "
|
||||
"no write access to node '%s'", name,
|
||||
bdrv_get_node_name(bs));
|
||||
ret = -EACCES;
|
||||
bm = NULL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
QSIMPLEQ_REMOVE(bm_list, bm, Qcow2Bitmap, entry);
|
||||
|
||||
ret = update_ext_header_and_dir(bs, bm_list);
|
||||
|
|
|
|||
|
|
@ -2870,11 +2870,7 @@ static int GRAPH_RDLOCK qcow2_inactivate(BlockDriverState *bs)
|
|||
strerror(-ret));
|
||||
}
|
||||
|
||||
/*
|
||||
* A read-only node cannot resolve an inherited dirty bit here;
|
||||
* leave it dirty, same as plain read access already does.
|
||||
*/
|
||||
if (result == 0 && !bdrv_is_read_only(bs)) {
|
||||
if (result == 0) {
|
||||
qcow2_mark_clean(bs);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1128,6 +1128,11 @@ static void qemu_chr_socket_connected(QIOTask *task, void *opaque)
|
|||
|
||||
if (qio_task_propagate_error(task, &err)) {
|
||||
tcp_chr_change_state(s, TCP_CHARDEV_STATE_DISCONNECTED);
|
||||
if (s->registered_yank) {
|
||||
yank_unregister_function(CHARDEV_YANK_INSTANCE(chr->label),
|
||||
char_socket_yank_iochannel,
|
||||
QIO_CHANNEL(sioc));
|
||||
}
|
||||
check_report_connect_error(chr, err);
|
||||
goto cleanup;
|
||||
}
|
||||
|
|
|
|||
7
configure
vendored
7
configure
vendored
|
|
@ -1166,12 +1166,12 @@ fi
|
|||
# detect rust triple
|
||||
|
||||
meson_version=$($meson --version)
|
||||
if test "$rust" != disabled && ! version_ge "$meson_version" 1.12.0; then
|
||||
if test "$rust" != disabled && ! version_ge "$meson_version" 1.10.0; then
|
||||
if test "$rust" = enabled; then
|
||||
$mkvenv ensuregroup --dir "${source_path}/python/wheels" \
|
||||
${source_path}/pythondeps.toml meson-rust || exit 1
|
||||
else
|
||||
echo "Rust needs Meson 1.12.0, disabling" 2>&1
|
||||
echo "Rust needs Meson 1.10.0, disabling" 2>&1
|
||||
rust=disabled
|
||||
fi
|
||||
fi
|
||||
|
|
@ -1740,6 +1740,9 @@ if test "$container_command" != ""; then
|
|||
echo "CONTAINER_COMMAND=$container_command" >> $config_host_mak
|
||||
fi
|
||||
echo "SUBDIRS=$subdirs" >> $config_host_mak
|
||||
if test "$rust" != disabled; then
|
||||
echo "RUST_TARGET_TRIPLE=$rust_target_triple" >> $config_host_mak
|
||||
fi
|
||||
echo "PYTHON=$python" >> $config_host_mak
|
||||
echo "MKVENV_ENSUREGROUP=$mkvenv ensuregroup $mkvenv_online_flag" >> $config_host_mak
|
||||
echo "GENISOIMAGE=$genisoimage" >> $config_host_mak
|
||||
|
|
|
|||
|
|
@ -388,13 +388,7 @@ vg_resource_create_2d(VuGpu *g,
|
|||
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER;
|
||||
return;
|
||||
}
|
||||
if (!vugbm_buffer_create(&res->buffer, &g->gdev, c2d.width, c2d.height)) {
|
||||
g_critical("%s: buffer creation failed %d %d %d",
|
||||
__func__, c2d.resource_id, c2d.width, c2d.height);
|
||||
g_free(res);
|
||||
cmd->error = VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY;
|
||||
return;
|
||||
}
|
||||
vugbm_buffer_create(&res->buffer, &g->gdev, c2d.width, c2d.height);
|
||||
res->image = pixman_image_create_bits(pformat,
|
||||
c2d.width,
|
||||
c2d.height,
|
||||
|
|
@ -487,7 +481,7 @@ vg_create_mapping_iov(VuGpu *g,
|
|||
struct virtio_gpu_ctrl_command *cmd,
|
||||
struct iovec **iov)
|
||||
{
|
||||
g_autofree struct virtio_gpu_mem_entry *ents = NULL;
|
||||
struct virtio_gpu_mem_entry *ents;
|
||||
size_t esize, s;
|
||||
int i;
|
||||
|
||||
|
|
@ -498,22 +492,17 @@ vg_create_mapping_iov(VuGpu *g,
|
|||
}
|
||||
|
||||
esize = sizeof(*ents) * ab->nr_entries;
|
||||
ents = g_try_malloc(esize);
|
||||
if (!ents && esize) {
|
||||
return -1;
|
||||
}
|
||||
ents = g_malloc(esize);
|
||||
s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
|
||||
sizeof(*ab), ents, esize);
|
||||
if (s != esize) {
|
||||
g_critical("%s: command data size incorrect %zu vs %zu",
|
||||
__func__, s, esize);
|
||||
g_free(ents);
|
||||
return -1;
|
||||
}
|
||||
|
||||
*iov = g_try_new0(struct iovec, ab->nr_entries);
|
||||
if (!*iov && ab->nr_entries) {
|
||||
return -1;
|
||||
}
|
||||
*iov = g_new0(struct iovec, ab->nr_entries);
|
||||
for (i = 0; i < ab->nr_entries; i++) {
|
||||
uint64_t len = ents[i].length;
|
||||
(*iov)[i].iov_len = ents[i].length;
|
||||
|
|
@ -522,10 +511,12 @@ vg_create_mapping_iov(VuGpu *g,
|
|||
g_critical("%s: resource %d element %d",
|
||||
__func__, ab->resource_id, i);
|
||||
g_free(*iov);
|
||||
g_free(ents);
|
||||
*iov = NULL;
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
g_free(ents);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -831,14 +822,8 @@ vg_resource_flush(VuGpu *g,
|
|||
PIXMAN_FORMAT_BPP(pixman_image_get_format(res->image)) / 8;
|
||||
size_t size = width * height * bpp;
|
||||
|
||||
void *p = g_try_malloc(VHOST_USER_GPU_HDR_SIZE +
|
||||
sizeof(VhostUserGpuUpdate) + size);
|
||||
if (!p) {
|
||||
pixman_region_fini(®ion);
|
||||
pixman_region_fini(&finalregion);
|
||||
cmd->error = VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY;
|
||||
break;
|
||||
}
|
||||
void *p = g_malloc(VHOST_USER_GPU_HDR_SIZE +
|
||||
sizeof(VhostUserGpuUpdate) + size);
|
||||
VhostUserGpuMsg *msg = p;
|
||||
msg->request = VHOST_USER_GPU_UPDATE;
|
||||
msg->size = sizeof(VhostUserGpuUpdate) + size;
|
||||
|
|
@ -939,19 +924,16 @@ vg_handle_ctrl(VuDev *dev, int qidx)
|
|||
if (len != sizeof(cmd->cmd_hdr)) {
|
||||
g_warning("%s: command size incorrect %zu vs %zu\n",
|
||||
__func__, len, sizeof(cmd->cmd_hdr));
|
||||
memset(&cmd->cmd_hdr, 0, sizeof(cmd->cmd_hdr));
|
||||
vg_ctrl_response_nodata(
|
||||
vg, cmd, VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER);
|
||||
} else {
|
||||
virtio_gpu_ctrl_hdr_bswap(&cmd->cmd_hdr);
|
||||
g_debug("%d %s\n", cmd->cmd_hdr.type,
|
||||
vg_cmd_to_string(cmd->cmd_hdr.type));
|
||||
}
|
||||
|
||||
if (vg->virgl) {
|
||||
vg_virgl_process_cmd(vg, cmd);
|
||||
} else {
|
||||
vg_process_cmd(vg, cmd);
|
||||
}
|
||||
virtio_gpu_ctrl_hdr_bswap(&cmd->cmd_hdr);
|
||||
g_debug("%d %s\n", cmd->cmd_hdr.type,
|
||||
vg_cmd_to_string(cmd->cmd_hdr.type));
|
||||
|
||||
if (vg->virgl) {
|
||||
vg_virgl_process_cmd(vg, cmd);
|
||||
} else {
|
||||
vg_process_cmd(vg, cmd);
|
||||
}
|
||||
|
||||
if (cmd->state != VG_CMD_STATE_FINISHED) {
|
||||
|
|
|
|||
|
|
@ -209,11 +209,7 @@ virgl_cmd_submit_3d(VuGpu *g,
|
|||
return;
|
||||
}
|
||||
|
||||
buf = g_try_malloc(cs.size);
|
||||
if (!buf && cs.size) {
|
||||
cmd->error = VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY;
|
||||
return;
|
||||
}
|
||||
buf = g_malloc(cs.size);
|
||||
s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num,
|
||||
sizeof(cs), buf, cs.size);
|
||||
if (s != cs.size) {
|
||||
|
|
|
|||
|
|
@ -13,10 +13,7 @@
|
|||
static bool
|
||||
mem_alloc_bo(struct vugbm_buffer *buf)
|
||||
{
|
||||
buf->mmap = g_try_malloc((uint64_t)buf->width * buf->height * 4);
|
||||
if (!buf->mmap && buf->width && buf->height) {
|
||||
return false;
|
||||
}
|
||||
buf->mmap = g_malloc(buf->width * buf->height * 4);
|
||||
buf->stride = buf->width * 4;
|
||||
return true;
|
||||
}
|
||||
|
|
@ -56,8 +53,7 @@ struct udmabuf_create {
|
|||
static size_t
|
||||
udmabuf_get_size(struct vugbm_buffer *buf)
|
||||
{
|
||||
return ROUND_UP((uint64_t)buf->width * buf->height * 4,
|
||||
qemu_real_host_page_size());
|
||||
return ROUND_UP(buf->width * buf->height * 4, qemu_real_host_page_size());
|
||||
}
|
||||
|
||||
static bool
|
||||
|
|
@ -297,12 +293,6 @@ bool
|
|||
vugbm_buffer_create(struct vugbm_buffer *buffer, struct vugbm_device *dev,
|
||||
uint32_t width, uint32_t height)
|
||||
{
|
||||
uint64_t size = (uint64_t)width * height * 4;
|
||||
if (size > UINT32_MAX) {
|
||||
g_warning("buffer dimensions too large: %ux%u", width, height);
|
||||
return false;
|
||||
}
|
||||
|
||||
buffer->dev = dev;
|
||||
buffer->width = width;
|
||||
buffer->height = height;
|
||||
|
|
|
|||
|
|
@ -179,7 +179,6 @@ struct virtio_gpu_ctrl_command {
|
|||
if (vugpufillcmd_s_ != sizeof(out)) { \
|
||||
g_critical("%s: command size incorrect %zu vs %zu", \
|
||||
__func__, vugpufillcmd_s_, sizeof(out)); \
|
||||
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER; \
|
||||
return; \
|
||||
} \
|
||||
} while (0)
|
||||
|
|
|
|||
|
|
@ -65,8 +65,6 @@ static int qcrypto_cipher_mode_to_gcry_mode(QCryptoCipherMode mode)
|
|||
return GCRY_CIPHER_MODE_CBC;
|
||||
case QCRYPTO_CIPHER_MODE_CTR:
|
||||
return GCRY_CIPHER_MODE_CTR;
|
||||
case QCRYPTO_CIPHER_MODE_GCM:
|
||||
return GCRY_CIPHER_MODE_GCM;
|
||||
default:
|
||||
return GCRY_CIPHER_MODE_NONE;
|
||||
}
|
||||
|
|
@ -106,10 +104,6 @@ bool qcrypto_cipher_supports(QCryptoCipherAlgo alg,
|
|||
case QCRYPTO_CIPHER_MODE_XTS:
|
||||
case QCRYPTO_CIPHER_MODE_CTR:
|
||||
return true;
|
||||
case QCRYPTO_CIPHER_MODE_GCM:
|
||||
/* GCM requires a 128-bit block cipher. */
|
||||
return gcry_cipher_get_algo_blklen(
|
||||
qcrypto_cipher_alg_to_gcry_alg(alg)) == 16;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
|
@ -234,99 +228,6 @@ static const struct QCryptoCipherDriver qcrypto_gcrypt_ctr_driver = {
|
|||
.cipher_free = qcrypto_gcrypt_ctx_free,
|
||||
};
|
||||
|
||||
/*
|
||||
* GCM is an AEAD stream mode: the IV/nonce need not match the block size,
|
||||
* the message length need not be a multiple of the block size, associated
|
||||
* data is fed with gcry_cipher_authenticate() and the authentication tag is
|
||||
* read back with gcry_cipher_gettag().
|
||||
*/
|
||||
static int qcrypto_gcrypt_gcm_setiv(QCryptoCipher *cipher,
|
||||
const uint8_t *iv, size_t niv,
|
||||
Error **errp)
|
||||
{
|
||||
QCryptoCipherGcrypt *ctx = container_of(cipher, QCryptoCipherGcrypt, base);
|
||||
gcry_error_t err;
|
||||
|
||||
gcry_cipher_reset(ctx->handle);
|
||||
err = gcry_cipher_setiv(ctx->handle, iv, niv);
|
||||
if (err != 0) {
|
||||
error_setg(errp, "Cannot set IV: %s", gcry_strerror(err));
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcrypto_gcrypt_gcm_setaad(QCryptoCipher *cipher,
|
||||
const uint8_t *aad, size_t len,
|
||||
Error **errp)
|
||||
{
|
||||
QCryptoCipherGcrypt *ctx = container_of(cipher, QCryptoCipherGcrypt, base);
|
||||
gcry_error_t err;
|
||||
|
||||
err = gcry_cipher_authenticate(ctx->handle, aad, len);
|
||||
if (err != 0) {
|
||||
error_setg(errp, "Cannot set AAD: %s", gcry_strerror(err));
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcrypto_gcrypt_gcm_encrypt(QCryptoCipher *cipher, const void *in,
|
||||
void *out, size_t len, Error **errp)
|
||||
{
|
||||
QCryptoCipherGcrypt *ctx = container_of(cipher, QCryptoCipherGcrypt, base);
|
||||
gcry_error_t err;
|
||||
|
||||
err = gcry_cipher_encrypt(ctx->handle, out, len, in, len);
|
||||
if (err != 0) {
|
||||
error_setg(errp, "Cannot encrypt data: %s", gcry_strerror(err));
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcrypto_gcrypt_gcm_decrypt(QCryptoCipher *cipher, const void *in,
|
||||
void *out, size_t len, Error **errp)
|
||||
{
|
||||
QCryptoCipherGcrypt *ctx = container_of(cipher, QCryptoCipherGcrypt, base);
|
||||
gcry_error_t err;
|
||||
|
||||
err = gcry_cipher_decrypt(ctx->handle, out, len, in, len);
|
||||
if (err != 0) {
|
||||
error_setg(errp, "Cannot decrypt data: %s", gcry_strerror(err));
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcrypto_gcrypt_gcm_gettag(QCryptoCipher *cipher,
|
||||
uint8_t *tag, size_t len, Error **errp)
|
||||
{
|
||||
QCryptoCipherGcrypt *ctx = container_of(cipher, QCryptoCipherGcrypt, base);
|
||||
gcry_error_t err;
|
||||
|
||||
err = gcry_cipher_gettag(ctx->handle, tag, len);
|
||||
if (err != 0) {
|
||||
error_setg(errp, "Cannot get tag: %s", gcry_strerror(err));
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct QCryptoCipherDriver qcrypto_gcrypt_gcm_driver = {
|
||||
.cipher_encrypt = qcrypto_gcrypt_gcm_encrypt,
|
||||
.cipher_decrypt = qcrypto_gcrypt_gcm_decrypt,
|
||||
.cipher_setiv = qcrypto_gcrypt_gcm_setiv,
|
||||
.cipher_setaad = qcrypto_gcrypt_gcm_setaad,
|
||||
.cipher_gettag = qcrypto_gcrypt_gcm_gettag,
|
||||
.cipher_free = qcrypto_gcrypt_ctx_free,
|
||||
};
|
||||
|
||||
static QCryptoCipher *qcrypto_cipher_ctx_new(QCryptoCipherAlgo alg,
|
||||
QCryptoCipherMode mode,
|
||||
const uint8_t *key,
|
||||
|
|
@ -358,8 +259,6 @@ static QCryptoCipher *qcrypto_cipher_ctx_new(QCryptoCipherAlgo alg,
|
|||
|
||||
if (mode == QCRYPTO_CIPHER_MODE_CTR) {
|
||||
drv = &qcrypto_gcrypt_ctr_driver;
|
||||
} else if (mode == QCRYPTO_CIPHER_MODE_GCM) {
|
||||
drv = &qcrypto_gcrypt_gcm_driver;
|
||||
} else {
|
||||
drv = &qcrypto_gcrypt_driver;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -48,15 +48,6 @@ bool qcrypto_cipher_supports(QCryptoCipherAlgo alg,
|
|||
default:
|
||||
return false;
|
||||
}
|
||||
case QCRYPTO_CIPHER_MODE_GCM:
|
||||
switch (alg) {
|
||||
case QCRYPTO_CIPHER_ALGO_AES_128:
|
||||
case QCRYPTO_CIPHER_ALGO_AES_192:
|
||||
case QCRYPTO_CIPHER_ALGO_AES_256:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
|
@ -232,147 +223,6 @@ static struct QCryptoCipherDriver gnutls_driver = {
|
|||
.cipher_free = qcrypto_gnutls_cipher_free,
|
||||
};
|
||||
|
||||
/*
|
||||
* GCM is an AEAD stream mode: the nonce need not match the block size, the
|
||||
* message length need not be a multiple of the block size, associated data is
|
||||
* fed with gnutls_cipher_add_auth() and the authentication tag is read back
|
||||
* with gnutls_cipher_tag().
|
||||
*/
|
||||
static int
|
||||
qcrypto_gnutls_cipher_encrypt_gcm(QCryptoCipher *cipher,
|
||||
const void *in, void *out,
|
||||
size_t len, Error **errp)
|
||||
{
|
||||
QCryptoCipherGnutls *ctx = container_of(cipher, QCryptoCipherGnutls, base);
|
||||
int err;
|
||||
|
||||
err = gnutls_cipher_encrypt2(ctx->handle, in, len, out, len);
|
||||
if (err != 0) {
|
||||
error_setg(errp, "Cannot encrypt data: %s", gnutls_strerror(err));
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
qcrypto_gnutls_cipher_decrypt_gcm(QCryptoCipher *cipher,
|
||||
const void *in, void *out,
|
||||
size_t len, Error **errp)
|
||||
{
|
||||
QCryptoCipherGnutls *ctx = container_of(cipher, QCryptoCipherGnutls, base);
|
||||
int err;
|
||||
|
||||
err = gnutls_cipher_decrypt2(ctx->handle, in, len, out, len);
|
||||
if (err != 0) {
|
||||
error_setg(errp, "Cannot decrypt data: %s", gnutls_strerror(err));
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
qcrypto_gnutls_cipher_setiv_gcm(QCryptoCipher *cipher,
|
||||
const uint8_t *iv, size_t niv,
|
||||
Error **errp)
|
||||
{
|
||||
QCryptoCipherGnutls *ctx = container_of(cipher, QCryptoCipherGnutls, base);
|
||||
|
||||
gnutls_cipher_set_iv(ctx->handle, (void *)iv, niv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
qcrypto_gnutls_cipher_setaad_gcm(QCryptoCipher *cipher,
|
||||
const uint8_t *aad, size_t len,
|
||||
Error **errp)
|
||||
{
|
||||
QCryptoCipherGnutls *ctx = container_of(cipher, QCryptoCipherGnutls, base);
|
||||
int err;
|
||||
|
||||
err = gnutls_cipher_add_auth(ctx->handle, aad, len);
|
||||
if (err != 0) {
|
||||
error_setg(errp, "Cannot add associated data: %s",
|
||||
gnutls_strerror(err));
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
qcrypto_gnutls_cipher_gettag_gcm(QCryptoCipher *cipher,
|
||||
uint8_t *tag, size_t len,
|
||||
Error **errp)
|
||||
{
|
||||
QCryptoCipherGnutls *ctx = container_of(cipher, QCryptoCipherGnutls, base);
|
||||
int err;
|
||||
|
||||
err = gnutls_cipher_tag(ctx->handle, tag, len);
|
||||
if (err != 0) {
|
||||
error_setg(errp, "Cannot get authentication tag: %s",
|
||||
gnutls_strerror(err));
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct QCryptoCipherDriver gnutls_gcm_driver = {
|
||||
.cipher_encrypt = qcrypto_gnutls_cipher_encrypt_gcm,
|
||||
.cipher_decrypt = qcrypto_gnutls_cipher_decrypt_gcm,
|
||||
.cipher_setiv = qcrypto_gnutls_cipher_setiv_gcm,
|
||||
.cipher_setaad = qcrypto_gnutls_cipher_setaad_gcm,
|
||||
.cipher_gettag = qcrypto_gnutls_cipher_gettag_gcm,
|
||||
.cipher_free = qcrypto_gnutls_cipher_free,
|
||||
};
|
||||
|
||||
static QCryptoCipher *
|
||||
qcrypto_gnutls_aes_gcm_ctx_new(QCryptoCipherAlgo alg, const uint8_t *key,
|
||||
size_t nkey, Error **errp)
|
||||
{
|
||||
gnutls_datum_t gkey = { (unsigned char *)key, nkey };
|
||||
gnutls_cipher_algorithm_t galg = GNUTLS_CIPHER_UNKNOWN;
|
||||
QCryptoCipherGnutls *ctx;
|
||||
int err;
|
||||
|
||||
switch (alg) {
|
||||
case QCRYPTO_CIPHER_ALGO_AES_128:
|
||||
galg = GNUTLS_CIPHER_AES_128_GCM;
|
||||
break;
|
||||
case QCRYPTO_CIPHER_ALGO_AES_192:
|
||||
galg = GNUTLS_CIPHER_AES_192_GCM;
|
||||
break;
|
||||
case QCRYPTO_CIPHER_ALGO_AES_256:
|
||||
galg = GNUTLS_CIPHER_AES_256_GCM;
|
||||
break;
|
||||
default:
|
||||
error_setg(errp, "Unsupported cipher algorithm %s with GCM mode",
|
||||
QCryptoCipherAlgo_str(alg));
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (!qcrypto_cipher_validate_key_length(alg, QCRYPTO_CIPHER_MODE_GCM,
|
||||
nkey, errp)) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
ctx = g_new0(QCryptoCipherGnutls, 1);
|
||||
ctx->base.driver = &gnutls_gcm_driver;
|
||||
ctx->blocksize = 16;
|
||||
|
||||
err = gnutls_cipher_init(&ctx->handle, galg, &gkey, NULL);
|
||||
if (err != 0) {
|
||||
error_setg(errp, "Cannot initialize cipher: %s", gnutls_strerror(err));
|
||||
g_free(ctx);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return &ctx->base;
|
||||
}
|
||||
|
||||
static QCryptoCipher *qcrypto_cipher_ctx_new(QCryptoCipherAlgo alg,
|
||||
QCryptoCipherMode mode,
|
||||
const uint8_t *key,
|
||||
|
|
@ -384,10 +234,6 @@ static QCryptoCipher *qcrypto_cipher_ctx_new(QCryptoCipherAlgo alg,
|
|||
gnutls_cipher_algorithm_t galg = GNUTLS_CIPHER_UNKNOWN;
|
||||
int err;
|
||||
|
||||
if (mode == QCRYPTO_CIPHER_MODE_GCM) {
|
||||
return qcrypto_gnutls_aes_gcm_ctx_new(alg, key, nkey, errp);
|
||||
}
|
||||
|
||||
switch (mode) {
|
||||
case QCRYPTO_CIPHER_MODE_XTS:
|
||||
switch (alg) {
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@
|
|||
#include <nettle/twofish.h>
|
||||
#include <nettle/ctr.h>
|
||||
#include <nettle/xts.h>
|
||||
#include <nettle/gcm.h>
|
||||
#ifdef CONFIG_CRYPTO_SM4
|
||||
#include <nettle/sm4.h>
|
||||
#endif
|
||||
|
|
@ -411,125 +410,6 @@ DEFINE_ECB(qcrypto_nettle_sm4,
|
|||
sm4_encrypt_native, sm4_decrypt_native)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* GCM is an AEAD mode built on AES (128-bit block only). Drive it through the
|
||||
* generic gcm_* interface, using the block cipher's encrypt function for both
|
||||
* directions; associated data is fed with gcm_update() and the authentication
|
||||
* tag is produced by gcm_digest().
|
||||
*/
|
||||
typedef struct QCryptoNettleAESGCM {
|
||||
QCryptoCipher base;
|
||||
struct gcm_key gcm_key;
|
||||
struct gcm_ctx gcm_ctx;
|
||||
union {
|
||||
struct aes128_ctx aes128;
|
||||
struct aes192_ctx aes192;
|
||||
struct aes256_ctx aes256;
|
||||
} cipher;
|
||||
nettle_cipher_func *encrypt;
|
||||
} QCryptoNettleAESGCM;
|
||||
|
||||
static int qcrypto_nettle_aes_gcm_setiv(QCryptoCipher *cipher,
|
||||
const uint8_t *iv, size_t niv,
|
||||
Error **errp)
|
||||
{
|
||||
QCryptoNettleAESGCM *ctx = container_of(cipher, QCryptoNettleAESGCM, base);
|
||||
|
||||
gcm_set_iv(&ctx->gcm_ctx, &ctx->gcm_key, niv, iv);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcrypto_nettle_aes_gcm_setaad(QCryptoCipher *cipher,
|
||||
const uint8_t *aad, size_t len,
|
||||
Error **errp)
|
||||
{
|
||||
QCryptoNettleAESGCM *ctx = container_of(cipher, QCryptoNettleAESGCM, base);
|
||||
|
||||
gcm_update(&ctx->gcm_ctx, &ctx->gcm_key, len, aad);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcrypto_nettle_aes_gcm_encrypt(QCryptoCipher *cipher,
|
||||
const void *in, void *out,
|
||||
size_t len, Error **errp)
|
||||
{
|
||||
QCryptoNettleAESGCM *ctx = container_of(cipher, QCryptoNettleAESGCM, base);
|
||||
|
||||
gcm_encrypt(&ctx->gcm_ctx, &ctx->gcm_key, &ctx->cipher, ctx->encrypt,
|
||||
len, out, in);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcrypto_nettle_aes_gcm_decrypt(QCryptoCipher *cipher,
|
||||
const void *in, void *out,
|
||||
size_t len, Error **errp)
|
||||
{
|
||||
QCryptoNettleAESGCM *ctx = container_of(cipher, QCryptoNettleAESGCM, base);
|
||||
|
||||
gcm_decrypt(&ctx->gcm_ctx, &ctx->gcm_key, &ctx->cipher, ctx->encrypt,
|
||||
len, out, in);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcrypto_nettle_aes_gcm_gettag(QCryptoCipher *cipher,
|
||||
uint8_t *tag, size_t len,
|
||||
Error **errp)
|
||||
{
|
||||
QCryptoNettleAESGCM *ctx = container_of(cipher, QCryptoNettleAESGCM, base);
|
||||
|
||||
gcm_digest(&ctx->gcm_ctx, &ctx->gcm_key, &ctx->cipher, ctx->encrypt,
|
||||
len, tag);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct QCryptoCipherDriver qcrypto_nettle_aes_gcm_driver = {
|
||||
.cipher_encrypt = qcrypto_nettle_aes_gcm_encrypt,
|
||||
.cipher_decrypt = qcrypto_nettle_aes_gcm_decrypt,
|
||||
.cipher_setiv = qcrypto_nettle_aes_gcm_setiv,
|
||||
.cipher_setaad = qcrypto_nettle_aes_gcm_setaad,
|
||||
.cipher_gettag = qcrypto_nettle_aes_gcm_gettag,
|
||||
.cipher_free = qcrypto_cipher_ctx_free,
|
||||
};
|
||||
|
||||
static QCryptoCipher *qcrypto_nettle_aes_gcm_ctx_new(QCryptoCipherAlgo alg,
|
||||
const uint8_t *key,
|
||||
size_t nkey,
|
||||
Error **errp)
|
||||
{
|
||||
QCryptoNettleAESGCM *ctx;
|
||||
|
||||
if (!qcrypto_cipher_validate_key_length(alg, QCRYPTO_CIPHER_MODE_GCM,
|
||||
nkey, errp)) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
ctx = g_new0(QCryptoNettleAESGCM, 1);
|
||||
ctx->base.driver = &qcrypto_nettle_aes_gcm_driver;
|
||||
|
||||
switch (alg) {
|
||||
case QCRYPTO_CIPHER_ALGO_AES_128:
|
||||
aes128_set_encrypt_key(&ctx->cipher.aes128, key);
|
||||
ctx->encrypt = aes128_encrypt_native;
|
||||
break;
|
||||
case QCRYPTO_CIPHER_ALGO_AES_192:
|
||||
aes192_set_encrypt_key(&ctx->cipher.aes192, key);
|
||||
ctx->encrypt = aes192_encrypt_native;
|
||||
break;
|
||||
case QCRYPTO_CIPHER_ALGO_AES_256:
|
||||
aes256_set_encrypt_key(&ctx->cipher.aes256, key);
|
||||
ctx->encrypt = aes256_encrypt_native;
|
||||
break;
|
||||
default:
|
||||
error_setg(errp, "Unsupported cipher algorithm %s with GCM mode",
|
||||
QCryptoCipherAlgo_str(alg));
|
||||
g_free(ctx);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
gcm_set_key(&ctx->gcm_key, &ctx->cipher, ctx->encrypt);
|
||||
return &ctx->base;
|
||||
}
|
||||
|
||||
bool qcrypto_cipher_supports(QCryptoCipherAlgo alg,
|
||||
QCryptoCipherMode mode)
|
||||
{
|
||||
|
|
@ -560,10 +440,6 @@ bool qcrypto_cipher_supports(QCryptoCipherAlgo alg,
|
|||
case QCRYPTO_CIPHER_MODE_XTS:
|
||||
case QCRYPTO_CIPHER_MODE_CTR:
|
||||
return true;
|
||||
case QCRYPTO_CIPHER_MODE_GCM:
|
||||
return alg == QCRYPTO_CIPHER_ALGO_AES_128 ||
|
||||
alg == QCRYPTO_CIPHER_ALGO_AES_192 ||
|
||||
alg == QCRYPTO_CIPHER_ALGO_AES_256;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
|
@ -575,10 +451,6 @@ static QCryptoCipher *qcrypto_cipher_ctx_new(QCryptoCipherAlgo alg,
|
|||
size_t nkey,
|
||||
Error **errp)
|
||||
{
|
||||
if (mode == QCRYPTO_CIPHER_MODE_GCM) {
|
||||
return qcrypto_nettle_aes_gcm_ctx_new(alg, key, nkey, errp);
|
||||
}
|
||||
|
||||
switch (mode) {
|
||||
case QCRYPTO_CIPHER_MODE_ECB:
|
||||
case QCRYPTO_CIPHER_MODE_CBC:
|
||||
|
|
|
|||
|
|
@ -66,7 +66,6 @@ static const bool mode_need_iv[QCRYPTO_CIPHER_MODE__MAX] = {
|
|||
[QCRYPTO_CIPHER_MODE_CBC] = true,
|
||||
[QCRYPTO_CIPHER_MODE_XTS] = true,
|
||||
[QCRYPTO_CIPHER_MODE_CTR] = true,
|
||||
[QCRYPTO_CIPHER_MODE_GCM] = true,
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -205,37 +204,6 @@ int qcrypto_cipher_setiv(QCryptoCipher *cipher,
|
|||
}
|
||||
|
||||
|
||||
int qcrypto_cipher_setaad(QCryptoCipher *cipher,
|
||||
const uint8_t *aad, size_t len,
|
||||
Error **errp)
|
||||
{
|
||||
const QCryptoCipherDriver *drv = cipher->driver;
|
||||
|
||||
if (!drv->cipher_setaad) {
|
||||
error_setg(errp, "The cipher mode does not support associated data");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return drv->cipher_setaad(cipher, aad, len, errp);
|
||||
}
|
||||
|
||||
|
||||
int qcrypto_cipher_gettag(QCryptoCipher *cipher,
|
||||
uint8_t *tag, size_t len,
|
||||
Error **errp)
|
||||
{
|
||||
const QCryptoCipherDriver *drv = cipher->driver;
|
||||
|
||||
if (!drv->cipher_gettag) {
|
||||
error_setg(errp,
|
||||
"The cipher mode does not produce an authentication tag");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return drv->cipher_gettag(cipher, tag, len, errp);
|
||||
}
|
||||
|
||||
|
||||
void qcrypto_cipher_free(QCryptoCipher *cipher)
|
||||
{
|
||||
if (cipher) {
|
||||
|
|
|
|||
|
|
@ -34,14 +34,6 @@ struct QCryptoCipherDriver {
|
|||
const uint8_t *iv, size_t niv,
|
||||
Error **errp);
|
||||
|
||||
int (*cipher_setaad)(QCryptoCipher *cipher,
|
||||
const uint8_t *aad, size_t len,
|
||||
Error **errp);
|
||||
|
||||
int (*cipher_gettag)(QCryptoCipher *cipher,
|
||||
uint8_t *tag, size_t len,
|
||||
Error **errp);
|
||||
|
||||
void (*cipher_free)(QCryptoCipher *cipher);
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -24,8 +24,7 @@
|
|||
#include "crypto/hash.h"
|
||||
#include "hashpriv.h"
|
||||
#include <nettle/md5.h>
|
||||
#include <nettle/sha1.h>
|
||||
#include <nettle/sha2.h>
|
||||
#include <nettle/sha.h>
|
||||
#include <nettle/ripemd160.h>
|
||||
#ifdef CONFIG_CRYPTO_SM3
|
||||
#include <nettle/sm3.h>
|
||||
|
|
|
|||
|
|
@ -49,20 +49,6 @@ static const cs_opt_skipdata cap_skipdata_s390x = {
|
|||
.callback = cap_skipdata_s390x_cb
|
||||
};
|
||||
|
||||
/* Similarly for RISCV */
|
||||
static size_t CAPSTONE_API
|
||||
cap_skipdata_riscv_cb(const uint8_t *code, size_t code_size,
|
||||
size_t offset, void *user_data)
|
||||
{
|
||||
/* See insn_len() from target/riscv/internals.h */
|
||||
return (code[offset] & 3) == 3 ? 4 : 2;
|
||||
}
|
||||
|
||||
static const cs_opt_skipdata cap_skipdata_riscv = {
|
||||
.mnemonic = ".byte",
|
||||
.callback = cap_skipdata_riscv_cb
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize the Capstone library.
|
||||
*
|
||||
|
|
@ -90,12 +76,7 @@ static cs_err cap_disas_start(disassemble_info *info, csh *handle)
|
|||
cs_option(*handle, CS_OPT_SKIPDATA, CS_OPT_ON);
|
||||
|
||||
switch (info->cap_arch) {
|
||||
case CS_ARCH_RISCV:
|
||||
cs_option(*handle, CS_OPT_SKIPDATA_SETUP,
|
||||
(uintptr_t)&cap_skipdata_riscv);
|
||||
break;
|
||||
|
||||
case CS_ARCH_SYSTEMZ:
|
||||
case CS_ARCH_SYSZ:
|
||||
cs_option(*handle, CS_OPT_SKIPDATA_SETUP,
|
||||
(uintptr_t)&cap_skipdata_s390x);
|
||||
break;
|
||||
|
|
@ -126,9 +107,8 @@ static void cap_dump_insn_units(disassemble_info *info, cs_insn *insn,
|
|||
{
|
||||
fprintf_function print = info->fprintf_func;
|
||||
FILE *stream = info->stream;
|
||||
int unit = MIN(info->cap_insn_unit, n - i);
|
||||
|
||||
switch (unit) {
|
||||
switch (info->cap_insn_unit) {
|
||||
case 4:
|
||||
if (info->endian == BFD_ENDIAN_BIG) {
|
||||
for (; i < n; i += 4) {
|
||||
|
|
@ -160,11 +140,6 @@ static void cap_dump_insn_units(disassemble_info *info, cs_insn *insn,
|
|||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (unit < info->cap_insn_unit) {
|
||||
int width = (info->cap_insn_unit - unit) * 2;
|
||||
print(stream, "%*s", width, "");
|
||||
}
|
||||
}
|
||||
|
||||
static void cap_dump_insn(disassemble_info *info, cs_insn *insn)
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
|
||||
int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)
|
||||
{
|
||||
const HexagonCPUDef *hex_def = (const HexagonCPUDef *)info->target_info;
|
||||
uint32_t words[PACKET_WORDS_MAX];
|
||||
bool found_end = false;
|
||||
GString *buf;
|
||||
|
|
@ -57,9 +58,8 @@ int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)
|
|||
return PACKET_WORDS_MAX * sizeof(uint32_t);
|
||||
}
|
||||
|
||||
const HexagonCPUConfig *cfg = info->target_info;
|
||||
buf = g_string_sized_new(PACKET_BUFFER_LEN);
|
||||
len = disassemble_hexagon(words, i, memaddr, buf, cfg);
|
||||
len = disassemble_hexagon(words, i, memaddr, buf, hex_def);
|
||||
(*info->fprintf_func)(info->stream, "%s", buf->str);
|
||||
g_string_free(buf, true);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,913 +0,0 @@
|
|||
OP(add, "add", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(add_uw, "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(addd, "addd", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(addi, "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi)
|
||||
OP(addid, "addid", rv_codec_i, rv_fmt_rd_rs1_imm)
|
||||
OP(addiw, "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw)
|
||||
OP(addw, "addw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(aes32dsi, "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
|
||||
OP(aes32dsmi, "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
|
||||
OP(aes32esi, "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
|
||||
OP(aes32esmi, "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
|
||||
OP(aes64ds, "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(aes64dsm, "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(aes64es, "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(aes64esm, "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(aes64im, "aes64im", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(aes64ks1i, "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum)
|
||||
OP(aes64ks2, "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(amoadd_b, "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoadd_d, "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoadd_h, "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoadd_q, "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoadd_w, "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoand_b, "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoand_d, "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoand_h, "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoand_q, "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoand_w, "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amocas_b, "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amocas_h, "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amocas_w, "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomax_b, "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomax_d, "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomax_h, "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomax_q, "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomax_w, "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomaxu_b, "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomaxu_d, "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomaxu_h, "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomaxu_q, "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomaxu_w, "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomin_b, "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomin_d, "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomin_h, "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomin_q, "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amomin_w, "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amominu_b, "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amominu_d, "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amominu_h, "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amominu_q, "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amominu_w, "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoor_b, "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoor_d, "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoor_h, "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoor_q, "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoor_w, "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoswap_b, "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoswap_d, "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoswap_h, "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoswap_q, "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoswap_w, "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoxor_b, "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoxor_d, "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoxor_h, "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoxor_q, "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(amoxor_w, "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(and, "and", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(andi, "andi", rv_codec_i, rv_fmt_rd_rs1_imm)
|
||||
OP(andn, "andn", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(auipc, "auipc", rv_codec_u, rv_fmt_rd_uoffset)
|
||||
OP(bclr, "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(bclri, "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(beq, "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq)
|
||||
OP(beqz, "beqz", rv_codec_illegal, rv_fmt_rs1_offset)
|
||||
OP(bext, "bext", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(bexti, "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(bge, "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge)
|
||||
OP(bgeu, "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
|
||||
OP(bgez, "bgez", rv_codec_illegal, rv_fmt_rs1_offset)
|
||||
OP(bgtz, "bgtz", rv_codec_illegal, rv_fmt_rs2_offset)
|
||||
OP(binv, "binv", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(binvi, "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(blez, "blez", rv_codec_illegal, rv_fmt_rs2_offset)
|
||||
OP(blt, "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt)
|
||||
OP(bltu, "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset)
|
||||
OP(bltz, "bltz", rv_codec_illegal, rv_fmt_rs1_offset)
|
||||
OP(bne, "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne)
|
||||
OP(bnez, "bnez", rv_codec_illegal, rv_fmt_rs1_offset)
|
||||
OP(brev8, "brev8", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(bset, "bset", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(bseti, "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(c_add, "c.add", rv_codec_cr, NULL, DECOMP(op_add))
|
||||
OP(c_addi, "c.addi", rv_codec_ci, NULL, DECOMP(op_addi))
|
||||
OP(c_addi16sp, "c.addi16sp", rv_codec_ci_16sp, NULL, DECOMP(op_addi))
|
||||
OP(c_addi4spn, "c.addi4spn", rv_codec_ciw_4spn, NULL, DECOMP(op_addi))
|
||||
OP(c_addiw, "c.addiw", rv_codec_ci, NULL, DECOMP(op_addiw))
|
||||
OP(c_addw, "c.addw", rv_codec_cs, NULL, DECOMP(op_addw))
|
||||
OP(c_and, "c.and", rv_codec_cs, NULL, DECOMP(op_and))
|
||||
OP(c_andi, "c.andi", rv_codec_cb_imm, NULL, DECOMP(op_andi))
|
||||
OP(c_beqz, "c.beqz", rv_codec_cb, NULL, DECOMP(op_beqz))
|
||||
OP(c_bnez, "c.bnez", rv_codec_cb, NULL, DECOMP(op_bnez))
|
||||
OP(c_ebreak, "c.ebreak", rv_codec_ci_none, NULL, DECOMP(op_ebreak))
|
||||
OP(c_fld, "c.fld", rv_codec_cl_ld, NULL, DECOMP(op_fld))
|
||||
OP(c_fldsp, "c.fldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_fld))
|
||||
OP(c_flw, "c.flw", rv_codec_cl_lw, NULL, DECOMP(op_flw))
|
||||
OP(c_flwsp, "c.flwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_flw))
|
||||
OP(c_fsd, "c.fsd", rv_codec_cs_sd, NULL, DECOMP(op_fsd))
|
||||
OP(c_fsdsp, "c.fsdsp", rv_codec_css_sdsp, NULL, DECOMP(op_fsd))
|
||||
OP(c_fsw, "c.fsw", rv_codec_cs_sw, NULL, DECOMP(op_fsw))
|
||||
OP(c_fswsp, "c.fswsp", rv_codec_css_swsp, NULL, DECOMP(op_fsw))
|
||||
OP(c_j, "c.j", rv_codec_cj, NULL, DECOMP(op_j))
|
||||
OP(c_jal, "c.jal", rv_codec_cj_jal, NULL, DECOMP(op_jal))
|
||||
OP(c_jalr, "c.jalr", rv_codec_cr_jalr, NULL, DECOMP(op_jalr))
|
||||
OP(c_jr, "c.jr", rv_codec_cr_jr, NULL, DECOMP(op_jr))
|
||||
OP(c_lbu, "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
|
||||
OP(c_ld, "c.ld", rv_codec_cl_ld, NULL, DECOMP(op_ld))
|
||||
OP(c_ldsp, "c.ldsp", rv_codec_ci_ldsp, NULL, DECOMP(op_ld))
|
||||
OP(c_lh, "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
|
||||
OP(c_lhu, "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
|
||||
OP(c_li, "c.li", rv_codec_ci_li, NULL, DECOMP(op_addi))
|
||||
OP(c_lq, "c.lq", rv_codec_cl_lq, NULL, DECOMP(op_lq))
|
||||
OP(c_lqsp, "c.lqsp", rv_codec_ci_lqsp, NULL, DECOMP(op_lq))
|
||||
OP(c_lui, "c.lui", rv_codec_ci_lui, NULL, DECOMP(op_lui))
|
||||
OP(c_lw, "c.lw", rv_codec_cl_lw, NULL, DECOMP(op_lw))
|
||||
OP(c_lwsp, "c.lwsp", rv_codec_ci_lwsp, NULL, DECOMP(op_lw))
|
||||
OP(c_mop, "c.mop", rv_codec_cmop, rv_fmt_cmop)
|
||||
OP(c_mul, "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2)
|
||||
OP(c_mv, "c.mv", rv_codec_cr_mv, NULL, DECOMP(op_mv))
|
||||
OP(c_not, "c.not", rv_codec_zcb_ext, rv_fmt_rd)
|
||||
OP(c_or, "c.or", rv_codec_cs, NULL, DECOMP(op_or))
|
||||
OP(c_sb, "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst)
|
||||
OP(c_sd, "c.sd", rv_codec_cs_sd, NULL, DECOMP(op_sd))
|
||||
OP(c_sdsp, "c.sdsp", rv_codec_css_sdsp, NULL, DECOMP(op_sd))
|
||||
OP(c_sext_b, "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd)
|
||||
OP(c_sext_h, "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd)
|
||||
OP(c_sh, "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst)
|
||||
OP(c_slli, "c.slli", rv_codec_ci_sh6, NULL, DECOMP(op_slli))
|
||||
OP(c_sq, "c.sq", rv_codec_cs_sq, NULL, DECOMP(op_sq))
|
||||
OP(c_sqsp, "c.sqsp", rv_codec_css_sqsp, NULL, DECOMP(op_sq))
|
||||
OP(c_srai, "c.srai", rv_codec_cb_sh6, NULL, DECOMP(op_srai))
|
||||
OP(c_srli, "c.srli", rv_codec_cb_sh6, NULL, DECOMP(op_srli))
|
||||
OP(c_sspopchk, "c.sspopchk", rv_codec_cmop_ss, NULL, DECOMP(op_sspopchk))
|
||||
OP(c_sspush, "c.sspush", rv_codec_cmop_ss, NULL, DECOMP(op_sspush))
|
||||
OP(c_sub, "c.sub", rv_codec_cs, NULL, DECOMP(op_sub))
|
||||
OP(c_subw, "c.subw", rv_codec_cs, NULL, DECOMP(op_subw))
|
||||
OP(c_sw, "c.sw", rv_codec_cs_sw, NULL, DECOMP(op_sw))
|
||||
OP(c_swsp, "c.swsp", rv_codec_css_swsp, NULL, DECOMP(op_sw))
|
||||
OP(c_xor, "c.xor", rv_codec_cs, NULL, DECOMP(op_xor))
|
||||
OP(c_zext_b, "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd)
|
||||
OP(c_zext_h, "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd)
|
||||
OP(c_zext_w, "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd)
|
||||
OP(cbo_clean, "cbo.clean", rv_codec_r, rv_fmt_rs1)
|
||||
OP(cbo_flush, "cbo.flush", rv_codec_r, rv_fmt_rs1)
|
||||
OP(cbo_inval, "cbo.inval", rv_codec_r, rv_fmt_rs1)
|
||||
OP(cbo_zero, "cbo.zero", rv_codec_r, rv_fmt_rs1)
|
||||
OP(clmul, "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(clmulh, "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(clmulr, "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(clz, "clz", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(clzw, "clzw", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(cm_jalt, "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
|
||||
OP(cm_jt, "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index)
|
||||
OP(cm_mva01s, "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
|
||||
OP(cm_mvsa01, "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2)
|
||||
OP(cm_pop, "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
|
||||
OP(cm_popret, "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
|
||||
OP(cm_popretz, "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist)
|
||||
OP(cm_push, "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist)
|
||||
OP(cpop, "cpop", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(cpopw, "cpopw", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(csrrc, "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
|
||||
OP(csrrci, "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
|
||||
OP(csrrs, "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
|
||||
OP(csrrsi, "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
|
||||
OP(csrrw, "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1)
|
||||
OP(csrrwi, "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm)
|
||||
OP(ctz, "ctz", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(ctzw, "ctzw", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(czero_eqz, "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(czero_nez, "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(div, "div", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(divd, "divd", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(divu, "divu", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(divud, "divud", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(divuw, "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(divw, "divw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(dret, "dret", rv_codec_none, rv_fmt_none)
|
||||
OP(ebreak, "ebreak", rv_codec_none, rv_fmt_none)
|
||||
OP(ecall, "ecall", rv_codec_none, rv_fmt_none)
|
||||
OP(fabs_d, "fabs.d", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fabs_q, "fabs.q", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fabs_s, "fabs.s", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fadd_d, "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fadd_q, "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fadd_s, "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fclass_d, "fclass.d", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fclass_q, "fclass.q", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fclass_s, "fclass.s", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fcvt_bf16_s, "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_d_l, "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_d_lu, "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_d_q, "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_d_s, "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_d_w, "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_d_wu, "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_l_d, "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_l_q, "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_l_s, "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_lu_d, "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_lu_q, "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_lu_s, "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_q_d, "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_q_l, "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_q_lu, "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_q_s, "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_q_w, "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_q_wu, "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_s_bf16, "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_s_d, "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_s_l, "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_s_lu, "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_s_q, "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fcvt_s_w, "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_s_wu, "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1)
|
||||
OP(fcvt_w_d, "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_w_q, "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_w_s, "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_wu_d, "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_wu_q, "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvt_wu_s, "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fcvtmod_w_d, "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1)
|
||||
OP(fdiv_d, "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fdiv_q, "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fdiv_s, "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fence, "fence", rv_codec_r_f, rv_fmt_pred_succ)
|
||||
OP(fence_i, "fence.i", rv_codec_none, rv_fmt_none)
|
||||
OP(feq_d, "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(feq_q, "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(feq_s, "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fld, "fld", rv_codec_i, rv_fmt_frd_offset_rs1)
|
||||
OP(fle_d, "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fle_q, "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fle_s, "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fleq_d, "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fleq_h, "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fleq_q, "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fleq_s, "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(flh, "flh", rv_codec_i, rv_fmt_frd_offset_rs1)
|
||||
OP(fli_d, "fli.d", rv_codec_fli, rv_fmt_fli)
|
||||
OP(fli_h, "fli.h", rv_codec_fli, rv_fmt_fli)
|
||||
OP(fli_q, "fli.q", rv_codec_fli, rv_fmt_fli)
|
||||
OP(fli_s, "fli.s", rv_codec_fli, rv_fmt_fli)
|
||||
OP(flq, "flq", rv_codec_i, rv_fmt_frd_offset_rs1)
|
||||
OP(flt_d, "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(flt_q, "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(flt_s, "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fltq_d, "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fltq_h, "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fltq_q, "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(fltq_s, "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2)
|
||||
OP(flw, "flw", rv_codec_i, rv_fmt_frd_offset_rs1)
|
||||
OP(fmadd_d, "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fmadd_q, "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fmadd_s, "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fmax_d, "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmax_q, "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmax_s, "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmaxm_d, "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmaxm_h, "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmaxm_q, "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmaxm_s, "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmin_d, "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmin_q, "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmin_s, "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fminm_d, "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fminm_h, "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fminm_q, "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fminm_s, "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2)
|
||||
OP(fmsub_d, "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fmsub_q, "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fmsub_s, "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fmul_d, "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fmul_q, "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fmul_s, "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fmv_d, "fmv.d", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fmv_d_x, "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1)
|
||||
OP(fmv_h_x, "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1)
|
||||
OP(fmv_q, "fmv.q", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fmv_q_x, "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1)
|
||||
OP(fmv_s, "fmv.s", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fmv_s_x, "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1)
|
||||
OP(fmv_x_d, "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fmv_x_h, "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fmv_x_q, "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fmv_x_s, "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fmvh_x_d, "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fmvh_x_q, "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(fmvp_d_x, "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
|
||||
OP(fmvp_q_x, "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2)
|
||||
OP(fneg_d, "fneg.d", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fneg_q, "fneg.q", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fneg_s, "fneg.s", rv_codec_illegal, rv_fmt_frd_frs1)
|
||||
OP(fnmadd_d, "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fnmadd_q, "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fnmadd_s, "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fnmsub_d, "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fnmsub_q, "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(fnmsub_s, "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3)
|
||||
OP(frcsr, "frcsr", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(frflags, "frflags", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(fround_d, "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fround_h, "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fround_q, "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fround_s, "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(froundnx_d, "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(froundnx_h, "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(froundnx_q, "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(froundnx_s, "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(frrm, "frrm", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(fscsr, "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1)
|
||||
OP(fsd, "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1)
|
||||
OP(fsflags, "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1)
|
||||
OP(fsflagsi, "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm)
|
||||
OP(fsgnj_d, "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d)
|
||||
OP(fsgnj_q, "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q)
|
||||
OP(fsgnj_s, "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s)
|
||||
OP(fsgnjn_d, "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d)
|
||||
OP(fsgnjn_q, "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q)
|
||||
OP(fsgnjn_s, "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s)
|
||||
OP(fsgnjx_d, "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d)
|
||||
OP(fsgnjx_q, "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q)
|
||||
OP(fsgnjx_s, "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s)
|
||||
OP(fsh, "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1)
|
||||
OP(fsq, "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1)
|
||||
OP(fsqrt_d, "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fsqrt_q, "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fsqrt_s, "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1)
|
||||
OP(fsrm, "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1)
|
||||
OP(fsrmi, "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm)
|
||||
OP(fsub_d, "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fsub_q, "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fsub_s, "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2)
|
||||
OP(fsw, "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1)
|
||||
OP(hret, "hret", rv_codec_none, rv_fmt_none)
|
||||
OP(illegal, "illegal", rv_codec_none, rv_fmt_none)
|
||||
OP(j, "j", rv_codec_illegal, rv_fmt_offset)
|
||||
OP(jal, "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal)
|
||||
OP(jal_ra, "jal", rv_codec_illegal, rv_fmt_offset)
|
||||
OP(jalr, "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr)
|
||||
OP(jalr_ra, "jalr", rv_codec_illegal, rv_fmt_rs1)
|
||||
OP(jr, "jr", rv_codec_illegal, rv_fmt_rs1, rvcp_jr)
|
||||
OP(lb, "lb", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(lbu, "lbu", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(ld, "ld", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(ldu, "ldu", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(lh, "lh", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(lhu, "lhu", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(lpad, "lpad", rv_codec_lp, rv_fmt_imm)
|
||||
OP(lq, "lq", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(lr_d, "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
|
||||
OP(lr_q, "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
|
||||
OP(lr_w, "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1)
|
||||
OP(lui, "lui", rv_codec_u, rv_fmt_rd_uimm)
|
||||
OP(lw, "lw", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(lwu, "lwu", rv_codec_i, rv_fmt_rd_offset_rs1)
|
||||
OP(max, "max", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(maxu, "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(min, "min", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(minu, "minu", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(mnret, "mnret", rv_codec_none, rv_fmt_none)
|
||||
OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r)
|
||||
OP(mop_rr, "mop.rr", rv_codec_mop_rr, rv_fmt_mop_rr)
|
||||
OP(mret, "mret", rv_codec_none, rv_fmt_none)
|
||||
OP(mul, "mul", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(muld, "muld", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(mulh, "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(mulhsu, "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(mulhu, "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(mulw, "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(mv, "mv", rv_codec_illegal, rv_fmt_rd_rs1, rvcp_mv)
|
||||
OP(neg, "neg", rv_codec_illegal, rv_fmt_rd_rs2)
|
||||
OP(negw, "negw", rv_codec_illegal, rv_fmt_rd_rs2)
|
||||
OP(nop, "nop", rv_codec_illegal, rv_fmt_none)
|
||||
OP(not, "not", rv_codec_illegal, rv_fmt_rd_rs1)
|
||||
OP(or, "or", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(orc_b, "orc.b", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(ori, "ori", rv_codec_i, rv_fmt_rd_rs1_imm)
|
||||
OP(orn, "orn", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(pack, "pack", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(packh, "packh", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(packw, "packw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(rdcycle, "rdcycle", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(rdcycleh, "rdcycleh", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(rdinstret, "rdinstret", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(rdinstreth, "rdinstreth", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(rdtime, "rdtime", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(rdtimeh, "rdtimeh", rv_codec_i_csr, rv_fmt_rd)
|
||||
OP(rem, "rem", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(remd, "remd", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(remu, "remu", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(remud, "remud", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(remuw, "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(remw, "remw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(ret, "ret", rv_codec_illegal, rv_fmt_none)
|
||||
OP(rev8, "rev8", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(rol, "rol", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(rolw, "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(ror, "ror", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(rori, "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(roriw, "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
|
||||
OP(rorw, "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sb, "sb", rv_codec_s, rv_fmt_rs2_offset_rs1)
|
||||
OP(sc_d, "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(sc_q, "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(sc_w, "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(sd, "sd", rv_codec_s, rv_fmt_rs2_offset_rs1)
|
||||
OP(seqz, "seqz", rv_codec_illegal, rv_fmt_rd_rs1)
|
||||
OP(sext_b, "sext.b", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sext_h, "sext.h", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sext_w, "sext.w", rv_codec_illegal, rv_fmt_rd_rs1)
|
||||
OP(sfence_vm, "sfence.vm", rv_codec_r, rv_fmt_rs1)
|
||||
OP(sfence_vma, "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2)
|
||||
OP(sgtz, "sgtz", rv_codec_illegal, rv_fmt_rd_rs2)
|
||||
OP(sh, "sh", rv_codec_s, rv_fmt_rs2_offset_rs1)
|
||||
OP(sh1add, "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sh1add_uw, "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sh2add, "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sh2add_uw, "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sh3add, "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sh3add_uw, "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha256sig0, "sha256sig0", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sha256sig1, "sha256sig1", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sha256sum0, "sha256sum0", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sha256sum1, "sha256sum1", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sha512sig0, "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sig0h, "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sig0l, "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sig1, "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sig1h, "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sig1l, "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sum0, "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sum0r, "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sum1, "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sha512sum1r, "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sll, "sll", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(slld, "slld", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(slli, "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(slli_uw, "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
|
||||
OP(sllid, "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
|
||||
OP(slliw, "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
|
||||
OP(sllw, "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(slt, "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt)
|
||||
OP(slti, "slti", rv_codec_i, rv_fmt_rd_rs1_imm)
|
||||
OP(sltiu, "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu)
|
||||
OP(sltu, "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu)
|
||||
OP(sltz, "sltz", rv_codec_illegal, rv_fmt_rd_rs1)
|
||||
OP(sm3p0, "sm3p0", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sm3p1, "sm3p1", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(sm4ed, "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
|
||||
OP(sm4ks, "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs)
|
||||
OP(snez, "snez", rv_codec_illegal, rv_fmt_rd_rs2)
|
||||
OP(sq, "sq", rv_codec_s, rv_fmt_rs2_offset_rs1)
|
||||
OP(sra, "sra", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(srad, "srad", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(srai, "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(sraid, "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
|
||||
OP(sraiw, "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
|
||||
OP(sraw, "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(sret, "sret", rv_codec_none, rv_fmt_none)
|
||||
OP(srl, "srl", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(srld, "srld", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(srli, "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm)
|
||||
OP(srlid, "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm)
|
||||
OP(srliw, "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm)
|
||||
OP(srlw, "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(ssamoswap_d, "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(ssamoswap_w, "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1)
|
||||
OP(sspopchk, "sspopchk", rv_codec_r, rv_fmt_rs1)
|
||||
OP(sspush, "sspush", rv_codec_r, rv_fmt_rs2)
|
||||
OP(ssrdp, "ssrdp", rv_codec_r, rv_fmt_rd)
|
||||
OP(sub, "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub)
|
||||
OP(subd, "subd", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(subw, "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw)
|
||||
OP(sw, "sw", rv_codec_s, rv_fmt_rs2_offset_rs1)
|
||||
OP(unzip, "unzip", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(uret, "uret", rv_codec_none, rv_fmt_none)
|
||||
OP(vaadd_vv, "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vaadd_vx, "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vaaddu_vv, "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vaaddu_vx, "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vadc_vim, "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
|
||||
OP(vadc_vvm, "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
|
||||
OP(vadc_vxm, "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
|
||||
OP(vadd_vi, "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vadd_vv, "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vadd_vx, "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vaesdf_vs, "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesdf_vv, "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesdm_vs, "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesdm_vv, "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesef_vs, "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesef_vv, "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesem_vs, "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaesem_vv, "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vaeskf1_vi, "vaeskf1.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
|
||||
OP(vaeskf2_vi, "vaeskf2.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
|
||||
OP(vaesz_vs, "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vand_vi, "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vand_vv, "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vand_vx, "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vandn_vv, "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vandn_vx, "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vasub_vv, "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vasub_vx, "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vasubu_vv, "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vasubu_vx, "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vbrev8_v, "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vbrev_v, "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vclmul_vv, "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vclmul_vx, "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vclmulh_vv, "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vclmulh_vx, "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vclz_v, "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vcompress_vm, "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
|
||||
OP(vcpop_m, "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
|
||||
OP(vcpop_v, "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vctz_v, "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vdiv_vv, "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vdiv_vx, "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vdivu_vv, "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vdivu_vx, "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vfadd_vf, "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfadd_vv, "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfclass_v, "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfcvt_f_x_v, "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfcvt_f_xu_v, "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfcvt_rtz_x_f_v, "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfcvt_rtz_xu_f_v, "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfcvt_x_f_v, "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfcvt_xu_f_v, "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfdiv_vf, "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfdiv_vv, "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfirst_m, "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm)
|
||||
OP(vfmacc_vf, "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfmacc_vv, "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfmadd_vf, "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfmadd_vv, "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfmax_vf, "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfmax_vv, "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfmerge_vfm, "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl)
|
||||
OP(vfmin_vf, "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfmin_vv, "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfmsac_vf, "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfmsac_vv, "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfmsub_vf, "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfmsub_vv, "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfmul_vf, "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfmul_vv, "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfmv_f_s, "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2)
|
||||
OP(vfmv_s_f, "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1)
|
||||
OP(vfmv_v_f, "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1)
|
||||
OP(vfncvt_f_f_w, "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_f_x_w, "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_f_xu_w, "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_rod_f_f_w, "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_rtz_x_f_w, "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_rtz_xu_f_w, "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_x_f_w, "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvt_xu_f_w, "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfncvtbf16_f_f_w, "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfnmacc_vf, "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfnmacc_vv, "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfnmadd_vf, "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfnmadd_vv, "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfnmsac_vf, "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfnmsac_vv, "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfnmsub_vf, "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfnmsub_vv, "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfrdiv_vf, "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfrec7_v, "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vfredmax_vs, "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfredmin_vs, "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfredosum_vs, "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfredusum_vs, "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfrsqrt7_v, "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vfrsub_vf, "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfsgnj_vf, "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfsgnj_vv, "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfsgnjn_vf, "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfsgnjn_vv, "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfsgnjx_vf, "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfsgnjx_vv, "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfslide1down_vf, "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfslide1up_vf, "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfsqrt_v, "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vfsub_vf, "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfsub_vv, "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwadd_vf, "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfwadd_vv, "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwadd_wf, "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfwadd_wv, "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwcvt_f_f_v, "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvt_f_x_v, "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvt_f_xu_v, "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvt_rtz_x_f_v, "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvt_rtz_xu_f_v, "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvt_x_f_v, "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvt_xu_f_v, "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwcvtbf16_f_f_v, "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vfwmacc_vf, "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfwmacc_vv, "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfwmaccbf16_vf, "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfwmaccbf16_vv, "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfwmsac_vf, "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfwmsac_vv, "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfwmul_vf, "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfwmul_vv, "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwnmacc_vf, "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfwnmacc_vv, "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfwnmsac_vf, "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm)
|
||||
OP(vfwnmsac_vv, "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vfwredosum_vs, "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwredusum_vs, "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwsub_vf, "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfwsub_vv, "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vfwsub_wf, "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vfwsub_wv, "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vghsh_vv, "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
|
||||
OP(vgmul_vv, "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vid_v, "vid.v", rv_codec_v_r, rv_fmt_vd_vm)
|
||||
OP(viota_m, "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vl1re16_v, "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl1re32_v, "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl1re64_v, "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl1re8_v, "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl2re16_v, "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl2re32_v, "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl2re64_v, "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl2re8_v, "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl4re16_v, "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl4re32_v, "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl4re64_v, "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl4re8_v, "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl8re16_v, "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl8re32_v, "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl8re64_v, "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vl8re8_v, "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle16_v, "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle16ff_v, "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle32_v, "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle32ff_v, "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle64_v, "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle64ff_v, "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle8_v, "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vle8ff_v, "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vlm_v, "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vloxei16_v, "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vloxei32_v, "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vloxei64_v, "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vloxei8_v, "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vlse16_v, "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vlse32_v, "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vlse64_v, "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vlse8_v, "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vluxei16_v, "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vluxei32_v, "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vluxei64_v, "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vluxei8_v, "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vmacc_vv, "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vmacc_vx, "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vmadc_vim, "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
|
||||
OP(vmadc_vvm, "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
|
||||
OP(vmadc_vxm, "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
|
||||
OP(vmadd_vv, "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vmadd_vx, "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vmand_mm, "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmandn_mm, "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmax_vv, "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmax_vx, "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmaxu_vv, "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmaxu_vx, "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmerge_vim, "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
|
||||
OP(vmerge_vvm, "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
|
||||
OP(vmerge_vxm, "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
|
||||
OP(vmfeq_vf, "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vmfeq_vv, "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmfge_vf, "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vmfgt_vf, "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vmfle_vf, "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vmfle_vv, "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmflt_vf, "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vmflt_vv, "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmfne_vf, "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm)
|
||||
OP(vmfne_vv, "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmin_vv, "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmin_vx, "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vminu_vv, "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vminu_vx, "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmnand_mm, "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmnor_mm, "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmor_mm, "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmorn_mm, "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmsbc_vvm, "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
|
||||
OP(vmsbc_vxm, "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
|
||||
OP(vmsbf_m, "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vmseq_vi, "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vmseq_vv, "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmseq_vx, "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsgt_vi, "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vmsgt_vx, "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsgtu_vi, "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vmsgtu_vx, "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsif_m, "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vmsle_vi, "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vmsle_vv, "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmsle_vx, "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsleu_vi, "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vmsleu_vv, "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmsleu_vx, "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmslt_vv, "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmslt_vx, "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsltu_vv, "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmsltu_vx, "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsne_vi, "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vmsne_vv, "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmsne_vx, "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmsof_m, "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vmul_vv, "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmul_vx, "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmulh_vv, "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmulh_vx, "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmulhsu_vv, "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmulhsu_vx, "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmulhu_vv, "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmulhu_vx, "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vmv1r_v, "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vmv2r_v, "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vmv4r_v, "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vmv8r_v, "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vmv_s_x, "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1)
|
||||
OP(vmv_v_i, "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm)
|
||||
OP(vmv_v_v, "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1)
|
||||
OP(vmv_v_x, "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1)
|
||||
OP(vmv_x_s, "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2)
|
||||
OP(vmxnor_mm, "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vmxor_mm, "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vnclip_wi, "vnclip.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vnclip_wv, "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vnclip_wx, "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vnclipu_wi, "vnclipu.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vnclipu_wv, "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vnclipu_wx, "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vnmsac_vv, "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vnmsac_vx, "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vnmsub_vv, "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vnmsub_vx, "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vnsra_wi, "vnsra.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vnsra_wv, "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vnsra_wx, "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vnsrl_wi, "vnsrl.wi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vnsrl_wv, "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vnsrl_wx, "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vor_vi, "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vor_vv, "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vor_vx, "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vredand_vs, "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredmax_vs, "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredmaxu_vs, "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredmin_vs, "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredminu_vs, "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredor_vs, "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredsum_vs, "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vredxor_vs, "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vrem_vv, "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vrem_vx, "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vremu_vv, "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vremu_vx, "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vrev8_v, "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vrgather_vi, "vrgather.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vrgather_vv, "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vrgather_vx, "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vrgatherei16_vv, "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vrol_vv, "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vrol_vx, "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vror_vi, "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vror_vv, "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vror_vx, "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vrsub_vi, "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vrsub_vx, "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vs1r_v, "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vs2r_v, "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vs4r_v, "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vs8r_v, "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vsadd_vi, "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vsadd_vv, "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsadd_vx, "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsaddu_vi, "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vsaddu_vv, "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsaddu_vx, "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsbc_vvm, "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
|
||||
OP(vsbc_vxm, "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
|
||||
OP(vse16_v, "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vse32_v, "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vse64_v, "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vse8_v, "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vsetivli, "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli)
|
||||
OP(vsetvl, "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(vsetvli, "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli)
|
||||
OP(vsext_vf2, "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vsext_vf4, "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vsext_vf8, "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vsha2ch_vv, "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
|
||||
OP(vsha2cl_vv, "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
|
||||
OP(vsha2ms_vv, "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
|
||||
OP(vslide1down_vx, "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vslide1up_vx, "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vslidedown_vi, "vslidedown.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vslidedown_vx, "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vslideup_vi, "vslideup.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vslideup_vx, "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsll_vi, "vsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vsll_vv, "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsll_vx, "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsm3c_vi, "vsm3c.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
|
||||
OP(vsm3me_vv, "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1)
|
||||
OP(vsm4k_vi, "vsm4k.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm)
|
||||
OP(vsm4r_vs, "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vsm4r_vv, "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2)
|
||||
OP(vsm_v, "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm)
|
||||
OP(vsmul_vv, "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsmul_vx, "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsoxei16_v, "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsoxei32_v, "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsoxei64_v, "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsoxei8_v, "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsra_vi, "vsra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vsra_vv, "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsra_vx, "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsrl_vi, "vsrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vsrl_vv, "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsrl_vx, "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsse16_v, "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vsse32_v, "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vsse64_v, "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vsse8_v, "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm)
|
||||
OP(vssra_vi, "vssra.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vssra_vv, "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vssra_vx, "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vssrl_vi, "vssrl.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vssrl_vv, "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vssrl_vx, "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vssub_vv, "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vssub_vx, "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vssubu_vv, "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vssubu_vx, "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsub_vv, "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vsub_vx, "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vsuxei16_v, "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsuxei32_v, "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsuxei64_v, "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vsuxei8_v, "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm)
|
||||
OP(vwadd_vv, "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwadd_vx, "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwadd_wv, "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwadd_wx, "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwaddu_vv, "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwaddu_vx, "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwaddu_wv, "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwaddu_wx, "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwmacc_vv, "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vwmacc_vx, "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vwmaccsu_vv, "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vwmaccsu_vx, "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vwmaccu_vv, "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm)
|
||||
OP(vwmaccu_vx, "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vwmaccus_vx, "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm)
|
||||
OP(vwmul_vv, "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwmul_vx, "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwmulsu_vv, "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwmulsu_vx, "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwmulu_vv, "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwmulu_vx, "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwredsum_vs, "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwredsumu_vs, "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwsll_vi, "vwsll.vi", rv_codec_v_i_u, rv_fmt_vd_vs2_uimm_vm)
|
||||
OP(vwsll_vv, "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwsll_vx, "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwsub_vv, "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwsub_vx, "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwsub_wv, "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwsub_wx, "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwsubu_vv, "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwsubu_vx, "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vwsubu_wv, "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vwsubu_wx, "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vxor_vi, "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm)
|
||||
OP(vxor_vv, "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
|
||||
OP(vxor_vx, "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
|
||||
OP(vzext_vf2, "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vzext_vf4, "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(vzext_vf8, "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm)
|
||||
OP(wfi, "wfi", rv_codec_none, rv_fmt_none)
|
||||
OP(wrs_nto, "wrs.nto", rv_codec_none, rv_fmt_none)
|
||||
OP(wrs_sto, "wrs.sto", rv_codec_none, rv_fmt_none)
|
||||
OP(xnor, "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(xor, "xor", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(xori, "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori)
|
||||
OP(xperm4, "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(xperm8, "xperm8", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(zext_h, "zext.h", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(zip, "zip", rv_codec_r, rv_fmt_rd_rs1)
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
OP(crc32_b, "crc32.b", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32_h, "crc32.h", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32_w, "crc32.w", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32_d, "crc32.d", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32c_b, "crc32c.b", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32c_h, "crc32c.h", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32c_w, "crc32c.w", rv_codec_r, rv_fmt_rd_rs1)
|
||||
OP(crc32c_d, "crc32c.d", rv_codec_r, rv_fmt_rd_rs1)
|
||||
|
|
@ -8,16 +8,38 @@
|
|||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
|
||||
#include "disas/riscv.h"
|
||||
#include "disas/riscv-xlrbr.h"
|
||||
|
||||
#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
|
||||
#include "riscv-xlrbr-op.c.inc"
|
||||
#undef OP
|
||||
typedef enum {
|
||||
/* 0 is reserved for rv_op_illegal. */
|
||||
rv_op_crc32_b = 1,
|
||||
rv_op_crc32_h = 2,
|
||||
rv_op_crc32_w = 3,
|
||||
rv_op_crc32_d = 4,
|
||||
rv_op_crc32c_b = 5,
|
||||
rv_op_crc32c_h = 6,
|
||||
rv_op_crc32c_w = 7,
|
||||
rv_op_crc32c_d = 8,
|
||||
} rv_xlrbr_op;
|
||||
|
||||
const rv_opcode_data *decode_xlrbr(rv_decode *dec, rv_isa isa)
|
||||
const rv_opcode_data rv_xlrbr_opcode_data[] = {
|
||||
{ "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
{ "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
{ "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
{ "crc32.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
{ "crc32.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
{ "crc32c.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
{ "crc32c.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
{ "crc32c.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
{ "crc32c.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
};
|
||||
|
||||
void decode_xlrbr(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch ((inst >> 0) & 0b1111111) {
|
||||
case 0b0010011:
|
||||
|
|
@ -25,26 +47,33 @@ const rv_opcode_data *decode_xlrbr(rv_decode *dec, rv_isa isa)
|
|||
case 0b001:
|
||||
switch ((inst >> 20 & 0b111111111111)) {
|
||||
case 0b011000010000:
|
||||
return &op_crc32_b;
|
||||
op = rv_op_crc32_b;
|
||||
break;
|
||||
case 0b011000010001:
|
||||
return &op_crc32_h;
|
||||
op = rv_op_crc32_h;
|
||||
break;
|
||||
case 0b011000010010:
|
||||
return &op_crc32_w;
|
||||
op = rv_op_crc32_w;
|
||||
break;
|
||||
case 0b011000010011:
|
||||
return &op_crc32_d;
|
||||
op = rv_op_crc32_d;
|
||||
break;
|
||||
case 0b011000011000:
|
||||
return &op_crc32c_b;
|
||||
op = rv_op_crc32c_b;
|
||||
break;
|
||||
case 0b011000011001:
|
||||
return &op_crc32c_h;
|
||||
op = rv_op_crc32c_h;
|
||||
break;
|
||||
case 0b011000011010:
|
||||
return &op_crc32c_w;
|
||||
op = rv_op_crc32c_w;
|
||||
break;
|
||||
case 0b011000011011:
|
||||
return &op_crc32c_d;
|
||||
op = rv_op_crc32c_d;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,6 +12,8 @@
|
|||
|
||||
#include "disas/riscv.h"
|
||||
|
||||
const rv_opcode_data *decode_xlrbr(rv_decode *, rv_isa);
|
||||
extern const rv_opcode_data rv_xlrbr_opcode_data[];
|
||||
|
||||
void decode_xlrbr(rv_decode *, rv_isa);
|
||||
|
||||
#endif /* DISAS_RISCV_XLRBR_H */
|
||||
|
|
|
|||
|
|
@ -1,125 +0,0 @@
|
|||
/* XTheadBa */
|
||||
OP(th_addsl, "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
|
||||
/* XTheadBb */
|
||||
OP(th_srri, "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm)
|
||||
OP(th_srriw, "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm)
|
||||
OP(th_ext, "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml)
|
||||
OP(th_extu, "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml)
|
||||
OP(th_ff0, "th.ff0", rv_codec_r2, rv_fmt_rd_rs1)
|
||||
OP(th_ff1, "th.ff1", rv_codec_r2, rv_fmt_rd_rs1)
|
||||
OP(th_rev, "th.rev", rv_codec_r2, rv_fmt_rd_rs1)
|
||||
OP(th_revw, "th.revw", rv_codec_r2, rv_fmt_rd_rs1)
|
||||
OP(th_tstnbz, "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1)
|
||||
|
||||
/* XTheadBs */
|
||||
OP(th_tst, "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm)
|
||||
|
||||
/* XTheadCmo */
|
||||
OP(th_dcache_call, "th.dcache.call", rv_codec_none, rv_fmt_none)
|
||||
OP(th_dcache_ciall, "th.dcache.ciall", rv_codec_none, rv_fmt_none)
|
||||
OP(th_dcache_iall, "th.dcache.iall", rv_codec_none, rv_fmt_none)
|
||||
OP(th_dcache_cpa, "th.dcache.cpa", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_cipa, "th.dcache.cipa", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_ipa, "th.dcache.ipa", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_cva, "th.dcache.cva", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_civa, "th.dcache.civa", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_iva, "th.dcache.iva", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_csw, "th.dcache.csw", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_cisw, "th.dcache.cisw", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_isw, "th.dcache.isw", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_cpal1, "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_dcache_cval1, "th.dcache.cval1", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_icache_iall, "th.icache.iall", rv_codec_none, rv_fmt_none)
|
||||
OP(th_icache_ialls, "th.icache.ialls", rv_codec_none, rv_fmt_none)
|
||||
OP(th_icache_ipa, "th.icache.ipa", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_icache_iva, "th.icache.iva", rv_codec_r, rv_fmt_rs1)
|
||||
OP(th_l2cache_call, "th.l2cache.call", rv_codec_none, rv_fmt_none)
|
||||
OP(th_l2cache_ciall, "th.l2cache.ciall", rv_codec_none, rv_fmt_none)
|
||||
OP(th_l2cache_iall, "th.l2cache.iall", rv_codec_none, rv_fmt_none)
|
||||
|
||||
/* XTheadCondMov */
|
||||
OP(th_mveqz, "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(th_mvnez, "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
|
||||
/* XTheadFMemIdx */
|
||||
OP(th_flrd, "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_flrw, "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_flurd, "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_flurw, "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_fsrd, "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_fsrw, "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_fsurd, "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
OP(th_fsurw, "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm)
|
||||
|
||||
/* XTheadFmv */
|
||||
OP(th_fmv_hw_x, "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1)
|
||||
OP(th_fmv_x_hw, "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1)
|
||||
|
||||
/* XTheadMac */
|
||||
OP(th_mula, "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(th_mulaw, "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(th_mulah, "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(th_muls, "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(th_mulsw, "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(th_mulsh, "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
|
||||
/* XTheadMemIdx */
|
||||
OP(th_lbia, "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lbib, "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lbuia, "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lbuib, "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lhia, "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lhib, "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lhuia, "th.lhuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lhuib, "th.lhuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lwia, "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lwib, "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lwuia, "th.lwuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lwuib, "th.lwuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_ldia, "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_ldib, "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_sbia, "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_sbib, "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_shia, "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_shib, "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_swia, "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_swib, "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_sdia, "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_sdib, "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr)
|
||||
OP(th_lrb, "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lrbu, "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lrh, "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lrhu, "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lrw, "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lrwu, "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lrd, "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_srb, "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_srh, "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_srw, "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_srd, "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurb, "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurbu, "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurh, "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurhu, "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurw, "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurwu, "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_lurd, "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_surb, "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_surh, "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_surw, "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
OP(th_surd, "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm)
|
||||
|
||||
/* XTheadMemPair */
|
||||
OP(th_ldd, "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm)
|
||||
OP(th_lwd, "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm)
|
||||
OP(th_lwud, "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm)
|
||||
OP(th_sdd, "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm)
|
||||
OP(th_swd, "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm)
|
||||
|
||||
/* XTheadSync */
|
||||
OP(th_sfence_vmas, "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2)
|
||||
OP(th_sync, "th.sync", rv_codec_none, rv_fmt_none)
|
||||
OP(th_sync_i, "th.sync.i", rv_codec_none, rv_fmt_none)
|
||||
OP(th_sync_is, "th.sync.is", rv_codec_none, rv_fmt_none)
|
||||
OP(th_sync_s, "th.sync.s", rv_codec_none, rv_fmt_none)
|
||||
|
|
@ -8,13 +8,248 @@
|
|||
#include "disas/riscv.h"
|
||||
#include "disas/riscv-xthead.h"
|
||||
|
||||
#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
|
||||
#include "riscv-xthead-op.c.inc"
|
||||
#undef OP
|
||||
typedef enum {
|
||||
/* 0 is reserved for rv_op_illegal. */
|
||||
/* XTheadBa */
|
||||
rv_op_th_addsl = 1,
|
||||
/* XTheadBb */
|
||||
rv_op_th_srri,
|
||||
rv_op_th_srriw,
|
||||
rv_op_th_ext,
|
||||
rv_op_th_extu,
|
||||
rv_op_th_ff0,
|
||||
rv_op_th_ff1,
|
||||
rv_op_th_rev,
|
||||
rv_op_th_revw,
|
||||
rv_op_th_tstnbz,
|
||||
/* XTheadBs */
|
||||
rv_op_th_tst,
|
||||
/* XTheadCmo */
|
||||
rv_op_th_dcache_call,
|
||||
rv_op_th_dcache_ciall,
|
||||
rv_op_th_dcache_iall,
|
||||
rv_op_th_dcache_cpa,
|
||||
rv_op_th_dcache_cipa,
|
||||
rv_op_th_dcache_ipa,
|
||||
rv_op_th_dcache_cva,
|
||||
rv_op_th_dcache_civa,
|
||||
rv_op_th_dcache_iva,
|
||||
rv_op_th_dcache_csw,
|
||||
rv_op_th_dcache_cisw,
|
||||
rv_op_th_dcache_isw,
|
||||
rv_op_th_dcache_cpal1,
|
||||
rv_op_th_dcache_cval1,
|
||||
rv_op_th_icache_iall,
|
||||
rv_op_th_icache_ialls,
|
||||
rv_op_th_icache_ipa,
|
||||
rv_op_th_icache_iva,
|
||||
rv_op_th_l2cache_call,
|
||||
rv_op_th_l2cache_ciall,
|
||||
rv_op_th_l2cache_iall,
|
||||
/* XTheadCondMov */
|
||||
rv_op_th_mveqz,
|
||||
rv_op_th_mvnez,
|
||||
/* XTheadFMemIdx */
|
||||
rv_op_th_flrd,
|
||||
rv_op_th_flrw,
|
||||
rv_op_th_flurd,
|
||||
rv_op_th_flurw,
|
||||
rv_op_th_fsrd,
|
||||
rv_op_th_fsrw,
|
||||
rv_op_th_fsurd,
|
||||
rv_op_th_fsurw,
|
||||
/* XTheadFmv */
|
||||
rv_op_th_fmv_hw_x,
|
||||
rv_op_th_fmv_x_hw,
|
||||
/* XTheadMac */
|
||||
rv_op_th_mula,
|
||||
rv_op_th_mulah,
|
||||
rv_op_th_mulaw,
|
||||
rv_op_th_muls,
|
||||
rv_op_th_mulsw,
|
||||
rv_op_th_mulsh,
|
||||
/* XTheadMemIdx */
|
||||
rv_op_th_lbia,
|
||||
rv_op_th_lbib,
|
||||
rv_op_th_lbuia,
|
||||
rv_op_th_lbuib,
|
||||
rv_op_th_lhia,
|
||||
rv_op_th_lhib,
|
||||
rv_op_th_lhuia,
|
||||
rv_op_th_lhuib,
|
||||
rv_op_th_lwia,
|
||||
rv_op_th_lwib,
|
||||
rv_op_th_lwuia,
|
||||
rv_op_th_lwuib,
|
||||
rv_op_th_ldia,
|
||||
rv_op_th_ldib,
|
||||
rv_op_th_sbia,
|
||||
rv_op_th_sbib,
|
||||
rv_op_th_shia,
|
||||
rv_op_th_shib,
|
||||
rv_op_th_swia,
|
||||
rv_op_th_swib,
|
||||
rv_op_th_sdia,
|
||||
rv_op_th_sdib,
|
||||
rv_op_th_lrb,
|
||||
rv_op_th_lrbu,
|
||||
rv_op_th_lrh,
|
||||
rv_op_th_lrhu,
|
||||
rv_op_th_lrw,
|
||||
rv_op_th_lrwu,
|
||||
rv_op_th_lrd,
|
||||
rv_op_th_srb,
|
||||
rv_op_th_srh,
|
||||
rv_op_th_srw,
|
||||
rv_op_th_srd,
|
||||
rv_op_th_lurb,
|
||||
rv_op_th_lurbu,
|
||||
rv_op_th_lurh,
|
||||
rv_op_th_lurhu,
|
||||
rv_op_th_lurw,
|
||||
rv_op_th_lurwu,
|
||||
rv_op_th_lurd,
|
||||
rv_op_th_surb,
|
||||
rv_op_th_surh,
|
||||
rv_op_th_surw,
|
||||
rv_op_th_surd,
|
||||
/* XTheadMemPair */
|
||||
rv_op_th_ldd,
|
||||
rv_op_th_lwd,
|
||||
rv_op_th_lwud,
|
||||
rv_op_th_sdd,
|
||||
rv_op_th_swd,
|
||||
/* XTheadSync */
|
||||
rv_op_th_sfence_vmas,
|
||||
rv_op_th_sync,
|
||||
rv_op_th_sync_i,
|
||||
rv_op_th_sync_is,
|
||||
rv_op_th_sync_s,
|
||||
} rv_xthead_op;
|
||||
|
||||
const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
|
||||
const rv_opcode_data xthead_opcode_data[] = {
|
||||
{ "th.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
/* XTheadBa */
|
||||
{ "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
/* XTheadBb */
|
||||
{ "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
|
||||
{ "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
|
||||
{ "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 },
|
||||
{ "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 },
|
||||
{ "th.ff0", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.ff1", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.rev", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.revw", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
|
||||
/* XTheadBs */
|
||||
{ "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
|
||||
/* XTheadCmo */
|
||||
{ "th.dcache.call", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.ciall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.cpa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.cipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.ipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.cva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.civa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.iva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.csw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.cisw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.isw", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.cpal1", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.dcache.cval1", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.icache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
{ "th.icache.ialls", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
{ "th.icache.ipa", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.icache.iva", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
|
||||
{ "th.l2cache.call", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
{ "th.l2cache.ciall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
{ "th.l2cache.iall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
/* XTheadCondMov */
|
||||
{ "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
|
||||
{ "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
|
||||
/* XTheadFMemIdx */
|
||||
{ "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
/* XTheadFmv */
|
||||
{ "th.fmv.hw.x", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
|
||||
{ "th.fmv.x.hw", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
|
||||
/* XTheadMac */
|
||||
{ "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
|
||||
{ "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
|
||||
{ "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
|
||||
{ "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
|
||||
{ "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
|
||||
{ "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
|
||||
/* XTheadMemIdx */
|
||||
{ "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 },
|
||||
{ "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.lhuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.lhuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.lwuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.lwuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 },
|
||||
{ "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 },
|
||||
/* XTheadMemPair */
|
||||
{ "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
|
||||
{ "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 },
|
||||
/* XTheadSync */
|
||||
{ "th.sfence.vmas", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
|
||||
{ "th.sync", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
{ "th.sync.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
{ "th.sync.is", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
{ "th.sync.s", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
};
|
||||
|
||||
void decode_xtheadba(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
|
|
@ -27,7 +262,7 @@ const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
|
|||
case 0b0000000:
|
||||
case 0b0000001:
|
||||
case 0b0000010:
|
||||
case 0b0000011: return &op_th_addsl;
|
||||
case 0b0000011: op = rv_op_th_addsl; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -37,12 +272,13 @@ const rv_opcode_data *decode_xtheadba(rv_decode *dec, rv_isa isa)
|
|||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
|
||||
void decode_xtheadbb(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
|
|
@ -52,41 +288,39 @@ const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
|
|||
switch ((inst >> 12) & 0b111) {
|
||||
case 1:
|
||||
switch ((inst >> 25) & 0b1111111) {
|
||||
case 0b0001010: return &op_th_srriw;
|
||||
case 0b0001010: op = rv_op_th_srriw; break;
|
||||
case 0b1000000:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_tstnbz;
|
||||
op = rv_op_th_tstnbz;
|
||||
}
|
||||
break;
|
||||
case 0b1000001:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_rev;
|
||||
op = rv_op_th_rev;
|
||||
}
|
||||
break;
|
||||
case 0b1000010:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_ff0;
|
||||
op = rv_op_th_ff0;
|
||||
}
|
||||
break;
|
||||
case 0b1000011:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_ff1;
|
||||
op = rv_op_th_ff1;
|
||||
}
|
||||
break;
|
||||
case 0b1000100:
|
||||
case 0b1001000:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_revw;
|
||||
op = rv_op_th_revw;
|
||||
}
|
||||
break;
|
||||
case 0b0001000:
|
||||
case 0b0001001:
|
||||
return &op_th_srri;
|
||||
break;
|
||||
case 0b0000100:
|
||||
case 0b0000101: op = rv_op_th_srri; break;
|
||||
}
|
||||
break;
|
||||
case 2: return &op_th_ext;
|
||||
case 3: return &op_th_extu;
|
||||
case 2: op = rv_op_th_ext; break;
|
||||
case 3: op = rv_op_th_extu; break;
|
||||
}
|
||||
break;
|
||||
/* custom-0 */
|
||||
|
|
@ -94,12 +328,13 @@ const rv_opcode_data *decode_xtheadbb(rv_decode *dec, rv_isa isa)
|
|||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
|
||||
void decode_xtheadbs(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
|
|
@ -109,7 +344,7 @@ const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
|
|||
switch ((inst >> 12) & 0b111) {
|
||||
case 1:
|
||||
switch ((inst >> 26) & 0b111111) {
|
||||
case 0b100010: return &op_th_tst;
|
||||
case 0b100010: op = rv_op_th_tst; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -119,12 +354,13 @@ const rv_opcode_data *decode_xtheadbs(rv_decode *dec, rv_isa isa)
|
|||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
|
||||
void decode_xtheadcmo(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
|
|
@ -136,55 +372,55 @@ const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
|
|||
switch ((inst >> 20 & 0b111111111111)) {
|
||||
case 0b000000000001:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_dcache_call;
|
||||
op = rv_op_th_dcache_call;
|
||||
}
|
||||
break;
|
||||
case 0b000000000011:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_dcache_ciall;
|
||||
op = rv_op_th_dcache_ciall;
|
||||
}
|
||||
break;
|
||||
case 0b000000000010:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_dcache_iall;
|
||||
op = rv_op_th_dcache_iall;
|
||||
}
|
||||
break;
|
||||
case 0b000000101001: return &op_th_dcache_cpa;
|
||||
case 0b000000101011: return &op_th_dcache_cipa;
|
||||
case 0b000000101010: return &op_th_dcache_ipa;
|
||||
case 0b000000100101: return &op_th_dcache_cva;
|
||||
case 0b000000100111: return &op_th_dcache_civa;
|
||||
case 0b000000100110: return &op_th_dcache_iva;
|
||||
case 0b000000100001: return &op_th_dcache_csw;
|
||||
case 0b000000100011: return &op_th_dcache_cisw;
|
||||
case 0b000000100010: return &op_th_dcache_isw;
|
||||
case 0b000000101000: return &op_th_dcache_cpal1;
|
||||
case 0b000000100100: return &op_th_dcache_cval1;
|
||||
case 0b000000101001: op = rv_op_th_dcache_cpa; break;
|
||||
case 0b000000101011: op = rv_op_th_dcache_cipa; break;
|
||||
case 0b000000101010: op = rv_op_th_dcache_ipa; break;
|
||||
case 0b000000100101: op = rv_op_th_dcache_cva; break;
|
||||
case 0b000000100111: op = rv_op_th_dcache_civa; break;
|
||||
case 0b000000100110: op = rv_op_th_dcache_iva; break;
|
||||
case 0b000000100001: op = rv_op_th_dcache_csw; break;
|
||||
case 0b000000100011: op = rv_op_th_dcache_cisw; break;
|
||||
case 0b000000100010: op = rv_op_th_dcache_isw; break;
|
||||
case 0b000000101000: op = rv_op_th_dcache_cpal1; break;
|
||||
case 0b000000100100: op = rv_op_th_dcache_cval1; break;
|
||||
case 0b000000010000:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_icache_iall;
|
||||
op = rv_op_th_icache_iall;
|
||||
}
|
||||
break;
|
||||
case 0b000000010001:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_icache_ialls;
|
||||
op = rv_op_th_icache_ialls;
|
||||
}
|
||||
break;
|
||||
case 0b000000111000: return &op_th_icache_ipa;
|
||||
case 0b000000110000: return &op_th_icache_iva;
|
||||
case 0b000000111000: op = rv_op_th_icache_ipa; break;
|
||||
case 0b000000110000: op = rv_op_th_icache_iva; break;
|
||||
case 0b000000010101:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_l2cache_call;
|
||||
op = rv_op_th_l2cache_call;
|
||||
}
|
||||
break;
|
||||
case 0b000000010111:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_l2cache_ciall;
|
||||
op = rv_op_th_l2cache_ciall;
|
||||
}
|
||||
break;
|
||||
case 0b000000010110:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_l2cache_iall;
|
||||
op = rv_op_th_l2cache_iall;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -196,12 +432,13 @@ const rv_opcode_data *decode_xtheadcmo(rv_decode *dec, rv_isa isa)
|
|||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
|
||||
void decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
|
|
@ -211,8 +448,8 @@ const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
|
|||
switch ((inst >> 12) & 0b111) {
|
||||
case 1:
|
||||
switch ((inst >> 25) & 0b1111111) {
|
||||
case 0b0100000: return &op_th_mveqz;
|
||||
case 0b0100001: return &op_th_mvnez;
|
||||
case 0b0100000: op = rv_op_th_mveqz; break;
|
||||
case 0b0100001: op = rv_op_th_mvnez; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -222,12 +459,13 @@ const rv_opcode_data *decode_xtheadcondmov(rv_decode *dec, rv_isa isa)
|
|||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
|
||||
void decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
|
|
@ -237,18 +475,18 @@ const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
|
|||
switch ((inst >> 12) & 0b111) {
|
||||
case 6:
|
||||
switch ((inst >> 27) & 0b11111) {
|
||||
case 8: return &op_th_flrw;
|
||||
case 10: return &op_th_flurw;
|
||||
case 12: return &op_th_flrd;
|
||||
case 14: return &op_th_flurd;
|
||||
case 8: op = rv_op_th_flrw; break;
|
||||
case 10: op = rv_op_th_flurw; break;
|
||||
case 12: op = rv_op_th_flrd; break;
|
||||
case 14: op = rv_op_th_flurd; break;
|
||||
}
|
||||
break;
|
||||
case 7:
|
||||
switch ((inst >> 27) & 0b11111) {
|
||||
case 8: return &op_th_fsrw;
|
||||
case 10: return &op_th_fsurw;
|
||||
case 12: return &op_th_fsrd;
|
||||
case 14: return &op_th_fsurd;
|
||||
case 8: op = rv_op_th_fsrw; break;
|
||||
case 10: op = rv_op_th_fsurw; break;
|
||||
case 12: op = rv_op_th_fsrd; break;
|
||||
case 14: op = rv_op_th_fsurd; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -258,12 +496,13 @@ const rv_opcode_data *decode_xtheadfmemidx(rv_decode *dec, rv_isa isa)
|
|||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
|
||||
void decode_xtheadfmv(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
|
|
@ -275,12 +514,12 @@ const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
|
|||
switch ((inst >> 25) & 0b1111111) {
|
||||
case 0b1010000:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_fmv_hw_x;
|
||||
op = rv_op_th_fmv_hw_x;
|
||||
}
|
||||
break;
|
||||
case 0b1100000:
|
||||
if (((inst >> 20) & 0b11111) == 0) {
|
||||
return &op_th_fmv_x_hw;
|
||||
op = rv_op_th_fmv_x_hw;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -292,12 +531,13 @@ const rv_opcode_data *decode_xtheadfmv(rv_decode *dec, rv_isa isa)
|
|||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
|
||||
void decode_xtheadmac(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
|
|
@ -307,12 +547,12 @@ const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
|
|||
switch ((inst >> 12) & 0b111) {
|
||||
case 1:
|
||||
switch ((inst >> 25) & 0b1111111) {
|
||||
case 0b0010000: return &op_th_mula;
|
||||
case 0b0010001: return &op_th_muls;
|
||||
case 0b0010010: return &op_th_mulaw;
|
||||
case 0b0010011: return &op_th_mulsw;
|
||||
case 0b0010100: return &op_th_mulah;
|
||||
case 0b0010101: return &op_th_mulsh;
|
||||
case 0b0010000: op = rv_op_th_mula; break;
|
||||
case 0b0010001: op = rv_op_th_muls; break;
|
||||
case 0b0010010: op = rv_op_th_mulaw; break;
|
||||
case 0b0010011: op = rv_op_th_mulsw; break;
|
||||
case 0b0010100: op = rv_op_th_mulah; break;
|
||||
case 0b0010101: op = rv_op_th_mulsh; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -322,12 +562,13 @@ const rv_opcode_data *decode_xtheadmac(rv_decode *dec, rv_isa isa)
|
|||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
|
||||
void decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
|
|
@ -337,54 +578,54 @@ const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
|
|||
switch ((inst >> 12) & 0b111) {
|
||||
case 4:
|
||||
switch ((inst >> 27) & 0b11111) {
|
||||
case 0: return &op_th_lrb;
|
||||
case 1: return &op_th_lbib;
|
||||
case 2: return &op_th_lurb;
|
||||
case 3: return &op_th_lbia;
|
||||
case 4: return &op_th_lrh;
|
||||
case 5: return &op_th_lhib;
|
||||
case 6: return &op_th_lurh;
|
||||
case 7: return &op_th_lhia;
|
||||
case 8: return &op_th_lrw;
|
||||
case 9: return &op_th_lwib;
|
||||
case 10: return &op_th_lurw;
|
||||
case 11: return &op_th_lwia;
|
||||
case 12: return &op_th_lrd;
|
||||
case 13: return &op_th_ldib;
|
||||
case 14: return &op_th_lurd;
|
||||
case 15: return &op_th_ldia;
|
||||
case 16: return &op_th_lrbu;
|
||||
case 17: return &op_th_lbuib;
|
||||
case 18: return &op_th_lurbu;
|
||||
case 19: return &op_th_lbuia;
|
||||
case 20: return &op_th_lrhu;
|
||||
case 21: return &op_th_lhuib;
|
||||
case 22: return &op_th_lurhu;
|
||||
case 23: return &op_th_lhuia;
|
||||
case 24: return &op_th_lrwu;
|
||||
case 25: return &op_th_lwuib;
|
||||
case 26: return &op_th_lurwu;
|
||||
case 27: return &op_th_lwuia;
|
||||
case 0: op = rv_op_th_lrb; break;
|
||||
case 1: op = rv_op_th_lbib; break;
|
||||
case 2: op = rv_op_th_lurb; break;
|
||||
case 3: op = rv_op_th_lbia; break;
|
||||
case 4: op = rv_op_th_lrh; break;
|
||||
case 5: op = rv_op_th_lhib; break;
|
||||
case 6: op = rv_op_th_lurh; break;
|
||||
case 7: op = rv_op_th_lhia; break;
|
||||
case 8: op = rv_op_th_lrw; break;
|
||||
case 9: op = rv_op_th_lwib; break;
|
||||
case 10: op = rv_op_th_lurw; break;
|
||||
case 11: op = rv_op_th_lwia; break;
|
||||
case 12: op = rv_op_th_lrd; break;
|
||||
case 13: op = rv_op_th_ldib; break;
|
||||
case 14: op = rv_op_th_lurd; break;
|
||||
case 15: op = rv_op_th_ldia; break;
|
||||
case 16: op = rv_op_th_lrbu; break;
|
||||
case 17: op = rv_op_th_lbuib; break;
|
||||
case 18: op = rv_op_th_lurbu; break;
|
||||
case 19: op = rv_op_th_lbuia; break;
|
||||
case 20: op = rv_op_th_lrhu; break;
|
||||
case 21: op = rv_op_th_lhuib; break;
|
||||
case 22: op = rv_op_th_lurhu; break;
|
||||
case 23: op = rv_op_th_lhuia; break;
|
||||
case 24: op = rv_op_th_lrwu; break;
|
||||
case 25: op = rv_op_th_lwuib; break;
|
||||
case 26: op = rv_op_th_lurwu; break;
|
||||
case 27: op = rv_op_th_lwuia; break;
|
||||
}
|
||||
break;
|
||||
case 5:
|
||||
switch ((inst >> 27) & 0b11111) {
|
||||
case 0: return &op_th_srb;
|
||||
case 1: return &op_th_sbib;
|
||||
case 2: return &op_th_surb;
|
||||
case 3: return &op_th_sbia;
|
||||
case 4: return &op_th_srh;
|
||||
case 5: return &op_th_shib;
|
||||
case 6: return &op_th_surh;
|
||||
case 7: return &op_th_shia;
|
||||
case 8: return &op_th_srw;
|
||||
case 9: return &op_th_swib;
|
||||
case 10: return &op_th_surw;
|
||||
case 11: return &op_th_swia;
|
||||
case 12: return &op_th_srd;
|
||||
case 13: return &op_th_sdib;
|
||||
case 14: return &op_th_surd;
|
||||
case 15: return &op_th_sdia;
|
||||
case 0: op = rv_op_th_srb; break;
|
||||
case 1: op = rv_op_th_sbib; break;
|
||||
case 2: op = rv_op_th_surb; break;
|
||||
case 3: op = rv_op_th_sbia; break;
|
||||
case 4: op = rv_op_th_srh; break;
|
||||
case 5: op = rv_op_th_shib; break;
|
||||
case 6: op = rv_op_th_surh; break;
|
||||
case 7: op = rv_op_th_shia; break;
|
||||
case 8: op = rv_op_th_srw; break;
|
||||
case 9: op = rv_op_th_swib; break;
|
||||
case 10: op = rv_op_th_surw; break;
|
||||
case 11: op = rv_op_th_swia; break;
|
||||
case 12: op = rv_op_th_srd; break;
|
||||
case 13: op = rv_op_th_sdib; break;
|
||||
case 14: op = rv_op_th_surd; break;
|
||||
case 15: op = rv_op_th_sdia; break;
|
||||
}
|
||||
break;
|
||||
break;
|
||||
|
|
@ -395,12 +636,13 @@ const rv_opcode_data *decode_xtheadmemidx(rv_decode *dec, rv_isa isa)
|
|||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
|
||||
void decode_xtheadmempair(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
|
|
@ -410,15 +652,15 @@ const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
|
|||
switch ((inst >> 12) & 0b111) {
|
||||
case 4:
|
||||
switch ((inst >> 27) & 0b11111) {
|
||||
case 28: return &op_th_lwd;
|
||||
case 30: return &op_th_lwud;
|
||||
case 31: return &op_th_ldd;
|
||||
case 28: op = rv_op_th_lwd; break;
|
||||
case 30: op = rv_op_th_lwud; break;
|
||||
case 31: op = rv_op_th_ldd; break;
|
||||
}
|
||||
break;
|
||||
case 5:
|
||||
switch ((inst >> 27) & 0b11111) {
|
||||
case 28: return &op_th_swd;
|
||||
case 31: return &op_th_sdd;
|
||||
case 28: op = rv_op_th_swd; break;
|
||||
case 31: op = rv_op_th_sdd; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -428,12 +670,13 @@ const rv_opcode_data *decode_xtheadmempair(rv_decode *dec, rv_isa isa)
|
|||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
||||
const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
|
||||
void decode_xtheadsync(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
|
|
@ -443,13 +686,13 @@ const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
|
|||
switch ((inst >> 12) & 0b111) {
|
||||
case 0:
|
||||
switch ((inst >> 25) & 0b1111111) {
|
||||
case 0b0000010: return &op_th_sfence_vmas;
|
||||
case 0b0000010: op = rv_op_th_sfence_vmas; break;
|
||||
case 0b0000000:
|
||||
switch ((inst >> 20) & 0b11111) {
|
||||
case 0b11000: return &op_th_sync;
|
||||
case 0b11010: return &op_th_sync_i;
|
||||
case 0b11011: return &op_th_sync_is;
|
||||
case 0b11001: return &op_th_sync_s;
|
||||
case 0b11000: op = rv_op_th_sync; break;
|
||||
case 0b11010: op = rv_op_th_sync_i; break;
|
||||
case 0b11011: op = rv_op_th_sync_is; break;
|
||||
case 0b11001: op = rv_op_th_sync_s; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -461,5 +704,5 @@ const rv_opcode_data *decode_xtheadsync(rv_decode *dec, rv_isa isa)
|
|||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,16 +11,18 @@
|
|||
|
||||
#include "disas/riscv.h"
|
||||
|
||||
const rv_opcode_data *decode_xtheadba(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadbb(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadbs(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadcmo(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadcondmov(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadfmemidx(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadfmv(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadmac(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadmemidx(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadmempair(rv_decode *, rv_isa);
|
||||
const rv_opcode_data *decode_xtheadsync(rv_decode *, rv_isa);
|
||||
extern const rv_opcode_data xthead_opcode_data[];
|
||||
|
||||
void decode_xtheadba(rv_decode *, rv_isa);
|
||||
void decode_xtheadbb(rv_decode *, rv_isa);
|
||||
void decode_xtheadbs(rv_decode *, rv_isa);
|
||||
void decode_xtheadcmo(rv_decode *, rv_isa);
|
||||
void decode_xtheadcondmov(rv_decode *, rv_isa);
|
||||
void decode_xtheadfmemidx(rv_decode *, rv_isa);
|
||||
void decode_xtheadfmv(rv_decode *, rv_isa);
|
||||
void decode_xtheadmac(rv_decode *, rv_isa);
|
||||
void decode_xtheadmemidx(rv_decode *, rv_isa);
|
||||
void decode_xtheadmempair(rv_decode *, rv_isa);
|
||||
void decode_xtheadsync(rv_decode *, rv_isa);
|
||||
|
||||
#endif /* DISAS_RISCV_XTHEAD_H */
|
||||
|
|
|
|||
|
|
@ -1,2 +0,0 @@
|
|||
OP(vt_maskc, "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
OP(vt_maskcn, "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2)
|
||||
|
|
@ -8,26 +8,35 @@
|
|||
#include "disas/riscv.h"
|
||||
#include "disas/riscv-xventana.h"
|
||||
|
||||
#define OP(N, ...) static const rv_opcode_data op_##N = { __VA_ARGS__ };
|
||||
#include "riscv-xventana-op.c.inc"
|
||||
#undef OP
|
||||
typedef enum {
|
||||
/* 0 is reserved for rv_op_illegal. */
|
||||
ventana_op_vt_maskc = 1,
|
||||
ventana_op_vt_maskcn = 2,
|
||||
} rv_ventana_op;
|
||||
|
||||
const rv_opcode_data *decode_xventanacondops(rv_decode *dec, rv_isa isa)
|
||||
const rv_opcode_data ventana_opcode_data[] = {
|
||||
{ "vt.illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
|
||||
{ "vt.maskc", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
|
||||
{ "vt.maskcn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
|
||||
};
|
||||
|
||||
void decode_xventanacondops(rv_decode *dec, rv_isa isa)
|
||||
{
|
||||
rv_inst inst = dec->inst;
|
||||
rv_opcode op = rv_op_illegal;
|
||||
|
||||
switch (((inst >> 0) & 0b11)) {
|
||||
case 3:
|
||||
switch (((inst >> 2) & 0b11111)) {
|
||||
case 30:
|
||||
switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
|
||||
case 6: return &op_vt_maskc;
|
||||
case 7: return &op_vt_maskcn;
|
||||
case 6: op = ventana_op_vt_maskc; break;
|
||||
case 7: op = ventana_op_vt_maskcn; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
dec->op = op;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,6 +11,8 @@
|
|||
|
||||
#include "disas/riscv.h"
|
||||
|
||||
const rv_opcode_data *decode_xventanacondops(rv_decode*, rv_isa);
|
||||
extern const rv_opcode_data ventana_opcode_data[];
|
||||
|
||||
void decode_xventanacondops(rv_decode*, rv_isa);
|
||||
|
||||
#endif /* DISAS_RISCV_XVENTANA_H */
|
||||
|
|
|
|||
5263
disas/riscv.c
5263
disas/riscv.c
File diff suppressed because it is too large
Load diff
|
|
@ -11,7 +11,7 @@
|
|||
|
||||
/* types */
|
||||
|
||||
typedef uint32_t rv_inst;
|
||||
typedef uint64_t rv_inst;
|
||||
typedef uint16_t rv_opcode;
|
||||
|
||||
/* enums */
|
||||
|
|
@ -84,6 +84,15 @@ typedef enum {
|
|||
rvc_imm_eq_zero,
|
||||
rvc_imm_eq_n1,
|
||||
rvc_imm_eq_p1,
|
||||
rvc_csr_eq_0x001,
|
||||
rvc_csr_eq_0x002,
|
||||
rvc_csr_eq_0x003,
|
||||
rvc_csr_eq_0xc00,
|
||||
rvc_csr_eq_0xc01,
|
||||
rvc_csr_eq_0xc02,
|
||||
rvc_csr_eq_0xc80,
|
||||
rvc_csr_eq_0xc81,
|
||||
rvc_csr_eq_0xc82,
|
||||
} rvc_constraint;
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -140,7 +149,6 @@ typedef enum {
|
|||
rv_codec_v_r,
|
||||
rv_codec_v_ldst,
|
||||
rv_codec_v_i,
|
||||
rv_codec_v_i_u,
|
||||
rv_codec_vsetvli,
|
||||
rv_codec_vsetivli,
|
||||
rv_codec_vror_vi,
|
||||
|
|
@ -159,34 +167,36 @@ typedef enum {
|
|||
rv_codec_r2_imm2_imm5,
|
||||
rv_codec_fli,
|
||||
rv_codec_lp,
|
||||
rv_codec_cmop,
|
||||
rv_codec_cmop_ss,
|
||||
rv_codec_mop_r,
|
||||
rv_codec_mop_rr,
|
||||
} rv_codec;
|
||||
|
||||
/* structures */
|
||||
|
||||
typedef struct rv_opcode_data rv_opcode_data;
|
||||
|
||||
typedef struct {
|
||||
const rv_opcode_data *op;
|
||||
const int op;
|
||||
const rvc_constraint *constraints;
|
||||
} rv_comp_data;
|
||||
|
||||
struct rv_opcode_data {
|
||||
const char *name;
|
||||
rv_codec codec;
|
||||
const char *format;
|
||||
typedef struct {
|
||||
const char * const name;
|
||||
const rv_codec codec;
|
||||
const char * const format;
|
||||
const rv_comp_data *pseudo;
|
||||
};
|
||||
const short decomp_rv32;
|
||||
const short decomp_rv64;
|
||||
const short decomp_rv128;
|
||||
const short decomp_data;
|
||||
} rv_opcode_data;
|
||||
|
||||
typedef struct {
|
||||
const RISCVCPUConfig *cfg;
|
||||
uint64_t pc;
|
||||
uint64_t inst;
|
||||
const rv_opcode_data *opcode_data;
|
||||
int32_t imm;
|
||||
int32_t imm1;
|
||||
uint16_t op;
|
||||
uint8_t codec;
|
||||
uint8_t rd;
|
||||
uint8_t rs1;
|
||||
uint8_t rs2;
|
||||
|
|
@ -203,6 +213,14 @@ typedef struct {
|
|||
uint8_t rlist;
|
||||
} rv_decode;
|
||||
|
||||
enum {
|
||||
rv_op_illegal = 0
|
||||
};
|
||||
|
||||
enum {
|
||||
rvcd_imm_nz = 0x1
|
||||
};
|
||||
|
||||
/* instruction formats */
|
||||
|
||||
#define rv_fmt_none "O\t"
|
||||
|
|
@ -287,8 +305,5 @@ typedef struct {
|
|||
#define rv_fmt_rd_rs1_immh_imml_addr "O\t0,(1),i,j"
|
||||
#define rv_fmt_rd2_imm "O\t0,2,(1),i"
|
||||
#define rv_fmt_fli "O\t3,h"
|
||||
#define rv_fmt_cmop "O.i"
|
||||
#define rv_fmt_mop_r "O.i\t0,1"
|
||||
#define rv_fmt_mop_rr "O.i\t0,1,2"
|
||||
|
||||
#endif /* DISAS_RISCV_H */
|
||||
|
|
|
|||
|
|
@ -1,55 +0,0 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
Hexagon L2 Vectored Interrupt Controller
|
||||
========================================
|
||||
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
+-------------+ +----------------------+
|
||||
| l2vic | | hexagon core |
|
||||
| | | |
|
||||
IRQ in ---->| | | |
|
||||
IRQ in ---->| VID0 -|----------------->| irq2 |
|
||||
... ---->| | | | |
|
||||
IRQ in ---->| | | v |
|
||||
| ... | | <int steering> |
|
||||
| | | / | | \ |
|
||||
IRQ in ---->| | | t0 t1 t2 t3 ...|
|
||||
IRQ in ---->| VIDN -| | |
|
||||
... ---->| | | |
|
||||
IRQ in ---->| | | Global SREG File |
|
||||
| | | |
|
||||
| State | | |
|
||||
| [ ] <--|==================|==> [ VID ] |
|
||||
| [ ] <--|==================|==> [ VID1 ] |
|
||||
| | | |
|
||||
+-------------+ +----------------------+
|
||||
|
||||
L2VIC/Core Integration
|
||||
----------------------
|
||||
|
||||
* hexagon core supports 8 external interrupt sources
|
||||
* l2vic supports 1024 input interrupts mapped among 4 output interrupts
|
||||
* l2vic has four output signals: { VID0, VID1, VID2, VID3 }
|
||||
* l2vic device has a bank of registers per-VID that can be used to query
|
||||
the status or assert new interrupts.
|
||||
* Interrupts are 'steered' to threads based on { thread priority, 'EX' state,
|
||||
thread interrupt mask, thread interrupt enable, global interrupt enable,
|
||||
etc. }.
|
||||
* Any hardware thread could conceivably handle any input interrupt, dependent
|
||||
on state.
|
||||
* The system register transfer instruction can read the VID0-VID3 values from
|
||||
the l2vic when reading from hexagon core system registers "VID" and "VID1".
|
||||
* When l2vic VID0 has multiple active interrupts, it pulses the VID0 output
|
||||
IRQ and stores the IRQ number for the VID0 register field. Only after this
|
||||
interrupt is cleared can the l2vic pulse the VID0 output IRQ again and provide
|
||||
the next interrupt number on the VID0 register.
|
||||
* The ``ciad`` instruction clears the l2vic input interrupt and un-disables the
|
||||
core interrupt. If some/an l2vic VID0 interrupt is pending when this occurs,
|
||||
the next interrupt should fire and any subsequent reads of the VID register
|
||||
should reflect the newly raised interrupt.
|
||||
* In QEMU, on an external interrupt or an unmasked-pending interrupt,
|
||||
all vCPUs are triggered (has_work==true) and each will grab the IO lock
|
||||
while considering the steering logic to determine whether they're the thread
|
||||
that must handle the interrupt.
|
||||
|
|
@ -15,7 +15,6 @@ Details about QEMU's various subsystems including how to add features to them.
|
|||
clocks
|
||||
ebpf_rss
|
||||
hexagon-sys
|
||||
hexagon-l2vic
|
||||
migration/index
|
||||
multi-process
|
||||
reset
|
||||
|
|
|
|||
|
|
@ -21,15 +21,19 @@ invokes rustc directly, building static libraries that are then linked
|
|||
together with the C code. This is completely automatic when you run
|
||||
``make`` or ``ninja``.
|
||||
|
||||
However, Meson is able to consume ``Cargo.toml`` files and tries
|
||||
to be easy to use for people who are accustomed to the more "normal"
|
||||
Cargo-based development workflow. In the case of QEMU, in addition,
|
||||
it is possible to use ``cargo`` for common Rust-specific coding
|
||||
tasks, in particular to invoke ``clippy``, ``rustfmt`` and ``rustdoc``.
|
||||
However, QEMU's build system also tries to be easy to use for people who
|
||||
are accustomed to the more "normal" Cargo-based development workflow.
|
||||
In particular:
|
||||
|
||||
* the set of warnings and lints that are used to build QEMU always
|
||||
comes from the ``rust/Cargo.toml`` workspace file
|
||||
|
||||
* it is also possible to use ``cargo`` for common Rust-specific coding
|
||||
tasks, in particular to invoke ``clippy``, ``rustfmt`` and ``rustdoc``.
|
||||
|
||||
To this end, QEMU includes a ``build.rs`` build script that picks up
|
||||
generated sources from QEMU's build directory and puts it in Cargo's
|
||||
output directory (typically ``target/``). A vanilla invocation
|
||||
output directory (typically ``rust/target/``). A vanilla invocation
|
||||
of Cargo will complain that it cannot find the generated sources,
|
||||
which can be fixed in different ways:
|
||||
|
||||
|
|
@ -462,38 +466,63 @@ Adding dependencies
|
|||
Generally, the set of dependent crates is kept small. Think twice before
|
||||
adding a new external crate, especially if it comes with a large set of
|
||||
dependencies itself. Sometimes QEMU only needs a small subset of the
|
||||
functionality; see for example QEMU's ``assertions`` module. Also,
|
||||
choose a version of the crate that works with QEMU's minimum supported
|
||||
Rust version (|msrv|).
|
||||
functionality; see for example QEMU's ``assertions`` module.
|
||||
|
||||
On top of this recommendation, adding external crates to QEMU is a
|
||||
slightly complicated process, mostly due to the need to teach Meson how
|
||||
to download them. While QEMU uses Meson's support for parsing ``Cargo.toml``
|
||||
files, it ships ``.wrap`` files instead of using ``Cargo.lock``; this way,
|
||||
distros can adjust the set of dependencies to the exact versions they use.
|
||||
The versions specified in QEMU's ``Cargo.lock`` must be the same as the
|
||||
one in the wrap file.
|
||||
to build them. While Meson has initial support for parsing ``Cargo.lock``
|
||||
files, it is still highly experimental and is therefore not used.
|
||||
|
||||
The wrap file must be named ``NAME-SEMVER-rs.wrap``, where ``NAME``
|
||||
Therefore, external crates must be added as subprojects for Meson to
|
||||
learn how to build them, as well as to the relevant ``Cargo.toml`` files.
|
||||
The versions specified in ``rust/Cargo.lock`` must be the same as the
|
||||
subprojects; note that the ``rust/`` directory forms a Cargo `workspace`__,
|
||||
and therefore there is a single lock file for the whole build.
|
||||
|
||||
__ https://doc.rust-lang.org/cargo/reference/workspaces.html#virtual-workspace
|
||||
|
||||
Choose a version of the crate that works with QEMU's minimum supported
|
||||
Rust version (|msrv|).
|
||||
|
||||
Second, a new ``wrap`` file must be added to teach Meson how to download the
|
||||
crate. The wrap file must be named ``NAME-SEMVER-rs.wrap``, where ``NAME``
|
||||
is the name of the crate and ``SEMVER`` is the version up to and including the
|
||||
first non-zero number. For example, a crate with version ``0.2.3`` will use
|
||||
``0.2`` for its ``SEMVER``, while a crate with version ``1.0.84`` will use ``1``.
|
||||
|
||||
Usually, Meson is able to figure out how to build the crate, and also handles
|
||||
cross compilation correctly. For crates that have a ``build.rs`` file,
|
||||
equivalent rules must be added to
|
||||
``subprojects/packagefiles/NAME-SEMVER-rs/meson/meson.build``.
|
||||
The file can modify the ``extra_args`` and ``extra_deps`` variables,
|
||||
which contain respectively the compiler arguments and external dependencies
|
||||
for the crate.
|
||||
Third, the Meson rules to build the crate must be added at
|
||||
``subprojects/NAME-SEMVER-rs/meson.build``. Generally this includes:
|
||||
|
||||
After every change to the ``meson/meson.build`` file you have to update the
|
||||
patched version with ``meson subprojects update --reset ``NAME-SEMVER-rs``.
|
||||
This might be automated in the future.
|
||||
* ``subproject`` and ``dependency`` lines for all dependent crates
|
||||
|
||||
Also, after every change to the file it is strongly suggested to do a dummy
|
||||
change to the ``.wrap`` file (for example adding a comment like ``# version 2``),
|
||||
which will help Meson notice that the subproject is out of date.
|
||||
* a ``static_library`` or ``rust.proc_macro`` line to perform the actual build
|
||||
|
||||
* ``declare_dependency`` and a ``meson.override_dependency`` lines to expose
|
||||
the result to QEMU and to other subprojects
|
||||
|
||||
Remember to add ``native: true`` to ``dependency``, ``static_library`` and
|
||||
``meson.override_dependency`` for dependencies of procedural macros.
|
||||
If a crate is needed in both procedural macros and QEMU binaries, everything
|
||||
apart from ``subproject`` must be duplicated to build both native and
|
||||
non-native versions of the crate.
|
||||
|
||||
It's important to specify the right compiler options. These include:
|
||||
|
||||
* the language edition (which can be found in the ``Cargo.toml`` file)
|
||||
|
||||
* the ``--cfg`` (which have to be "reverse engineered" from the ``build.rs``
|
||||
file of the crate).
|
||||
|
||||
* usually, a ``--cap-lints allow`` argument to hide warnings from rustc
|
||||
or clippy.
|
||||
|
||||
After every change to the ``meson.build`` file you have to update the patched
|
||||
version with ``meson subprojects update --reset ``NAME-SEMVER-rs``. This might
|
||||
be automated in the future.
|
||||
|
||||
Also, after every change to the ``meson.build`` file it is strongly suggested to
|
||||
do a dummy change to the ``.wrap`` file (for example adding a comment like
|
||||
``# version 2``), which will help Meson notice that the subproject is out of date.
|
||||
|
||||
As a last step, add the new subproject to ``scripts/archive-source.sh``,
|
||||
``scripts/make-release`` and ``subprojects/.gitignore``.
|
||||
|
|
|
|||
|
|
@ -317,18 +317,6 @@ Arithmetic
|
|||
pass 0 to *nh* to make a simple zero-extension of *nl*,
|
||||
so overflow should never occur.
|
||||
|
||||
* - smax *t0*, *t1*, *t2*
|
||||
|
||||
umax *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = MAX(*t1*, *t2*), for signed and unsigned integers.
|
||||
|
||||
* - smin *t0*, *t1*, *t2*
|
||||
|
||||
umin *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = MIN(*t1*, *t2*), for signed and unsigned integers.
|
||||
|
||||
Logical
|
||||
-------
|
||||
|
||||
|
|
@ -507,22 +495,6 @@ Misc
|
|||
into 32-bit output *t0*. Depending on the host, this may be a simple shift,
|
||||
or may require additional canonicalization.
|
||||
|
||||
* - revbit8 *dest*, *t1*
|
||||
|
||||
- | Reverse the 8 bits within each byte of input *t1* with
|
||||
| output in *dest*; the byte order is unchanged.
|
||||
|
||||
* - revbit32 *dest*, *t1*, *flags*
|
||||
|
||||
- | Reverse the 32 bits of the lower 32 bits of input *t1*
|
||||
| with output in *dest*. On TCG_TYPE_I64, *flags* control
|
||||
| any required sign or zero extension of the result in
|
||||
| the same way as for bswap32.
|
||||
| On TCG_TYPE_I32, *flags* should be zero.
|
||||
|
||||
* - revbit64 *dest*, *t1*
|
||||
|
||||
- | Reverse the 64 bits of input *t1* with output in *dest*.
|
||||
|
||||
Conditional moves
|
||||
-----------------
|
||||
|
|
|
|||
|
|
@ -34,7 +34,6 @@ guest hardware that is specific to QEMU.
|
|||
virt-ctlr
|
||||
vmcoreinfo
|
||||
vmgenid
|
||||
vmlaunchupdate
|
||||
rapl-msr
|
||||
rocker
|
||||
riscv-iommu
|
||||
|
|
|
|||
|
|
@ -1,198 +0,0 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
VMLAUNCHUPDATE Interface Specification
|
||||
######################################
|
||||
|
||||
Introduction
|
||||
************
|
||||
|
||||
``VmLaunchUpdate`` is an extension to ``fw-cfg`` that allows guests to replace
|
||||
boot state in their virtual machine using IGVM file container. Through a combination
|
||||
of this ``fw-cfg`` hypervisor interface, an IGVM file containing specific directives
|
||||
and with hypervisor stack knowledge, guests can deterministically replace the launch
|
||||
state for guests. This is useful for environments like SEV-SNP where the
|
||||
launch payload becomes the launch digest. Guests can use vm-launch-update device to
|
||||
provide a measured, full guest payload (BIOS image, kernel, initramfs, kernel
|
||||
command line) to the virtual machine which enables them to easily reason about
|
||||
integrity of the resulting system.
|
||||
It is also to be noted that this mechanism currently works only when the guest was
|
||||
already started with an IGVM file defining its initial launch state. Subsequent
|
||||
guest resets will use the launch state as defined in the guest provided IGVM file,
|
||||
not the file with which the guest was initially started. If the guest was not started
|
||||
with IGVM, writing a new bundle through the ``fw-cfg`` interface has no effect.
|
||||
|
||||
For more information, please see the `KVM Forum 2024 presentation <KVMFORUM_>`__
|
||||
about this work.
|
||||
|
||||
|
||||
.. _KVMFORUM: https://www.youtube.com/watch?v=VCMBxU6tAto
|
||||
|
||||
Base Requirements
|
||||
*****************
|
||||
|
||||
#. **fw-cfg**:
|
||||
The target system must provide a ``fw-cfg`` interface. For x86 based
|
||||
environments, this ``fw-cfg`` interface must be accessible through PIO ports
|
||||
0x510 and 0x511. The ``fw-cfg`` interface does not need to be announced as part
|
||||
of system device tables such as DSDT. The ``fw-cfg`` interface must support the
|
||||
DMA interface. It may only support the DMA interface for write operations.
|
||||
|
||||
#. **IGVM support**:
|
||||
The hypervisor must provide support for parsing and executing the IGVM file bundle.
|
||||
|
||||
#. **Confidential guests**:
|
||||
For confidential guests, the hypervisor must support guest reset. Otherwise, the new
|
||||
boot state provided through IGVM will not be applied.
|
||||
|
||||
The Fw-cfg File
|
||||
***************
|
||||
|
||||
Guests drive vmlaunchupdate through special ``fw-cfg`` files that control its flow
|
||||
followed by a standard system reset operation. When the ``vm-launch-update`` device
|
||||
is available, it provides the following ``fw-cfg`` file:
|
||||
|
||||
* ``etc/vmlaunchupdate`` - It exposes a structure of the following type, all in
|
||||
little-endian format:
|
||||
|
||||
.. code-block:: c
|
||||
:linenos:
|
||||
|
||||
typedef struct {
|
||||
uint16_t version;
|
||||
uint16_t status;
|
||||
|
||||
uint32_t _padding;
|
||||
|
||||
uint64_t capabilities;
|
||||
uint64_t control;
|
||||
|
||||
uint64_t fw_image_addr;
|
||||
uint64_t fw_image_size;
|
||||
|
||||
uint64_t opaque_addr;
|
||||
uint64_t opaque_size;
|
||||
|
||||
} VMLaunchUpdate;
|
||||
|
||||
|
||||
Currently, the ``version`` number (line 2 above) is initialized to the value ``1``.
|
||||
Only IGVM files are supported at present. The ``capabilities`` (line 7) and ``control`` (line 8) both support
|
||||
the following single value:
|
||||
|
||||
* ``VM_LAUNCHUPDATE_FORMAT_IGVM``
|
||||
|
||||
This value is used by the hypervisor to indicate that only IGVM container files are supported.
|
||||
This is set as a part of ``capabilities`` parameter (line 7) in the above structure. This same value
|
||||
is passed by the guest to the hypervisor in the ``control`` parameter (line 8) in the above structure
|
||||
to indicate that the guest passed IGVM file in memory to the hypervisor. The starting guest physical
|
||||
address of the IGVM file in memory is specified in ``fw_image_addr`` and it's length is specified in
|
||||
``fw_image_size`` by the guest. If any other value is passed by the guest in the ``control`` parameter,
|
||||
the write is ignored by the hypervisor.
|
||||
|
||||
Following ``control`` parameters are supported:
|
||||
|
||||
* ``VM_LAUNCHUPDATE_CTL_DISABLE``
|
||||
|
||||
This value is set in the ``control`` parameter by the guest in order to disable this ``fw-cfg``
|
||||
hypervisor interface from further updating the guest launch state with a new IGVM file.
|
||||
|
||||
* ``VM_LAUNCHUPDATE_CTL_HOST_IGVM``
|
||||
|
||||
This value is set in the ``control`` parameter by the guest in order to send request to the
|
||||
hypervisor to initialize the guest using the original host provided IGVM file.
|
||||
It is useful if the guest wanted to update the UKIs present in the ESP and upon
|
||||
reset, use one of the updated UKIs present there. If the guest passed addresses in memory
|
||||
where its own IGVM file is loaded (see below) while also setting this control value, the next
|
||||
reset will load the guest provided IGVM file and a subsequent second reset will restore the original
|
||||
host IGVM. If the guest did not provide any addresses of its own IGVM (the address values are
|
||||
cleared) while setting this control parameter, the immediate next guest reset will load the
|
||||
original host provided IGVM file.
|
||||
|
||||
The combination of the above two ctl interfaces work as
|
||||
follows:
|
||||
|
||||
A) ``CTL_HOST_IGVM`` = off ``CTL_DISABLE`` = off
|
||||
|
||||
Supplied IGVM file replaces the firmware permanently. Updating the
|
||||
firmware again is possible.
|
||||
|
||||
B) ``CTL_HOST_IGVM`` = off ``CTL_DISABLE`` = on
|
||||
|
||||
Supplied IGVM file replaces the firmware permanently. Updating the
|
||||
firmware again is not possible.
|
||||
|
||||
C) ``CTL_HOST_IGVM`` = on ``CTL_DISABLE`` = off
|
||||
|
||||
Supplied IGVM file replaces the firmware for one reset. Resetting
|
||||
again will switch back to the original firmware. Updating the
|
||||
firmware again is possible.
|
||||
|
||||
D) ``CTL_HOST_IGVM`` = on ``CTL_DISABLE`` = on
|
||||
|
||||
Supplied IGVM file replaces the firmware for one reset. Resetting
|
||||
again will switch back to the original firmware. Updating the
|
||||
firmware again is NOT possible.
|
||||
|
||||
``fw_image_addr`` (line 10) is the base guest physical address of the guest memory where the IGVM file of size
|
||||
``fw_image_size`` (line 11) is loaded. ``opaque_addr`` (line 13) and ``opaque_size`` (line 14) are used by
|
||||
the guest for passing data across resets. The contents of this guest memory are preserved across the
|
||||
reset. For confidential guests, this memory region must come from guest shared unencrypted memory.
|
||||
|
||||
``status`` (line 3) is written by the hypervisor and it indicates the result of the IGVM loading operation.
|
||||
A success indicates status code 0. Otherwise a non-zero status code indicates failure. The nature of the
|
||||
failure is indicated by the value of the code.
|
||||
|
||||
Triggering the Launch State Update using IGVM
|
||||
*********************************************
|
||||
|
||||
To initiate the launch update process, the guest issues a standard system reset
|
||||
operation through any of the means implemented by the machine model.
|
||||
|
||||
On a write to the ``etc/vmlaunchupdate`` interface, the hypervisor evaluates whether this
|
||||
hypervisor interface is disabled. If it is, it ignores any writes to this ``fw-cfg`` file
|
||||
by the guest. No updates to initial launch state is performed.
|
||||
|
||||
If the hypervisor interface is enabled, upon write to the ``etc/vmlaunchupdate`` interface,
|
||||
the hypervisor parses the IGVM file bundle passed to it in memory, with starting guest physical
|
||||
address at ``fw_image_addr`` and length ``fw_image_size``. If parsing is successful, it creates
|
||||
a context handle to the IGVM file. If parsing and context loading is successful and there are no
|
||||
errors, ``fw_image_addr`` and ``fw_image_size`` are cleared. The guest can check this in order
|
||||
to determine if the IGVM was successfully parsed and the new context was loaded. If not, the
|
||||
guest can throw error and abort rebooting to new IGVM boot state. Alternatively, the guest can
|
||||
also check the ``status`` code from the ``fw-cfg`` file. A status code of 0 indicates success
|
||||
of the operation. Non-zero status code indicates failure. Exact nature of the failure is
|
||||
indicated by the value of the code. Currently, only two error values are supported:
|
||||
|
||||
* ``VM_LAUNCHUPDATE_LOAD_FAIL`` - defined as value 1 and is set when loading of the IGVM file failed.
|
||||
* ``VM_LAUNCHUPDATE_NOT_IGVM_INIT`` - defined as value 2 and is set when the guest was not started with
|
||||
IGVM file.
|
||||
|
||||
Upon guest reset, the hypervisor executes the IGVM bundle using
|
||||
the context handle, setting the initial launch state of the guest accordingly.
|
||||
If an invalid IGVM file is passed, parsing the file fails and the hypervisor ignores it
|
||||
when ``fw-cfg`` files are written. In this case, the initial launch state
|
||||
is not modified. If invalid addresses are passed, the hypervisor ignores them as well and no
|
||||
new launch state is set.
|
||||
|
||||
The launch state update mechanism works both for confidential and non-confidential
|
||||
guests. In confidential guests, as a part of the reset operation, all existing
|
||||
guest shared memory (shared with the hypervisor) as well as the guest memory region
|
||||
starting with ``opaque_addr`` and length ``opaque_size`` are preserved.
|
||||
The reset causes recreation of the VM context which triggers a fresh
|
||||
measurement of the replaced BIOS region and reset CPU state.
|
||||
|
||||
For non-confidential guests, there is no concept of guest private memory and all the existing
|
||||
guest memory is preserved (this is the default behaviour today - QEMU does not reset/clear
|
||||
guest memory upon reset).
|
||||
|
||||
In both confidential and non-confidential cases, CPU and device state are reset to
|
||||
the reset states specified in IGVM. In confidential environments, the guest
|
||||
always resumes operation in the highest privileged mode available to it (VMPL0 in SEV-SNP).
|
||||
|
||||
Closing Remarks
|
||||
***************
|
||||
The exact content of the memory region specified by starting address ``opaque_addr``
|
||||
and length ``opaque_size`` is guest specific and is hypervisor agnostic. The hypervisor does
|
||||
not care about the contents of this memory region. Therefore, it is not included in this
|
||||
specification. As of writing this document, TDX guests on QEMU does not support IGVM.
|
||||
Therefore, this mechanism cannot be used to change launch state of TDX guests.
|
||||
|
|
@ -188,7 +188,6 @@ the following architecture extensions:
|
|||
- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
|
||||
- FEAT_SME_LUTv2 (Lookup table instructions with 4-bit indices and 8-bit elements)
|
||||
- FEAT_SME_MOP4 (Quarter-tile outer product instructions)
|
||||
- FEAT_SME_TMOP (Structured sparsity outer product instructions)
|
||||
- FEAT_SSVE_AES (Streaming SVE Mode Advanced Encryption Standard and 128-bit polynomial multiply long instructions)
|
||||
- FEAT_SSVE_FEXPA (Streaming FEXPA instruction)
|
||||
- FEAT_SSVE_FP8DOT2 (SVE2 FP8 2-way dot product to half-precision instructions in Streaming SVE mode)
|
||||
|
|
|
|||
|
|
@ -20,18 +20,12 @@ The ``k230`` machine supports the following devices:
|
|||
* Platform-Level Interrupt Controller (PLIC)
|
||||
* 2 K230 Watchdog Timer
|
||||
* 5 UART
|
||||
* K230 DDRC CFG and DDR PHY
|
||||
* System Direct Memory Access (SDMA)
|
||||
* GZIP Decompress Engine (Decomp_gzip)
|
||||
|
||||
Boot options
|
||||
------------
|
||||
The ``k230`` machine supports K230 SDK boot through M-mode U-Boot, which then
|
||||
starts OpenSBI/Linux with ``bootm``. It also supports direct Linux boot.
|
||||
|
||||
The DDRC CFG and DDR PHY models allow the K230 SDK U-Boot SPL to complete DDR
|
||||
initialization before loading the next boot stage.
|
||||
|
||||
K230 SDK Linux kernels use T-HEAD C9xx private MAEE page table attributes. QEMU
|
||||
does not implement MAEE in the generic RISC-V MMU, so such kernels need to be
|
||||
built with standard RISC-V PTE bits before they can boot under QEMU.
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ The ``virt`` machine supports the following devices:
|
|||
* Core Local Interruptor (CLINT)
|
||||
* Platform-Level Interrupt Controller (PLIC)
|
||||
* CFI parallel NOR flash memory
|
||||
* Either 1 or 2 NS16550 compatible UARTs
|
||||
* 1 NS16550 compatible UART
|
||||
* 1 Google Goldfish RTC
|
||||
* 1 SiFive Test device
|
||||
* 8 virtio-mmio transport devices
|
||||
|
|
@ -27,9 +27,6 @@ The hypervisor extension has been enabled for the default CPU, so virtual
|
|||
machines with hypervisor extension can simply be used without explicitly
|
||||
declaring.
|
||||
|
||||
The second UART only exists if a backend is configured explicitly (e.g.
|
||||
with a second ``-serial`` command line option).
|
||||
|
||||
Hardware configuration information
|
||||
----------------------------------
|
||||
|
||||
|
|
|
|||
|
|
@ -133,16 +133,6 @@ an issue as a normal bug.
|
|||
that affect the level 0 QEMU process. While these bugs should be
|
||||
fixed, they will not be triaged as security flaws at this time.
|
||||
|
||||
* **migration/snapshots**. Migration failures and snapshot load
|
||||
failures are considered part of normal operation as long as the
|
||||
source virtual machine and savevm file, respectively, are still
|
||||
functional. Aborting the QEMU process at the migration/snapshot
|
||||
destination is similarly not considered a security issue. The
|
||||
migration stream is assumed to be secure as long as the design
|
||||
principles described in the Architecture section are held, in
|
||||
which case plain manipulation of the stream is not considered as
|
||||
an attack vector.
|
||||
|
||||
* **low severity impact**. As a catch all rule, issues which
|
||||
are judged to have a "low" severity impact on the system will
|
||||
usually not justify handling as security bugs, nor assignment
|
||||
|
|
@ -169,11 +159,10 @@ could allow malicious guests to gain code execution in QEMU. At this point the
|
|||
guest has escaped the virtual machine and is able to act in the context of the
|
||||
QEMU process on the host.
|
||||
|
||||
Guests often interact with other guests and share resources with them.
|
||||
A malicious guest must not gain control of other guests or access
|
||||
their data. Disk image files and network traffic must be protected
|
||||
from other guests, users and processes unless explicitly shared with
|
||||
them by the user.
|
||||
Guests often interact with other guests and share resources with them. A
|
||||
malicious guest must not gain control of other guests or access their data.
|
||||
Disk image files and network traffic must be protected from other guests unless
|
||||
explicitly shared between them by the user.
|
||||
|
||||
Principle of Least Privilege
|
||||
''''''''''''''''''''''''''''
|
||||
|
|
@ -234,9 +223,6 @@ Some Linux distros already ship with UNIX groups for these devices by default.
|
|||
system calls that are not needed by QEMU, thereby reducing the host kernel
|
||||
attack surface.
|
||||
|
||||
- Transport Layer Security (TLS) protocol can be used to ensure authenticity and
|
||||
encryption of the live migration connection where the network is untrusted.
|
||||
|
||||
Sensitive configurations
|
||||
------------------------
|
||||
|
||||
|
|
|
|||
|
|
@ -865,13 +865,12 @@ ERST
|
|||
.name = "nmi",
|
||||
.args_type = "",
|
||||
.params = "",
|
||||
.help = "Inject an NMI, in a machine-specific way",
|
||||
.help = "inject an NMI",
|
||||
.cmd = hmp_nmi,
|
||||
},
|
||||
SRST
|
||||
``nmi``
|
||||
Inject an NMI, in a machine-specific way.
|
||||
Not all machines implement NMI handling.
|
||||
``nmi`` *cpu*
|
||||
Inject an NMI on the default CPU (x86/s390) or all CPUs (ppc64).
|
||||
ERST
|
||||
|
||||
{
|
||||
|
|
@ -929,17 +928,16 @@ ERST
|
|||
|
||||
{
|
||||
.name = "migrate",
|
||||
.args_type = "detach:-d,resume:-r,uri-cpr:-cs,uri:s",
|
||||
.params = "[-d] [-r] [-c uri-cpr] uri",
|
||||
.args_type = "detach:-d,resume:-r,uri:s",
|
||||
.params = "[-d] [-r] uri",
|
||||
.help = "migrate to URI (using -d to not wait for completion)"
|
||||
"\n\t\t\t -r to resume a paused postcopy migration"
|
||||
"\n\t\t\t -c to specify a CPR URI for cpr-transfer mode",
|
||||
"\n\t\t\t -r to resume a paused postcopy migration",
|
||||
.cmd = hmp_migrate,
|
||||
},
|
||||
|
||||
|
||||
SRST
|
||||
``migrate [-d] [-r] [-c uri-cpr]`` *uri*
|
||||
``migrate [-d] [-r]`` *uri*
|
||||
Migrate the VM to *uri*.
|
||||
|
||||
``-d``
|
||||
|
|
@ -947,9 +945,6 @@ SRST
|
|||
query an ongoing migration process, use "info migrate".
|
||||
``-r``
|
||||
Resume a paused postcopy migration.
|
||||
``-c`` *uri-cpr*
|
||||
Specify the CPR URI for cpr-transfer mode. It must be a UNIX domain
|
||||
socket.
|
||||
ERST
|
||||
|
||||
{
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#define CPUINFO_AES (1u << 3)
|
||||
#define CPUINFO_PMULL (1u << 4)
|
||||
#define CPUINFO_BTI (1u << 5)
|
||||
#define CPUINFO_CSSC (1u << 6)
|
||||
|
||||
/* Initialized with a constructor. */
|
||||
extern unsigned cpuinfo;
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#define CPUINFO_ZBS (1u << 3)
|
||||
#define CPUINFO_ZICOND (1u << 4)
|
||||
#define CPUINFO_ZVE64X (1u << 5)
|
||||
#define CPUINFO_ZBKB (1u << 6)
|
||||
|
||||
/* Initialized with a constructor. */
|
||||
extern unsigned cpuinfo;
|
||||
|
|
|
|||
|
|
@ -533,9 +533,7 @@ config ASPEED_SOC
|
|||
bool
|
||||
default y
|
||||
depends on TCG && ARM
|
||||
imply GENERIC_LOADER
|
||||
imply PCI_DEVICES
|
||||
imply E1000E_PCI_EXPRESS
|
||||
select DS1338
|
||||
select FTGMAC100
|
||||
select I2C
|
||||
|
|
@ -553,17 +551,14 @@ config ASPEED_SOC
|
|||
select TMP105
|
||||
select TMP421
|
||||
select EMC141X
|
||||
select OR_IRQ
|
||||
select UNIMP
|
||||
select LED
|
||||
select PMBUS
|
||||
select MAX31785
|
||||
select ADC128D818
|
||||
select FSI_APB2OPB_ASPEED
|
||||
select AT24C
|
||||
select PCI_EXPRESS
|
||||
select PCI_EXPRESS_ASPEED
|
||||
select USB_EHCI_SYSBUS
|
||||
select SDHCI
|
||||
|
||||
config MPS2
|
||||
bool
|
||||
|
|
@ -730,18 +725,3 @@ config ARMSSE
|
|||
select UNIMP
|
||||
select SSE_COUNTER
|
||||
select SSE_TIMER
|
||||
|
||||
config AXIADO_SOC
|
||||
bool
|
||||
select ARM_GIC
|
||||
select CADENCE # UART
|
||||
select AXIADO_CLK
|
||||
select CADENCE_GPIO
|
||||
select AXIADO_SDHCI
|
||||
select UNIMP
|
||||
|
||||
config AXIADO_EVK
|
||||
bool
|
||||
default y
|
||||
depends on TCG && ARM
|
||||
select AXIADO_SOC
|
||||
|
|
|
|||
|
|
@ -409,7 +409,7 @@ static const ARMSSEDeviceInfo sse300_devices[] = {
|
|||
.name = "s32kwatchdog",
|
||||
.type = TYPE_CMSDK_APB_WATCHDOG,
|
||||
.index = 0,
|
||||
.addr = 0x5802e000,
|
||||
.addr = 0x4802e000,
|
||||
.ppc = NO_PPC,
|
||||
.irq = NMI_0,
|
||||
.slowclk = true,
|
||||
|
|
@ -452,7 +452,7 @@ static const ARMSSEDeviceInfo sse300_devices[] = {
|
|||
.name = "CPU0CORE_PPU",
|
||||
.type = TYPE_UNIMPLEMENTED_DEVICE,
|
||||
.index = 2,
|
||||
.addr = 0x58023000,
|
||||
.addr = 0x50023000,
|
||||
.size = 0x1000,
|
||||
.ppc = NO_PPC,
|
||||
.irq = NO_IRQ,
|
||||
|
|
@ -461,7 +461,7 @@ static const ARMSSEDeviceInfo sse300_devices[] = {
|
|||
.name = "MGMT_PPU",
|
||||
.type = TYPE_UNIMPLEMENTED_DEVICE,
|
||||
.index = 3,
|
||||
.addr = 0x58028000,
|
||||
.addr = 0x50028000,
|
||||
.size = 0x1000,
|
||||
.ppc = NO_PPC,
|
||||
.irq = NO_IRQ,
|
||||
|
|
@ -470,7 +470,7 @@ static const ARMSSEDeviceInfo sse300_devices[] = {
|
|||
.name = "DEBUG_PPU",
|
||||
.type = TYPE_UNIMPLEMENTED_DEVICE,
|
||||
.index = 4,
|
||||
.addr = 0x58029000,
|
||||
.addr = 0x50029000,
|
||||
.size = 0x1000,
|
||||
.ppc = NO_PPC,
|
||||
.irq = NO_IRQ,
|
||||
|
|
|
|||
|
|
@ -24,6 +24,10 @@
|
|||
#include "hw/core/qdev-clock.h"
|
||||
#include "system/system.h"
|
||||
|
||||
static struct arm_boot_info aspeed_board_binfo = {
|
||||
.board_id = -1, /* device-tree-only board */
|
||||
};
|
||||
|
||||
#define AST_SMP_MAILBOX_BASE 0x1e6e2180
|
||||
#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
|
||||
#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
|
||||
|
|
@ -202,14 +206,13 @@ static void aspeed_machine_init(MachineState *machine)
|
|||
memory_region_add_subregion(get_system_memory(),
|
||||
AST_SMP_MAILBOX_BASE, smpboot);
|
||||
|
||||
bmc->bootinfo.write_secondary_boot = aspeed_write_smpboot;
|
||||
bmc->bootinfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
|
||||
bmc->bootinfo.smp_loader_start = AST_SMP_MBOX_CODE;
|
||||
aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
|
||||
aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
|
||||
aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
|
||||
}
|
||||
|
||||
bmc->bootinfo.board_id = -1; /* device-tree-only board */
|
||||
bmc->bootinfo.ram_size = machine->ram_size;
|
||||
bmc->bootinfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
|
||||
aspeed_board_binfo.ram_size = machine->ram_size;
|
||||
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
|
||||
|
||||
if (amc->i2c_init) {
|
||||
amc->i2c_init(bmc);
|
||||
|
|
@ -245,7 +248,7 @@ static void aspeed_machine_init(MachineState *machine)
|
|||
aspeed_load_vbootrom(bmc->soc, bios_name, &error_abort);
|
||||
}
|
||||
|
||||
arm_load_kernel(ARM_CPU(first_cpu), machine, &bmc->bootinfo);
|
||||
arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
|
||||
}
|
||||
|
||||
void aspeed_create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
|
||||
|
|
@ -324,7 +327,7 @@ static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
|
|||
int uart_first = aspeed_uart_first(sc->uarts_base);
|
||||
int uart_last = aspeed_uart_last(sc->uarts_base, sc->uarts_num);
|
||||
|
||||
if (sscanf(value, "uart%d", &val) != 1 || val < 0) {
|
||||
if (sscanf(value, "uart%u", &val) != 1) {
|
||||
error_setg(errp, "Bad value for \"uart\" property");
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,14 +1,13 @@
|
|||
/*
|
||||
* Facebook Anacapa
|
||||
*
|
||||
* Copyright (c) 2026 Meta Platforms, Inc. and affiliates.
|
||||
* Copyright (c) Meta Platforms, Inc. and affiliates.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "qapi/error.h"
|
||||
#include "hw/sensor/adc128d818.h"
|
||||
#include "hw/arm/machines-qom.h"
|
||||
#include "hw/arm/aspeed.h"
|
||||
#include "hw/arm/aspeed_soc.h"
|
||||
|
|
@ -16,6 +15,7 @@
|
|||
#include "hw/gpio/pca9552.h"
|
||||
#include "hw/nvram/eeprom_at24c.h"
|
||||
|
||||
/* Anacapa hardware value */
|
||||
#define ANACAPA_BMC_HW_STRAP1 0x00002002
|
||||
#define ANACAPA_BMC_HW_STRAP2 0x00000000
|
||||
#define ANACAPA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
|
||||
|
|
@ -221,17 +221,6 @@ static const uint8_t hpm_brd_id_eeprom[] = {
|
|||
};
|
||||
static const size_t hpm_brd_id_eeprom_len = sizeof(hpm_brd_id_eeprom);
|
||||
|
||||
static void anacapa_add_adc128d818(I2CBus *bus, uint8_t addr,
|
||||
const char *description)
|
||||
{
|
||||
DeviceState *dev = DEVICE(i2c_slave_new(TYPE_ADC128D818, addr));
|
||||
g_autofree char *childname = g_strdup_printf("0x%02x", addr);
|
||||
|
||||
qdev_prop_set_string(dev, "description", description);
|
||||
object_property_add_child(OBJECT(bus), childname, OBJECT(dev));
|
||||
i2c_slave_realize_and_unref(I2C_SLAVE(dev), bus, &error_fatal);
|
||||
}
|
||||
|
||||
static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
|
||||
{
|
||||
/* Reference: aspeed-bmc-facebook-anacapa.dts */
|
||||
|
|
@ -253,7 +242,7 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
|
|||
/* &i2c1 */
|
||||
/* eeprom@50 */
|
||||
at24c_eeprom_init(i2c[1], 0x50, 256 * KiB);
|
||||
/* i2c-mux@70 (PCA9546) - 4 channels, empty */
|
||||
/* i2c-mux@70 (PCA9546) — 4 channels, empty */
|
||||
i2c_slave_create_simple(i2c[1], TYPE_PCA9546, 0x70);
|
||||
|
||||
/* &i2c4 */
|
||||
|
|
@ -270,8 +259,7 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
|
|||
i2c_mux = i2c_slave_create_simple(i2c[8], TYPE_PCA9546, 0x72);
|
||||
|
||||
/* i2c8mux ch0 */
|
||||
/* adc128d818@1f - R-PDB ADC (mode 1: 8 voltage channels) */
|
||||
anacapa_add_adc128d818(pca954x_i2c_get_bus(i2c_mux, 0), 0x1f, "i2c8:0:1f");
|
||||
/* adc128d818@1f — no model */
|
||||
/* pca9555@22 */
|
||||
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0),
|
||||
TYPE_PCA9552, 0x22);
|
||||
|
|
@ -317,7 +305,7 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
|
|||
/* i2c-mux@71 (PCA9548) */
|
||||
i2c_mux = i2c_slave_create_simple(i2c[11], TYPE_PCA9548, 0x71);
|
||||
|
||||
/* i2c11mux ch0-ch4 - empty */
|
||||
/* i2c11mux ch0-ch4 — empty */
|
||||
|
||||
/* i2c11mux ch5 */
|
||||
/* pca9555@22 */
|
||||
|
|
@ -332,8 +320,7 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
|
|||
i2c_mux = i2c_slave_create_simple(i2c[13], TYPE_PCA9548, 0x70);
|
||||
|
||||
/* i2c13mux ch3 */
|
||||
/* adc128d818@1f - MB ADC (mode 1: 8 voltage channels) */
|
||||
anacapa_add_adc128d818(pca954x_i2c_get_bus(i2c_mux, 3), 0x1f, "i2c13:3:1f");
|
||||
/* adc128d818@1f - no model */
|
||||
|
||||
/* i2c13mux ch4 */
|
||||
/* eeprom@51 */
|
||||
|
|
@ -341,7 +328,7 @@ static void anacapa_bmc_i2c_init(AspeedMachineState *bmc)
|
|||
hpm_brd_id_eeprom, hpm_brd_id_eeprom_len);
|
||||
|
||||
/* i2c13mux ch7 */
|
||||
/* nfc@28 - no model */
|
||||
/* nfc@28 — no model */
|
||||
}
|
||||
|
||||
static void aspeed_machine_anacapa_class_init(ObjectClass *oc,
|
||||
|
|
|
|||
|
|
@ -472,16 +472,7 @@ static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
|
|||
|
||||
/* &i2c0 */
|
||||
/* i2c-mux@71 (PCA9546) on i2c0 */
|
||||
i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x71);
|
||||
|
||||
/* i2c0mux0ch0 */
|
||||
/* IOB0 NIC0 temperature-sensor@1f - tmp421 */
|
||||
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0),
|
||||
TYPE_TMP421, 0x1f);
|
||||
/* i2c0mux0ch2 */
|
||||
/* IOB0 NIC1 temperature-sensor@1f - tmp421 */
|
||||
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2),
|
||||
TYPE_TMP421, 0x1f);
|
||||
i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x71);
|
||||
|
||||
/* i2c-mux@72 (PCA9546) on i2c0 */
|
||||
i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x72);
|
||||
|
|
@ -498,16 +489,7 @@ static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
|
|||
i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x73);
|
||||
|
||||
/* i2c-mux@75 (PCA9546) on i2c0 */
|
||||
i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x75);
|
||||
|
||||
/* i2c0mux3ch0 */
|
||||
/* IOB1 NIC0 temperature-sensor@1f - tmp421 */
|
||||
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0),
|
||||
TYPE_TMP421, 0x1f);
|
||||
/* i2c0mux3ch2 */
|
||||
/* IOB1 NIC1 temperature-sensor@1f - tmp421 */
|
||||
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2),
|
||||
TYPE_TMP421, 0x1f);
|
||||
i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x75);
|
||||
|
||||
/* i2c-mux@76 (PCA9546) on i2c0 */
|
||||
i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x76);
|
||||
|
|
@ -551,7 +533,7 @@ static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
|
|||
TYPE_PCA9554, 0x27);
|
||||
/* io_expander6 - pca9555@25 */
|
||||
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6),
|
||||
TYPE_PCA9555, 0x25);
|
||||
TYPE_PCA9552, 0x25);
|
||||
/* eeprom@51 */
|
||||
at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB,
|
||||
osfp_eeprom, osfp_eeprom_len);
|
||||
|
|
@ -562,16 +544,14 @@ static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
|
|||
fio_eeprom, fio_eeprom_len);
|
||||
/* temperature-sensor@4b - tmp75 */
|
||||
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0x4b);
|
||||
/* temperature-sensor@4f - tmp75 (FIO remote) */
|
||||
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0x4f);
|
||||
|
||||
/* &i2c2 */
|
||||
/* io_expander0 - pca9555@20 */
|
||||
i2c_slave_create_simple(i2c[2], TYPE_PCA9555, 0x20);
|
||||
i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x20);
|
||||
/* io_expander0 - pca9555@21 */
|
||||
i2c_slave_create_simple(i2c[2], TYPE_PCA9555, 0x21);
|
||||
i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x21);
|
||||
/* io_expander0 - pca9555@27 */
|
||||
i2c_slave_create_simple(i2c[2], TYPE_PCA9555, 0x27);
|
||||
i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x27);
|
||||
/* eeprom@50 */
|
||||
at24c_eeprom_init(i2c[2], 0x50, 8 * KiB);
|
||||
/* eeprom@51 */
|
||||
|
|
@ -584,17 +564,21 @@ static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
|
|||
/* eeprom@52 */
|
||||
at24c_eeprom_init_rom(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB,
|
||||
hdd_eeprom, hdd_eeprom_len);
|
||||
/* i2c5mux0ch7 - empty */
|
||||
/* i2c5mux0ch7 */
|
||||
/* ina230@40 - no model */
|
||||
/* ina230@41 - no model */
|
||||
/* ina230@44 - no model */
|
||||
/* ina230@45 - no model */
|
||||
|
||||
/* &i2c6 */
|
||||
/* io_expander3 - pca9555@21 */
|
||||
i2c_slave_create_simple(i2c[6], TYPE_PCA9555, 0x21);
|
||||
i2c_slave_create_simple(i2c[6], TYPE_PCA9552, 0x21);
|
||||
/* rtc@6f - nct3018y */
|
||||
i2c_slave_create_simple(i2c[6], TYPE_DS1338, 0x6f);
|
||||
|
||||
/* &i2c9 */
|
||||
/* io_expander4 - pca9555@4f */
|
||||
i2c_slave_create_simple(i2c[9], TYPE_PCA9555, 0x4f);
|
||||
i2c_slave_create_simple(i2c[9], TYPE_PCA9552, 0x4f);
|
||||
/* temperature-sensor@4b - tpm75 */
|
||||
i2c_slave_create_simple(i2c[9], TYPE_TMP75, 0x4b);
|
||||
/* eeprom@50 */
|
||||
|
|
@ -631,17 +615,17 @@ static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
|
|||
|
||||
/* &i2c14 */
|
||||
/* io_expander9 - pca9555@10 */
|
||||
i2c_slave_create_simple(i2c[14], TYPE_PCA9555, 0x10);
|
||||
i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x10);
|
||||
/* io_expander10 - pca9555@11 */
|
||||
i2c_slave_create_simple(i2c[14], TYPE_PCA9555, 0x11);
|
||||
i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x11);
|
||||
/* io_expander11 - pca9555@12 */
|
||||
i2c_slave_create_simple(i2c[14], TYPE_PCA9555, 0x12);
|
||||
i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x12);
|
||||
/* io_expander12 - pca9555@13 */
|
||||
i2c_slave_create_simple(i2c[14], TYPE_PCA9555, 0x13);
|
||||
i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x13);
|
||||
/* io_expander13 - pca9555@14 */
|
||||
i2c_slave_create_simple(i2c[14], TYPE_PCA9555, 0x14);
|
||||
i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x14);
|
||||
/* io_expander14 - pca9555@15 */
|
||||
i2c_slave_create_simple(i2c[14], TYPE_PCA9555, 0x15);
|
||||
i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x15);
|
||||
|
||||
/* &i2c15 */
|
||||
/* temperature-sensor@1f - tmp421 */
|
||||
|
|
|
|||
|
|
@ -27,6 +27,10 @@
|
|||
#define TYPE_AST2700FC MACHINE_TYPE_NAME("ast2700fc")
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700FC);
|
||||
|
||||
static struct arm_boot_info ast2700fc_board_info = {
|
||||
.board_id = -1, /* device-tree-only board */
|
||||
};
|
||||
|
||||
struct Ast2700FCState {
|
||||
MachineState parent_obj;
|
||||
|
||||
|
|
@ -42,8 +46,6 @@ struct Ast2700FCState {
|
|||
Aspeed27x0SoCState ca35;
|
||||
Aspeed27x0CoprocessorState ssp;
|
||||
Aspeed27x0CoprocessorState tsp;
|
||||
|
||||
struct arm_boot_info bootinfo;
|
||||
};
|
||||
|
||||
#define AST2700FC_BMC_RAM_SIZE (2 * GiB)
|
||||
|
|
@ -112,9 +114,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
|
|||
aspeed_board_init_flashes(&soc->fmc, AST2700FC_FMC_MODEL, 2, 0);
|
||||
aspeed_board_init_flashes(&soc->spi[0], AST2700FC_SPI_MODEL, 1, 2);
|
||||
|
||||
s->bootinfo.ram_size = machine->ram_size;
|
||||
s->bootinfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
|
||||
s->bootinfo.board_id = -1; /* device-tree-only board */
|
||||
ast2700fc_board_info.ram_size = machine->ram_size;
|
||||
ast2700fc_board_info.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
|
||||
|
||||
dev = ssi_get_cs(soc->fmc.spi, 0);
|
||||
fmc0 = dev ? m25p80_get_blk(dev) : NULL;
|
||||
|
|
@ -128,14 +129,16 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
|
|||
bios_name = machine->firmware ?: VBOOTROM_FILE_NAME;
|
||||
aspeed_load_vbootrom(soc, bios_name, errp);
|
||||
|
||||
arm_load_kernel(ARM_CPU(first_cpu), machine, &s->bootinfo);
|
||||
arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool ast2700fc_ssp_init(Ast2700FCState *s, AspeedSoCState *psp,
|
||||
Error **errp)
|
||||
static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
|
||||
{
|
||||
Ast2700FCState *s = AST2700FC(machine);
|
||||
AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
|
||||
|
||||
s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
|
||||
clock_set_hz(s->ssp_sysclk, 200000000ULL);
|
||||
|
||||
|
|
@ -155,11 +158,7 @@ static bool ast2700fc_ssp_init(Ast2700FCState *s, AspeedSoCState *psp,
|
|||
object_property_set_link(OBJECT(&s->ssp), "sram",
|
||||
OBJECT(&psp->sram), &error_abort);
|
||||
object_property_set_link(OBJECT(&s->ssp), "scu",
|
||||
OBJECT(&s->ca35.scu), &error_abort);
|
||||
object_property_set_link(OBJECT(&s->ssp), "scuio",
|
||||
OBJECT(&psp->scuio), &error_abort);
|
||||
object_property_set_link(OBJECT(&s->ssp), "fmc",
|
||||
OBJECT(&psp->fmc), &error_abort);
|
||||
OBJECT(&psp->scu), &error_abort);
|
||||
if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {
|
||||
return false;
|
||||
}
|
||||
|
|
@ -167,9 +166,11 @@ static bool ast2700fc_ssp_init(Ast2700FCState *s, AspeedSoCState *psp,
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool ast2700fc_tsp_init(Ast2700FCState *s, AspeedSoCState *psp,
|
||||
Error **errp)
|
||||
static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
|
||||
{
|
||||
Ast2700FCState *s = AST2700FC(machine);
|
||||
AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
|
||||
|
||||
s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
|
||||
clock_set_hz(s->tsp_sysclk, 200000000ULL);
|
||||
|
||||
|
|
@ -189,11 +190,7 @@ static bool ast2700fc_tsp_init(Ast2700FCState *s, AspeedSoCState *psp,
|
|||
object_property_set_link(OBJECT(&s->tsp), "sram",
|
||||
OBJECT(&psp->sram), &error_abort);
|
||||
object_property_set_link(OBJECT(&s->tsp), "scu",
|
||||
OBJECT(&s->ca35.scu), &error_abort);
|
||||
object_property_set_link(OBJECT(&s->tsp), "scuio",
|
||||
OBJECT(&psp->scuio), &error_abort);
|
||||
object_property_set_link(OBJECT(&s->tsp), "fmc",
|
||||
OBJECT(&psp->fmc), &error_abort);
|
||||
OBJECT(&psp->scu), &error_abort);
|
||||
if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {
|
||||
return false;
|
||||
}
|
||||
|
|
@ -203,19 +200,9 @@ static bool ast2700fc_tsp_init(Ast2700FCState *s, AspeedSoCState *psp,
|
|||
|
||||
static void ast2700fc_init(MachineState *machine)
|
||||
{
|
||||
Ast2700FCState *s = AST2700FC(machine);
|
||||
AspeedSoCState *psp;
|
||||
|
||||
ast2700fc_ca35_init(machine, &error_abort);
|
||||
|
||||
/*
|
||||
* SSP and TSP use resources owned by the PSP SoC, such as UART,
|
||||
* SRAM, SCU and SCUIO. Therefore the PSP SoC must be realized
|
||||
* before the coprocessors are initialized.
|
||||
*/
|
||||
psp = ASPEED_SOC(&s->ca35);
|
||||
ast2700fc_ssp_init(s, psp, &error_abort);
|
||||
ast2700fc_tsp_init(s, psp, &error_abort);
|
||||
ast2700fc_ssp_init(machine, &error_abort);
|
||||
ast2700fc_tsp_init(machine, &error_abort);
|
||||
}
|
||||
|
||||
static void ast2700fc_class_init(ObjectClass *oc, const void *data)
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
|
|||
[ASPEED_DEV_TIMER1] = 0x72C10000,
|
||||
[ASPEED_DEV_UART4] = 0x72C1A000,
|
||||
[ASPEED_DEV_IPC0] = 0x72C1C000,
|
||||
[ASPEED_DEV_FMC] = 0x74000000,
|
||||
[ASPEED_DEV_PRIC1] = 0x74100000,
|
||||
[ASPEED_DEV_SCUIO] = 0x74C02000,
|
||||
[ASPEED_DEV_OTP] = 0x74C07000,
|
||||
|
|
@ -143,6 +142,8 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
|
|||
TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "ipc1", &a->ipc[1],
|
||||
TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "scuio", &a->scuio,
|
||||
TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "pric0", &a->pric[0],
|
||||
TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "pric1", &a->pric[1],
|
||||
|
|
@ -166,24 +167,6 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
|
|||
return;
|
||||
}
|
||||
|
||||
if (!a->scu) {
|
||||
error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
|
||||
": 'scu' link is not set");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!a->scuio) {
|
||||
error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
|
||||
": 'scuio' link is not set");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!a->fmc) {
|
||||
error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
|
||||
": 'fmc' link is not set");
|
||||
return;
|
||||
}
|
||||
|
||||
/* AST27X0 SSP Core */
|
||||
armv7m = DEVICE(&a->armv7m);
|
||||
qdev_prop_set_uint32(armv7m, "num-irq", 256);
|
||||
|
|
@ -212,18 +195,11 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
|
|||
&s->sram_alias);
|
||||
|
||||
/* SCU */
|
||||
memory_region_init_alias(&a->scu_alias, OBJECT(a), "scu.alias",
|
||||
&a->scu->parent_obj.iomem, 0,
|
||||
memory_region_size(&a->scu->parent_obj.iomem));
|
||||
memory_region_init_alias(&s->scu_alias, OBJECT(s), "scu.alias",
|
||||
&s->scu->iomem, 0,
|
||||
memory_region_size(&s->scu->iomem));
|
||||
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
|
||||
&a->scu_alias);
|
||||
|
||||
/* SCUIO */
|
||||
memory_region_init_alias(&a->scuio_alias, OBJECT(a), "scuio.alias",
|
||||
&a->scuio->iomem, 0,
|
||||
memory_region_size(&a->scuio->iomem));
|
||||
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
|
||||
&a->scuio_alias);
|
||||
&s->scu_alias);
|
||||
|
||||
/* INTC */
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
|
||||
|
|
@ -276,13 +252,6 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
|
|||
sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0,
|
||||
aspeed_soc_ast27x0ssp_get_irq(s, s->uart_dev));
|
||||
|
||||
/* FMC */
|
||||
memory_region_init_alias(&a->fmc_alias, OBJECT(a), "fmc.alias",
|
||||
&a->fmc->mmio, 0,
|
||||
memory_region_size(&a->fmc->mmio));
|
||||
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_FMC],
|
||||
&a->fmc_alias);
|
||||
|
||||
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
|
||||
"aspeed.timerctrl",
|
||||
sc->memmap[ASPEED_DEV_TIMER1], 0x200);
|
||||
|
|
@ -292,6 +261,9 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
|
|||
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]),
|
||||
"aspeed.ipc1",
|
||||
sc->memmap[ASPEED_DEV_IPC1], 0x1000);
|
||||
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
|
||||
"aspeed.scuio",
|
||||
sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
|
||||
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
|
||||
"aspeed.pric0",
|
||||
sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
|
||||
|
|
@ -303,15 +275,6 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
|
|||
sc->memmap[ASPEED_DEV_OTP], 0x800);
|
||||
}
|
||||
|
||||
static const Property aspeed_27x0_coprocessor_properties[] = {
|
||||
DEFINE_PROP_LINK("scu", Aspeed27x0CoprocessorState, scu,
|
||||
TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),
|
||||
DEFINE_PROP_LINK("scuio", Aspeed27x0CoprocessorState, scuio,
|
||||
TYPE_ASPEED_SCU, AspeedSCUState *),
|
||||
DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
|
||||
AspeedSMCState *),
|
||||
};
|
||||
|
||||
static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
|
||||
const void *data)
|
||||
{
|
||||
|
|
@ -325,7 +288,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
|
|||
/* Reason: The Aspeed Coprocessor can only be instantiated from a board */
|
||||
dc->user_creatable = false;
|
||||
dc->realize = aspeed_soc_ast27x0ssp_realize;
|
||||
device_class_set_props(dc, aspeed_27x0_coprocessor_properties);
|
||||
|
||||
sc->valid_cpu_types = valid_cpu_types;
|
||||
sc->irqmap = aspeed_soc_ast27x0ssp_irqmap;
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
|
|||
[ASPEED_DEV_TIMER1] = 0x72C10000,
|
||||
[ASPEED_DEV_UART4] = 0x72C1A000,
|
||||
[ASPEED_DEV_IPC0] = 0x72C1C000,
|
||||
[ASPEED_DEV_FMC] = 0x74000000,
|
||||
[ASPEED_DEV_PRIC1] = 0x74100000,
|
||||
[ASPEED_DEV_SCUIO] = 0x74C02000,
|
||||
[ASPEED_DEV_OTP] = 0x74C07000,
|
||||
|
|
@ -143,6 +142,8 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
|
|||
TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "ipc1", &a->ipc[1],
|
||||
TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "scuio", &a->scuio,
|
||||
TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "pric0", &a->pric[0],
|
||||
TYPE_UNIMPLEMENTED_DEVICE);
|
||||
object_initialize_child(obj, "pric1", &a->pric[1],
|
||||
|
|
@ -166,24 +167,6 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
|
|||
return;
|
||||
}
|
||||
|
||||
if (!a->scu) {
|
||||
error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
|
||||
": 'scu' link is not set");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!a->scuio) {
|
||||
error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
|
||||
": 'scuio' link is not set");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!a->fmc) {
|
||||
error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
|
||||
": 'fmc' link is not set");
|
||||
return;
|
||||
}
|
||||
|
||||
/* AST27X0 TSP Core */
|
||||
armv7m = DEVICE(&a->armv7m);
|
||||
qdev_prop_set_uint32(armv7m, "num-irq", 256);
|
||||
|
|
@ -212,18 +195,11 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
|
|||
&s->sram_alias);
|
||||
|
||||
/* SCU */
|
||||
memory_region_init_alias(&a->scu_alias, OBJECT(a), "scu.alias",
|
||||
&a->scu->parent_obj.iomem, 0,
|
||||
memory_region_size(&a->scu->parent_obj.iomem));
|
||||
memory_region_init_alias(&s->scu_alias, OBJECT(s), "scu.alias",
|
||||
&s->scu->iomem, 0,
|
||||
memory_region_size(&s->scu->iomem));
|
||||
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
|
||||
&a->scu_alias);
|
||||
|
||||
/* SCUIO */
|
||||
memory_region_init_alias(&a->scuio_alias, OBJECT(a), "scuio.alias",
|
||||
&a->scuio->iomem, 0,
|
||||
memory_region_size(&a->scuio->iomem));
|
||||
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
|
||||
&a->scuio_alias);
|
||||
&s->scu_alias);
|
||||
|
||||
/* INTC */
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
|
||||
|
|
@ -276,13 +252,6 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
|
|||
sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0,
|
||||
aspeed_soc_ast27x0tsp_get_irq(s, s->uart_dev));
|
||||
|
||||
/* FMC */
|
||||
memory_region_init_alias(&a->fmc_alias, OBJECT(a), "fmc.alias",
|
||||
&a->fmc->mmio, 0,
|
||||
memory_region_size(&a->fmc->mmio));
|
||||
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_FMC],
|
||||
&a->fmc_alias);
|
||||
|
||||
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
|
||||
"aspeed.timerctrl",
|
||||
sc->memmap[ASPEED_DEV_TIMER1], 0x200);
|
||||
|
|
@ -292,6 +261,9 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
|
|||
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]),
|
||||
"aspeed.ipc1",
|
||||
sc->memmap[ASPEED_DEV_IPC1], 0x1000);
|
||||
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
|
||||
"aspeed.scuio",
|
||||
sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
|
||||
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
|
||||
"aspeed.pric0",
|
||||
sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
|
||||
|
|
@ -303,15 +275,6 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
|
|||
sc->memmap[ASPEED_DEV_OTP], 0x800);
|
||||
}
|
||||
|
||||
static const Property aspeed_27x0_coprocessor_properties[] = {
|
||||
DEFINE_PROP_LINK("scu", Aspeed27x0CoprocessorState, scu,
|
||||
TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),
|
||||
DEFINE_PROP_LINK("scuio", Aspeed27x0CoprocessorState, scuio,
|
||||
TYPE_ASPEED_SCU, AspeedSCUState *),
|
||||
DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
|
||||
AspeedSMCState *),
|
||||
};
|
||||
|
||||
static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
|
||||
const void *data)
|
||||
{
|
||||
|
|
@ -325,7 +288,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
|
|||
/* Reason: The Aspeed Coprocessor can only be instantiated from a board */
|
||||
dc->user_creatable = false;
|
||||
dc->realize = aspeed_soc_ast27x0tsp_realize;
|
||||
device_class_set_props(dc, aspeed_27x0_coprocessor_properties);
|
||||
|
||||
sc->valid_cpu_types = valid_cpu_types;
|
||||
sc->irqmap = aspeed_soc_ast27x0tsp_irqmap;
|
||||
|
|
|
|||
|
|
@ -435,12 +435,12 @@ static void aspeed_soc_ast2700_init(Object *obj)
|
|||
|
||||
object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
|
||||
|
||||
object_initialize_child(obj, "scu", &a->scu, TYPE_ASPEED_2700_SCU);
|
||||
qdev_prop_set_uint32(DEVICE(&a->scu), "silicon-rev",
|
||||
object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
|
||||
qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
|
||||
sc->silicon_rev);
|
||||
object_property_add_alias(obj, "hw-strap1", OBJECT(&a->scu),
|
||||
object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
|
||||
"hw-strap1");
|
||||
object_property_add_alias(obj, "hw-prot-key", OBJECT(&a->scu),
|
||||
object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
|
||||
"hw-prot-key");
|
||||
|
||||
object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
|
||||
|
|
@ -808,10 +808,10 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
|
|||
sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom);
|
||||
|
||||
/* SCU */
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&a->scu), errp)) {
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
|
||||
return;
|
||||
}
|
||||
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->scu), 0,
|
||||
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
|
||||
sc->memmap[ASPEED_DEV_SCU]);
|
||||
|
||||
/* SCU1 */
|
||||
|
|
@ -870,11 +870,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
|
|||
|
||||
/* EHCI */
|
||||
for (i = 0; i < sc->ehcis_num; i++) {
|
||||
object_property_set_int(OBJECT(&s->ehci[i]), "ctrldssegment-default",
|
||||
sc->memmap[ASPEED_DEV_SDRAM] >> 32,
|
||||
&error_abort);
|
||||
object_property_set_bool(OBJECT(&s->ehci[i]), "caps-64bit-addr", true,
|
||||
&error_abort);
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
|
||||
return;
|
||||
}
|
||||
|
|
@ -934,7 +929,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
|
|||
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
|
||||
hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
|
||||
|
||||
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&a->scu),
|
||||
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
|
||||
&error_abort);
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
|
||||
return;
|
||||
|
|
@ -1037,7 +1032,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
|
|||
aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_EMMC));
|
||||
|
||||
/* Timer */
|
||||
object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&a->scu),
|
||||
object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
|
||||
&error_abort);
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -27,6 +27,8 @@ static const Property aspeed_coprocessor_properties[] = {
|
|||
TYPE_MEMORY_REGION, MemoryRegion *),
|
||||
DEFINE_PROP_LINK("sram", AspeedCoprocessorState, sram, TYPE_MEMORY_REGION,
|
||||
MemoryRegion *),
|
||||
DEFINE_PROP_LINK("scu", AspeedCoprocessorState, scu, TYPE_ASPEED_SCU,
|
||||
AspeedSCUState *),
|
||||
DEFINE_PROP_LINK("uart", AspeedCoprocessorState, uart, TYPE_SERIAL_MM,
|
||||
SerialMM *),
|
||||
DEFINE_PROP_INT32("uart-dev", AspeedCoprocessorState, uart_dev, 0),
|
||||
|
|
|
|||
|
|
@ -1,56 +0,0 @@
|
|||
/*
|
||||
* Axiado Boards
|
||||
*
|
||||
* Author: Kuan-Jui Chiu <kchiu@axiado.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "hw/arm/ax3000-boards.h"
|
||||
#include "hw/arm/boot.h"
|
||||
#include "hw/arm/machines-qom.h"
|
||||
#include "qemu/error-report.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
static struct arm_boot_info ax3000_binfo = {
|
||||
.loader_start = AX3000_DRAM0_BASE,
|
||||
.board_id = -1,
|
||||
};
|
||||
|
||||
static void ax3000_machine_init(MachineState *machine)
|
||||
{
|
||||
Ax3000MachineState *ams = AX3000_MACHINE(machine);
|
||||
|
||||
ams->soc = AX3000_SOC(object_new(TYPE_AX3000_SOC));
|
||||
object_property_add_child(OBJECT(machine), "soc", OBJECT(ams->soc));
|
||||
sysbus_realize_and_unref(SYS_BUS_DEVICE(ams->soc), &error_fatal);
|
||||
|
||||
ax3000_binfo.ram_size = machine->ram_size;
|
||||
arm_load_kernel(&ams->soc->cpu[0], machine, &ax3000_binfo);
|
||||
}
|
||||
|
||||
static void ax3000_machine_class_init(ObjectClass *oc, const void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->init = ax3000_machine_init;
|
||||
mc->default_cpus = AX3000_NUM_CPUS;
|
||||
mc->min_cpus = AX3000_NUM_CPUS;
|
||||
mc->max_cpus = AX3000_NUM_CPUS;
|
||||
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53");
|
||||
}
|
||||
|
||||
static const TypeInfo ax3000_machine_types[] = {
|
||||
{
|
||||
.name = TYPE_AX3000_MACHINE,
|
||||
.parent = TYPE_MACHINE,
|
||||
.instance_size = sizeof(Ax3000MachineState),
|
||||
.class_size = sizeof(Ax3000MachineClass),
|
||||
.class_init = ax3000_machine_class_init,
|
||||
.interfaces = aarch64_machine_interfaces,
|
||||
.abstract = true,
|
||||
}
|
||||
};
|
||||
|
||||
DEFINE_TYPES(ax3000_machine_types)
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
* Axiado Evaluation Kit Emulation
|
||||
*
|
||||
* Author: Kuan-Jui Chiu <kchiu@axiado.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "hw/arm/ax3000-boards.h"
|
||||
|
||||
static void axiado_scm3003_class_init(ObjectClass *oc, const void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Axiado SCM3003 EVK Board";
|
||||
}
|
||||
|
||||
static const TypeInfo ax3000_evk_types[] = {
|
||||
{
|
||||
.name = MACHINE_TYPE_NAME("axiado-scm3003"),
|
||||
.parent = TYPE_AX3000_MACHINE,
|
||||
.class_init = axiado_scm3003_class_init,
|
||||
}
|
||||
};
|
||||
|
||||
DEFINE_TYPES(ax3000_evk_types)
|
||||
|
|
@ -1,243 +0,0 @@
|
|||
/*
|
||||
* Axiado SoC AX3000
|
||||
*
|
||||
* Author: Kuan-Jui Chiu <kchiu@axiado.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "system/address-spaces.h"
|
||||
#include "hw/arm/bsa.h"
|
||||
#include "hw/arm/ax3000-soc.h"
|
||||
#include "hw/misc/unimp.h"
|
||||
#include "system/system.h"
|
||||
#include "qobject/qlist.h"
|
||||
#include "qom/object.h"
|
||||
#include "hw/core/boards.h"
|
||||
|
||||
static void ax3000_init(Object *obj)
|
||||
{
|
||||
Ax3000SoCState *s = AX3000_SOC(obj);
|
||||
Ax3000SoCClass *sc = AX3000_SOC_GET_CLASS(s);
|
||||
|
||||
for (int i = 0; i < sc->num_cpus; i++) {
|
||||
g_autofree char *name = g_strdup_printf("cpu%d", i);
|
||||
object_initialize_child(obj, name, &s->cpu[i],
|
||||
ARM_CPU_TYPE_NAME("cortex-a53"));
|
||||
}
|
||||
|
||||
object_initialize_child(obj, "gic", &s->gic, gicv3_class_name());
|
||||
|
||||
for (int i = 0; i < AX3000_NUM_UARTS; i++) {
|
||||
g_autofree char *name = g_strdup_printf("uart%d", i);
|
||||
object_initialize_child(obj, name, &s->uart[i], TYPE_CADENCE_UART);
|
||||
}
|
||||
|
||||
object_initialize_child(obj, "clk", &s->ax3000_clk, TYPE_AX3000_CLK);
|
||||
object_initialize_child(obj, "sdhci0", &s->sdhci0, TYPE_AXIADO_SDHCI);
|
||||
|
||||
for (int i = 0; i < AX3000_NUM_GPIOS; i++) {
|
||||
g_autofree char *name = g_strdup_printf("gpio%d", i);
|
||||
object_initialize_child(obj, name, &s->gpio[i], TYPE_CADENCE_GPIO);
|
||||
}
|
||||
}
|
||||
|
||||
static void ax3000_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
Ax3000SoCState *s = AX3000_SOC(dev);
|
||||
Ax3000SoCClass *sc = AX3000_SOC_GET_CLASS(s);
|
||||
SysBusDevice *gic_sbd = SYS_BUS_DEVICE(&s->gic);
|
||||
DeviceState *gic_dev = DEVICE(&s->gic);
|
||||
QList *redist_region_count;
|
||||
SysBusDevice *sdhci0_sbd;
|
||||
DeviceState *card;
|
||||
DriveInfo *dinfo;
|
||||
|
||||
/* CPUs */
|
||||
for (int i = 0; i < sc->num_cpus; i++) {
|
||||
object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 8000000,
|
||||
&error_abort);
|
||||
|
||||
if (object_property_find(OBJECT(&s->cpu[i]), "has_el3")) {
|
||||
object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3",
|
||||
false, &error_abort);
|
||||
}
|
||||
|
||||
if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* GIC */
|
||||
qdev_prop_set_uint32(gic_dev, "num-cpu", sc->num_cpus);
|
||||
qdev_prop_set_uint32(gic_dev, "num-irq",
|
||||
AX3000_NUM_IRQS + GIC_INTERNAL);
|
||||
|
||||
redist_region_count = qlist_new();
|
||||
qlist_append_int(redist_region_count, sc->num_cpus);
|
||||
qdev_prop_set_array(gic_dev, "redist-region-count", redist_region_count);
|
||||
|
||||
if (!sysbus_realize(gic_sbd, errp)) {
|
||||
return;
|
||||
}
|
||||
|
||||
sysbus_mmio_map(gic_sbd, 0, AX3000_GIC_DIST_BASE);
|
||||
sysbus_mmio_map(gic_sbd, 1, AX3000_GIC_REDIST_BASE);
|
||||
|
||||
/*
|
||||
* Mapping from the output timer irq lines from the CPU to the
|
||||
* GIC PPI inputs.
|
||||
*/
|
||||
const int timer_irqs[] = {
|
||||
[GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
|
||||
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
|
||||
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
|
||||
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ
|
||||
};
|
||||
|
||||
/*
|
||||
* Wire the outputs from each CPU's generic timer and the GICv3
|
||||
* maintenance interrupt signal to the appropriate GIC PPI inputs, and
|
||||
* the GIC's IRQ/FIQ interrupt outputs to the CPU's inputs.
|
||||
*/
|
||||
for (int i = 0; i < sc->num_cpus; i++) {
|
||||
DeviceState *cpu_dev = DEVICE(&s->cpu[i]);
|
||||
int intidbase = AX3000_NUM_IRQS + i * GIC_INTERNAL;
|
||||
qemu_irq irq;
|
||||
|
||||
for (int j = 0; j < ARRAY_SIZE(timer_irqs); j++) {
|
||||
irq = qdev_get_gpio_in(gic_dev, intidbase + timer_irqs[j]);
|
||||
qdev_connect_gpio_out(cpu_dev, j, irq);
|
||||
}
|
||||
|
||||
irq = qdev_get_gpio_in(gic_dev, intidbase + ARCH_GIC_MAINT_IRQ);
|
||||
qdev_connect_gpio_out_named(cpu_dev, "gicv3-maintenance-interrupt",
|
||||
0, irq);
|
||||
|
||||
sysbus_connect_irq(gic_sbd, i,
|
||||
qdev_get_gpio_in(cpu_dev, ARM_CPU_IRQ));
|
||||
sysbus_connect_irq(gic_sbd, i + sc->num_cpus,
|
||||
qdev_get_gpio_in(cpu_dev, ARM_CPU_FIQ));
|
||||
sysbus_connect_irq(gic_sbd, i + 2 * sc->num_cpus,
|
||||
qdev_get_gpio_in(cpu_dev, ARM_CPU_VIRQ));
|
||||
sysbus_connect_irq(gic_sbd, i + 3 * sc->num_cpus,
|
||||
qdev_get_gpio_in(cpu_dev, ARM_CPU_VFIQ));
|
||||
}
|
||||
|
||||
/* DRAM */
|
||||
const struct {
|
||||
hwaddr addr;
|
||||
size_t size;
|
||||
const char *name;
|
||||
} dram_table[] = {
|
||||
{ AX3000_DRAM0_BASE, AX3000_DRAM0_SIZE, "dram0" },
|
||||
{ AX3000_DRAM1_BASE, AX3000_DRAM1_SIZE, "dram1" }
|
||||
};
|
||||
|
||||
for (int i = 0; i < AX3000_NUM_BANKS; i++) {
|
||||
memory_region_init_ram(&s->dram[i], OBJECT(s), dram_table[i].name,
|
||||
dram_table[i].size, &error_fatal);
|
||||
memory_region_add_subregion(get_system_memory(), dram_table[i].addr,
|
||||
&s->dram[i]);
|
||||
}
|
||||
|
||||
/* UARTs */
|
||||
const struct {
|
||||
hwaddr addr;
|
||||
unsigned int irq;
|
||||
} serial_table[] = {
|
||||
{ AX3000_UART0_BASE, AX3000_UART0_IRQ },
|
||||
{ AX3000_UART1_BASE, AX3000_UART1_IRQ },
|
||||
{ AX3000_UART2_BASE, AX3000_UART2_IRQ },
|
||||
{ AX3000_UART3_BASE, AX3000_UART3_IRQ }
|
||||
};
|
||||
|
||||
for (int i = 0; i < AX3000_NUM_UARTS; i++) {
|
||||
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
|
||||
return;
|
||||
}
|
||||
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
|
||||
qdev_get_gpio_in(gic_dev, serial_table[i].irq));
|
||||
}
|
||||
|
||||
/* Timer control */
|
||||
create_unimplemented_device("ax3000.timerctrl", AX3000_TIMER_CTRL, 32);
|
||||
|
||||
/* Clock control */
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ax3000_clk), errp)) {
|
||||
return;
|
||||
}
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ax3000_clk), 0, AX3000_PLL_BASE);
|
||||
|
||||
/* SDHCI */
|
||||
sdhci0_sbd = SYS_BUS_DEVICE(&s->sdhci0);
|
||||
if (!sysbus_realize(sdhci0_sbd, errp)) {
|
||||
return;
|
||||
}
|
||||
|
||||
sysbus_mmio_map(sdhci0_sbd, 0, AX3000_SDHCI0_BASE);
|
||||
sysbus_mmio_map(sdhci0_sbd, 1, AX3000_EMMC_PHY_BASE);
|
||||
sysbus_connect_irq(sdhci0_sbd, 0,
|
||||
qdev_get_gpio_in(gic_dev, AX3000_SDHCI0_IRQ));
|
||||
|
||||
dinfo = drive_get(IF_SD, 0, 0);
|
||||
if (dinfo) {
|
||||
card = qdev_new(TYPE_SD_CARD);
|
||||
qdev_prop_set_drive_err(card, "drive",
|
||||
blk_by_legacy_dinfo(dinfo),
|
||||
&error_fatal);
|
||||
qdev_realize_and_unref(card, s->sdhci0.sd_bus, &error_fatal);
|
||||
}
|
||||
|
||||
/* GPIOs */
|
||||
const struct {
|
||||
hwaddr addr;
|
||||
unsigned int irq;
|
||||
} gpio_table[] = {
|
||||
{ AX3000_GPIO0_BASE, AX3000_GPIO0_IRQ },
|
||||
{ AX3000_GPIO1_BASE, AX3000_GPIO1_IRQ },
|
||||
{ AX3000_GPIO2_BASE, AX3000_GPIO2_IRQ },
|
||||
{ AX3000_GPIO3_BASE, AX3000_GPIO3_IRQ },
|
||||
{ AX3000_GPIO4_BASE, AX3000_GPIO4_IRQ },
|
||||
{ AX3000_GPIO5_BASE, AX3000_GPIO5_IRQ },
|
||||
{ AX3000_GPIO6_BASE, AX3000_GPIO6_IRQ },
|
||||
{ AX3000_GPIO7_BASE, AX3000_GPIO7_IRQ }
|
||||
};
|
||||
|
||||
for (int i = 0; i < AX3000_NUM_GPIOS; i++) {
|
||||
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
|
||||
return;
|
||||
}
|
||||
|
||||
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
|
||||
qdev_get_gpio_in(gic_dev, gpio_table[i].irq));
|
||||
}
|
||||
}
|
||||
|
||||
static void ax3000_class_init(ObjectClass *oc, const void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(oc);
|
||||
Ax3000SoCClass *sc = AX3000_SOC_CLASS(oc);
|
||||
|
||||
dc->desc = "Axiado SoC AX3000";
|
||||
dc->realize = ax3000_realize;
|
||||
sc->num_cpus = AX3000_NUM_CPUS;
|
||||
}
|
||||
|
||||
static const TypeInfo axiado_soc_types[] = {
|
||||
{
|
||||
.name = TYPE_AX3000_SOC,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(Ax3000SoCState),
|
||||
.instance_init = ax3000_init,
|
||||
.class_init = ax3000_class_init,
|
||||
.class_size = sizeof(Ax3000SoCClass),
|
||||
}
|
||||
};
|
||||
|
||||
DEFINE_TYPES(axiado_soc_types)
|
||||
|
|
@ -29,14 +29,7 @@
|
|||
#include "hw/arm/boot.h"
|
||||
#include "hw/arm/machines-qom.h"
|
||||
|
||||
#define TYPE_BPIM2U_MACHINE MACHINE_TYPE_NAME("bpim2u")
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(Bpim2uMachineState, BPIM2U_MACHINE)
|
||||
|
||||
struct Bpim2uMachineState {
|
||||
MachineState parent;
|
||||
|
||||
struct arm_boot_info bootinfo;
|
||||
};
|
||||
static struct arm_boot_info bpim2u_binfo;
|
||||
|
||||
/*
|
||||
* R40 can boot from mmc0 and mmc2, and bpim2u has two mmc interface, one is
|
||||
|
|
@ -69,7 +62,6 @@ static void mmc_attach_drive(AwR40State *s, AwSdHostState *mmc, int unit,
|
|||
|
||||
static void bpim2u_init(MachineState *machine)
|
||||
{
|
||||
Bpim2uMachineState *bpms = BPIM2U_MACHINE(machine);
|
||||
bool bootroom_loaded = false;
|
||||
AwR40State *r40;
|
||||
I2CBus *i2c;
|
||||
|
|
@ -128,10 +120,10 @@ static void bpim2u_init(MachineState *machine)
|
|||
memory_region_add_subregion(get_system_memory(),
|
||||
r40->memmap[AW_R40_DEV_SDRAM], machine->ram);
|
||||
|
||||
bpms->bootinfo.loader_start = r40->memmap[AW_R40_DEV_SDRAM];
|
||||
bpms->bootinfo.ram_size = machine->ram_size;
|
||||
bpms->bootinfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
|
||||
arm_load_kernel(&r40->cpus[0], machine, &bpms->bootinfo);
|
||||
bpim2u_binfo.loader_start = r40->memmap[AW_R40_DEV_SDRAM];
|
||||
bpim2u_binfo.ram_size = machine->ram_size;
|
||||
bpim2u_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
|
||||
arm_load_kernel(&r40->cpus[0], machine, &bpim2u_binfo);
|
||||
}
|
||||
|
||||
static void bpim2u_machine_init(MachineClass *mc)
|
||||
|
|
@ -153,5 +145,4 @@ static void bpim2u_machine_init(MachineClass *mc)
|
|||
mc->auto_create_sdcard = true;
|
||||
}
|
||||
|
||||
DEFINE_MACHINE_EXTENDED("bpim2u", MACHINE, Bpim2uMachineState,
|
||||
bpim2u_machine_init, false, arm_machine_interfaces)
|
||||
DEFINE_MACHINE_ARM("bpim2u", bpim2u_machine_init)
|
||||
|
|
|
|||
|
|
@ -30,12 +30,16 @@ struct CollieMachineState {
|
|||
MachineState parent;
|
||||
|
||||
StrongARMState *sa1110;
|
||||
struct arm_boot_info bootinfo;
|
||||
};
|
||||
|
||||
#define TYPE_COLLIE_MACHINE MACHINE_TYPE_NAME("collie")
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(CollieMachineState, COLLIE_MACHINE)
|
||||
|
||||
static struct arm_boot_info collie_binfo = {
|
||||
.loader_start = SA_SDCS0,
|
||||
.ram_size = RAM_SIZE,
|
||||
};
|
||||
|
||||
static void collie_init(MachineState *machine)
|
||||
{
|
||||
MachineClass *mc = MACHINE_GET_CLASS(machine);
|
||||
|
|
@ -62,10 +66,8 @@ static void collie_init(MachineState *machine)
|
|||
|
||||
sysbus_create_simple("scoop", 0x40800000, NULL);
|
||||
|
||||
cms->bootinfo.loader_start = SA_SDCS0;
|
||||
cms->bootinfo.ram_size = RAM_SIZE;
|
||||
cms->bootinfo.board_id = 0x208;
|
||||
arm_load_kernel(cms->sa1110->cpu, machine, &cms->bootinfo);
|
||||
collie_binfo.board_id = 0x208;
|
||||
arm_load_kernel(cms->sa1110->cpu, machine, &collie_binfo);
|
||||
}
|
||||
|
||||
static void collie_machine_class_init(ObjectClass *oc, const void *data)
|
||||
|
|
|
|||
|
|
@ -25,18 +25,13 @@
|
|||
#include "hw/arm/machines-qom.h"
|
||||
#include "hw/i2c/i2c.h"
|
||||
|
||||
#define TYPE_CUBIEBOARD_MACHINE MACHINE_TYPE_NAME("cubieboard")
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(CubieboardMachineState, CUBIEBOARD_MACHINE)
|
||||
|
||||
struct CubieboardMachineState {
|
||||
MachineState parent;
|
||||
|
||||
struct arm_boot_info bootinfo;
|
||||
static struct arm_boot_info cubieboard_binfo = {
|
||||
.loader_start = AW_A10_SDRAM_BASE,
|
||||
.board_id = 0x1008,
|
||||
};
|
||||
|
||||
static void cubieboard_init(MachineState *machine)
|
||||
{
|
||||
CubieboardMachineState *cbs = CUBIEBOARD_MACHINE(machine);
|
||||
AwA10State *a10;
|
||||
Error *err = NULL;
|
||||
DriveInfo *di;
|
||||
|
|
@ -108,10 +103,8 @@ static void cubieboard_init(MachineState *machine)
|
|||
}
|
||||
/* TODO create and connect IDE devices for ide_drive_get() */
|
||||
|
||||
cbs->bootinfo.loader_start = AW_A10_SDRAM_BASE;
|
||||
cbs->bootinfo.board_id = 0x1008;
|
||||
cbs->bootinfo.ram_size = machine->ram_size;
|
||||
arm_load_kernel(&a10->cpu, machine, &cbs->bootinfo);
|
||||
cubieboard_binfo.ram_size = machine->ram_size;
|
||||
arm_load_kernel(&a10->cpu, machine, &cubieboard_binfo);
|
||||
}
|
||||
|
||||
static void cubieboard_machine_init(MachineClass *mc)
|
||||
|
|
@ -133,6 +126,4 @@ static void cubieboard_machine_init(MachineClass *mc)
|
|||
mc->auto_create_sdcard = true;
|
||||
}
|
||||
|
||||
DEFINE_MACHINE_EXTENDED("cubieboard", MACHINE, CubieboardMachineState,
|
||||
cubieboard_machine_init, false,
|
||||
arm_machine_interfaces)
|
||||
DEFINE_MACHINE_ARM("cubieboard", cubieboard_machine_init)
|
||||
|
|
|
|||
|
|
@ -49,7 +49,6 @@ typedef struct Exynos4BoardState {
|
|||
Exynos4210State soc;
|
||||
MemoryRegion dram0_mem;
|
||||
MemoryRegion dram1_mem;
|
||||
struct arm_boot_info bootinfo;
|
||||
} Exynos4BoardState;
|
||||
|
||||
static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = {
|
||||
|
|
@ -67,6 +66,12 @@ static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
|
|||
[EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
|
||||
};
|
||||
|
||||
static struct arm_boot_info exynos4_board_binfo = {
|
||||
.loader_start = EXYNOS4210_BASE_BOOT_ADDR,
|
||||
.smp_loader_start = EXYNOS4210_SMP_BOOT_ADDR,
|
||||
.write_secondary_boot = exynos4210_write_secondary,
|
||||
};
|
||||
|
||||
static void lan9215_init(uint32_t base, qemu_irq irq)
|
||||
{
|
||||
DeviceState *dev;
|
||||
|
|
@ -108,15 +113,14 @@ static Exynos4BoardState *
|
|||
exynos4_boards_init_common(MachineState *machine,
|
||||
Exynos4BoardType board_type)
|
||||
{
|
||||
Exynos4BoardState *s = g_new0(Exynos4BoardState, 1);
|
||||
Exynos4BoardState *s = g_new(Exynos4BoardState, 1);
|
||||
|
||||
s->bootinfo.loader_start = EXYNOS4210_BASE_BOOT_ADDR;
|
||||
s->bootinfo.smp_loader_start = EXYNOS4210_SMP_BOOT_ADDR;
|
||||
s->bootinfo.write_secondary_boot = exynos4210_write_secondary;
|
||||
s->bootinfo.ram_size = exynos4_board_ram_size[board_type];
|
||||
s->bootinfo.board_id = exynos4_board_id[board_type];
|
||||
s->bootinfo.smp_bootreg_addr = exynos4_board_smp_bootreg_addr[board_type];
|
||||
s->bootinfo.gic_cpu_if_addr = EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
|
||||
exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
|
||||
exynos4_board_binfo.board_id = exynos4_board_id[board_type];
|
||||
exynos4_board_binfo.smp_bootreg_addr =
|
||||
exynos4_board_smp_bootreg_addr[board_type];
|
||||
exynos4_board_binfo.gic_cpu_if_addr =
|
||||
EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
|
||||
|
||||
exynos4_boards_init_ram(s, get_system_memory(),
|
||||
exynos4_board_ram_size[board_type]);
|
||||
|
|
@ -133,7 +137,7 @@ static void nuri_init(MachineState *machine)
|
|||
Exynos4BoardState *s = exynos4_boards_init_common(machine,
|
||||
EXYNOS4_BOARD_NURI);
|
||||
|
||||
arm_load_kernel(s->soc.cpu[0], machine, &s->bootinfo);
|
||||
arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo);
|
||||
}
|
||||
|
||||
static void smdkc210_init(MachineState *machine)
|
||||
|
|
@ -143,7 +147,7 @@ static void smdkc210_init(MachineState *machine)
|
|||
|
||||
lan9215_init(SMDK_LAN9118_BASE_ADDR,
|
||||
qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
|
||||
arm_load_kernel(s->soc.cpu[0], machine, &s->bootinfo);
|
||||
arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo);
|
||||
}
|
||||
|
||||
static const char * const valid_cpu_types[] = {
|
||||
|
|
|
|||
|
|
@ -61,9 +61,10 @@
|
|||
typedef struct IMX25PDK {
|
||||
FslIMX25State soc;
|
||||
MemoryRegion ram_alias;
|
||||
struct arm_boot_info bootinfo;
|
||||
} IMX25PDK;
|
||||
|
||||
static struct arm_boot_info imx25_pdk_binfo;
|
||||
|
||||
static void imx25_pdk_init(MachineState *machine)
|
||||
{
|
||||
IMX25PDK *s = g_new0(IMX25PDK, 1);
|
||||
|
|
@ -113,9 +114,9 @@ static void imx25_pdk_init(MachineState *machine)
|
|||
alias_offset += ram[i].size;
|
||||
}
|
||||
|
||||
s->bootinfo.ram_size = machine->ram_size;
|
||||
s->bootinfo.loader_start = FSL_IMX25_SDRAM0_ADDR;
|
||||
s->bootinfo.board_id = 1771;
|
||||
imx25_pdk_binfo.ram_size = machine->ram_size;
|
||||
imx25_pdk_binfo.loader_start = FSL_IMX25_SDRAM0_ADDR;
|
||||
imx25_pdk_binfo.board_id = 1771;
|
||||
|
||||
for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
|
||||
BusState *bus;
|
||||
|
|
@ -137,7 +138,7 @@ static void imx25_pdk_init(MachineState *machine)
|
|||
* fail.
|
||||
*/
|
||||
if (!qtest_enabled()) {
|
||||
arm_load_kernel(&s->soc.cpu, machine, &s->bootinfo);
|
||||
arm_load_kernel(&s->soc.cpu, machine, &imx25_pdk_binfo);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -20,15 +20,6 @@
|
|||
#include "qapi/error.h"
|
||||
#include <libfdt.h>
|
||||
|
||||
#define TYPE_IMX8MM_EVK_MACHINE MACHINE_TYPE_NAME("imx8mm-evk")
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(Imx8mmEvkMachineState, IMX8MM_EVK_MACHINE)
|
||||
|
||||
struct Imx8mmEvkMachineState {
|
||||
MachineState parent;
|
||||
|
||||
struct arm_boot_info bootinfo;
|
||||
};
|
||||
|
||||
static void imx8mm_evk_modify_dtb(const struct arm_boot_info *info, void *fdt)
|
||||
{
|
||||
int i, offset;
|
||||
|
|
@ -69,7 +60,7 @@ static void imx8mm_evk_modify_dtb(const struct arm_boot_info *info, void *fdt)
|
|||
|
||||
static void imx8mm_evk_init(MachineState *machine)
|
||||
{
|
||||
Imx8mmEvkMachineState *ims = IMX8MM_EVK_MACHINE(machine);
|
||||
static struct arm_boot_info boot_info;
|
||||
FslImx8mmState *s;
|
||||
|
||||
if (machine->ram_size > FSL_IMX8MM_RAM_SIZE_MAX) {
|
||||
|
|
@ -78,11 +69,13 @@ static void imx8mm_evk_init(MachineState *machine)
|
|||
exit(1);
|
||||
}
|
||||
|
||||
ims->bootinfo.loader_start = FSL_IMX8MM_RAM_START;
|
||||
ims->bootinfo.board_id = -1;
|
||||
ims->bootinfo.ram_size = machine->ram_size;
|
||||
ims->bootinfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
|
||||
ims->bootinfo.modify_dtb = imx8mm_evk_modify_dtb;
|
||||
boot_info = (struct arm_boot_info) {
|
||||
.loader_start = FSL_IMX8MM_RAM_START,
|
||||
.board_id = -1,
|
||||
.ram_size = machine->ram_size,
|
||||
.psci_conduit = QEMU_PSCI_CONDUIT_SMC,
|
||||
.modify_dtb = imx8mm_evk_modify_dtb,
|
||||
};
|
||||
|
||||
s = FSL_IMX8MM(object_new_with_props(TYPE_FSL_IMX8MM, OBJECT(machine),
|
||||
"soc", &error_fatal, NULL));
|
||||
|
|
@ -110,7 +103,7 @@ static void imx8mm_evk_init(MachineState *machine)
|
|||
}
|
||||
|
||||
if (!qtest_enabled()) {
|
||||
arm_load_kernel(&s->cpu[0], machine, &ims->bootinfo);
|
||||
arm_load_kernel(&s->cpu[0], machine, &boot_info);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -134,6 +127,4 @@ static void imx8mm_evk_machine_init(MachineClass *mc)
|
|||
mc->get_default_cpu_type = imx8mm_evk_get_default_cpu_type;
|
||||
}
|
||||
|
||||
DEFINE_MACHINE_EXTENDED("imx8mm-evk", MACHINE, Imx8mmEvkMachineState,
|
||||
imx8mm_evk_machine_init, false,
|
||||
aarch64_machine_interfaces)
|
||||
DEFINE_MACHINE_AARCH64("imx8mm-evk", imx8mm_evk_machine_init)
|
||||
|
|
|
|||
|
|
@ -581,19 +581,13 @@ static void icp_control_init(Object *obj)
|
|||
|
||||
/* Board init. */
|
||||
|
||||
#define TYPE_INTEGRATORCP_MACHINE MACHINE_TYPE_NAME("integratorcp")
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(IntegratorcpMachineState,
|
||||
INTEGRATORCP_MACHINE)
|
||||
|
||||
struct IntegratorcpMachineState {
|
||||
MachineState parent;
|
||||
|
||||
struct arm_boot_info bootinfo;
|
||||
static struct arm_boot_info integrator_binfo = {
|
||||
.loader_start = 0x0,
|
||||
.board_id = 0x113,
|
||||
};
|
||||
|
||||
static void integratorcp_init(MachineState *machine)
|
||||
{
|
||||
IntegratorcpMachineState *icms = INTEGRATORCP_MACHINE(machine);
|
||||
ram_addr_t ram_size = machine->ram_size;
|
||||
Object *cpuobj;
|
||||
ARMCPU *cpu;
|
||||
|
|
@ -686,10 +680,8 @@ static void integratorcp_init(MachineState *machine)
|
|||
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xc0000000);
|
||||
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[22]);
|
||||
|
||||
icms->bootinfo.loader_start = 0x0;
|
||||
icms->bootinfo.board_id = 0x113;
|
||||
icms->bootinfo.ram_size = ram_size;
|
||||
arm_load_kernel(cpu, machine, &icms->bootinfo);
|
||||
integrator_binfo.ram_size = ram_size;
|
||||
arm_load_kernel(cpu, machine, &integrator_binfo);
|
||||
}
|
||||
|
||||
static void integratorcp_machine_init(MachineClass *mc)
|
||||
|
|
@ -704,9 +696,7 @@ static void integratorcp_machine_init(MachineClass *mc)
|
|||
machine_add_audiodev_property(mc);
|
||||
}
|
||||
|
||||
DEFINE_MACHINE_EXTENDED("integratorcp", MACHINE, IntegratorcpMachineState,
|
||||
integratorcp_machine_init, false,
|
||||
arm_machine_interfaces)
|
||||
DEFINE_MACHINE_ARM("integratorcp", integratorcp_machine_init)
|
||||
|
||||
static const Property core_properties[] = {
|
||||
DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
|
||||
|
|
|
|||
12
hw/arm/kzm.c
12
hw/arm/kzm.c
|
|
@ -54,13 +54,17 @@
|
|||
typedef struct IMX31KZM {
|
||||
FslIMX31State soc;
|
||||
MemoryRegion ram_alias;
|
||||
struct arm_boot_info bootinfo;
|
||||
} IMX31KZM;
|
||||
|
||||
#define KZM_RAM_ADDR (FSL_IMX31_SDRAM0_ADDR)
|
||||
#define KZM_FPGA_ADDR (FSL_IMX31_CS4_ADDR + 0x1040)
|
||||
#define KZM_LAN9118_ADDR (FSL_IMX31_CS5_ADDR)
|
||||
|
||||
static struct arm_boot_info kzm_binfo = {
|
||||
.loader_start = KZM_RAM_ADDR,
|
||||
.board_id = 1722,
|
||||
};
|
||||
|
||||
static void kzm_init(MachineState *machine)
|
||||
{
|
||||
IMX31KZM *s = g_new0(IMX31KZM, 1);
|
||||
|
|
@ -121,12 +125,10 @@ static void kzm_init(MachineState *machine)
|
|||
14745600, serial_hd(2), DEVICE_NATIVE_ENDIAN);
|
||||
}
|
||||
|
||||
s->bootinfo.loader_start = KZM_RAM_ADDR;
|
||||
s->bootinfo.board_id = 1722;
|
||||
s->bootinfo.ram_size = machine->ram_size;
|
||||
kzm_binfo.ram_size = machine->ram_size;
|
||||
|
||||
if (!qtest_enabled()) {
|
||||
arm_load_kernel(&s->soc.cpu, machine, &s->bootinfo);
|
||||
arm_load_kernel(&s->soc.cpu, machine, &kzm_binfo);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -22,19 +22,9 @@
|
|||
#include "qemu/error-report.h"
|
||||
#include "system/qtest.h"
|
||||
|
||||
#define TYPE_MCIMX7D_SABRE_MACHINE MACHINE_TYPE_NAME("mcimx7d-sabre")
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(Mcimx7dSabreMachineState,
|
||||
MCIMX7D_SABRE_MACHINE)
|
||||
|
||||
struct Mcimx7dSabreMachineState {
|
||||
MachineState parent;
|
||||
|
||||
struct arm_boot_info bootinfo;
|
||||
};
|
||||
|
||||
static void mcimx7d_sabre_init(MachineState *machine)
|
||||
{
|
||||
Mcimx7dSabreMachineState *msms = MCIMX7D_SABRE_MACHINE(machine);
|
||||
static struct arm_boot_info boot_info;
|
||||
FslIMX7State *s;
|
||||
int i;
|
||||
|
||||
|
|
@ -44,10 +34,12 @@ static void mcimx7d_sabre_init(MachineState *machine)
|
|||
exit(1);
|
||||
}
|
||||
|
||||
msms->bootinfo.loader_start = FSL_IMX7_MMDC_ADDR;
|
||||
msms->bootinfo.board_id = -1;
|
||||
msms->bootinfo.ram_size = machine->ram_size;
|
||||
msms->bootinfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
|
||||
boot_info = (struct arm_boot_info) {
|
||||
.loader_start = FSL_IMX7_MMDC_ADDR,
|
||||
.board_id = -1,
|
||||
.ram_size = machine->ram_size,
|
||||
.psci_conduit = QEMU_PSCI_CONDUIT_SMC,
|
||||
};
|
||||
|
||||
s = FSL_IMX7(object_new(TYPE_FSL_IMX7));
|
||||
object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
|
||||
|
|
@ -73,7 +65,7 @@ static void mcimx7d_sabre_init(MachineState *machine)
|
|||
}
|
||||
|
||||
if (!qtest_enabled()) {
|
||||
arm_load_kernel(&s->cpu[0], machine, &msms->bootinfo);
|
||||
arm_load_kernel(&s->cpu[0], machine, &boot_info);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -86,6 +78,4 @@ static void mcimx7d_sabre_machine_init(MachineClass *mc)
|
|||
mc->auto_create_sdcard = true;
|
||||
}
|
||||
|
||||
DEFINE_MACHINE_EXTENDED("mcimx7d-sabre", MACHINE, Mcimx7dSabreMachineState,
|
||||
mcimx7d_sabre_machine_init, false,
|
||||
arm_machine_interfaces)
|
||||
DEFINE_MACHINE_ARM("mcimx7d-sabre", mcimx7d_sabre_machine_init)
|
||||
|
|
|
|||
|
|
@ -110,12 +110,6 @@ arm_common_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
|
|||
arm_common_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
|
||||
arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
|
||||
|
||||
arm_common_ss.add(when: ['CONFIG_AXIADO_SOC', 'TARGET_AARCH64'], if_true: files(
|
||||
'ax3000-soc.c'))
|
||||
arm_common_ss.add(when: ['CONFIG_AXIADO_EVK', 'TARGET_AARCH64'], if_true: files(
|
||||
'ax3000-boards.c',
|
||||
'ax3000-evk.c'))
|
||||
|
||||
arm_common_ss.add(files('boot.c'))
|
||||
|
||||
hw_common_arch += {'arm': arm_common_ss}
|
||||
|
|
|
|||
|
|
@ -1048,19 +1048,6 @@ static void mps2tz_common_init(MachineState *machine)
|
|||
const PPCInfo an547_ppcs[] = { {
|
||||
.name = "apb_ppcexp0",
|
||||
.ports = {
|
||||
{ /* port 0 USER MEM APB0 */ },
|
||||
{ /* port 1 USER MEM APB0 */ },
|
||||
{ /* port 2 reserved */ },
|
||||
{ /* port 3 reserved */ },
|
||||
{ /* port 4 NPU APB0 */ },
|
||||
{ /* port 5 NPU APB1 */ },
|
||||
{ /* port 6 reserved */ },
|
||||
{ /* port 7 reserved */ },
|
||||
{ /* port 8 reserved */ },
|
||||
{ /* port 9 reserved */ },
|
||||
{ /* port 10 reserved */ },
|
||||
{ /* port 11 reserved */ },
|
||||
{ /* port 12 reserved */ },
|
||||
{ "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 },
|
||||
{ "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 },
|
||||
{ "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 },
|
||||
|
|
@ -1113,14 +1100,6 @@ static void mps2tz_common_init(MachineState *machine)
|
|||
{ /* port 7 USER AHB interface 3 */ },
|
||||
{ "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } },
|
||||
},
|
||||
}, {
|
||||
.name = "ahb_ppcexp1",
|
||||
.ports = {
|
||||
{ /* port 0 reserved */ },
|
||||
{ "dma1", make_dma, &mms->dma[1], 0x41201000, 0x1000, { 62, 60, 61 } },
|
||||
{ "dma2", make_dma, &mms->dma[2], 0x41202000, 0x1000, { 65, 63, 64 } },
|
||||
{ "dma3", make_dma, &mms->dma[3], 0x41203000, 0x1000, { 68, 66, 67 } },
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1200,18 +1200,13 @@ static const TypeInfo musicpal_key_info = {
|
|||
|
||||
#define FLASH_SECTOR_SIZE (64 * KiB)
|
||||
|
||||
#define TYPE_MUSICPAL_MACHINE MACHINE_TYPE_NAME("musicpal")
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(MusicPalMachineState, MUSICPAL_MACHINE)
|
||||
|
||||
struct MusicPalMachineState {
|
||||
MachineState parent;
|
||||
|
||||
struct arm_boot_info bootinfo;
|
||||
static struct arm_boot_info musicpal_binfo = {
|
||||
.loader_start = 0x0,
|
||||
.board_id = 0x20e,
|
||||
};
|
||||
|
||||
static void musicpal_init(MachineState *machine)
|
||||
{
|
||||
MusicPalMachineState *mpms = MUSICPAL_MACHINE(machine);
|
||||
ARMCPU *cpu;
|
||||
DeviceState *dev;
|
||||
DeviceState *pic;
|
||||
|
|
@ -1346,10 +1341,8 @@ static void musicpal_init(MachineState *machine)
|
|||
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
|
||||
sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ));
|
||||
|
||||
mpms->bootinfo.loader_start = 0x0;
|
||||
mpms->bootinfo.board_id = 0x20e;
|
||||
mpms->bootinfo.ram_size = MP_RAM_DEFAULT_SIZE;
|
||||
arm_load_kernel(cpu, machine, &mpms->bootinfo);
|
||||
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
|
||||
arm_load_kernel(cpu, machine, &musicpal_binfo);
|
||||
}
|
||||
|
||||
static void musicpal_machine_init(MachineClass *mc)
|
||||
|
|
@ -1364,9 +1357,7 @@ static void musicpal_machine_init(MachineClass *mc)
|
|||
machine_add_audiodev_property(mc);
|
||||
}
|
||||
|
||||
DEFINE_MACHINE_EXTENDED("musicpal", MACHINE, MusicPalMachineState,
|
||||
musicpal_machine_init, false,
|
||||
arm_machine_interfaces)
|
||||
DEFINE_MACHINE_ARM("musicpal", musicpal_machine_init)
|
||||
|
||||
static void mv88w8618_wlan_class_init(ObjectClass *klass, const void *data)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -364,20 +364,22 @@ static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
|
|||
NPCM7XX_SMP_LOADER_START);
|
||||
}
|
||||
|
||||
void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc,
|
||||
struct arm_boot_info *binfo)
|
||||
{
|
||||
binfo->loader_start = NPCM7XX_LOADER_START;
|
||||
binfo->smp_loader_start = NPCM7XX_SMP_LOADER_START;
|
||||
binfo->smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR;
|
||||
binfo->gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR;
|
||||
binfo->write_secondary_boot = npcm7xx_write_secondary_boot;
|
||||
binfo->board_id = -1;
|
||||
binfo->board_setup_addr = NPCM7XX_BOARD_SETUP_ADDR;
|
||||
binfo->write_board_setup = npcm7xx_write_board_setup;
|
||||
binfo->ram_size = machine->ram_size;
|
||||
static struct arm_boot_info npcm7xx_binfo = {
|
||||
.loader_start = NPCM7XX_LOADER_START,
|
||||
.smp_loader_start = NPCM7XX_SMP_LOADER_START,
|
||||
.smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR,
|
||||
.gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR,
|
||||
.write_secondary_boot = npcm7xx_write_secondary_boot,
|
||||
.board_id = -1,
|
||||
.board_setup_addr = NPCM7XX_BOARD_SETUP_ADDR,
|
||||
.write_board_setup = npcm7xx_write_board_setup,
|
||||
};
|
||||
|
||||
arm_load_kernel(&soc->cpu[0], machine, binfo);
|
||||
void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
|
||||
{
|
||||
npcm7xx_binfo.ram_size = machine->ram_size;
|
||||
|
||||
arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
|
||||
}
|
||||
|
||||
static void npcm7xx_init_fuses(NPCM7xxState *s)
|
||||
|
|
|
|||
|
|
@ -374,7 +374,7 @@ static void npcm750_evb_init(MachineState *machine)
|
|||
npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
|
||||
npcm750_evb_i2c_init(soc);
|
||||
npcm750_evb_fan_init(NPCM7XX_MACHINE(machine), soc);
|
||||
npcm7xx_load_kernel(machine, soc, &NPCM7XX_MACHINE(machine)->bootinfo);
|
||||
npcm7xx_load_kernel(machine, soc);
|
||||
}
|
||||
|
||||
static void quanta_gsj_init(MachineState *machine)
|
||||
|
|
@ -390,7 +390,7 @@ static void quanta_gsj_init(MachineState *machine)
|
|||
drive_get(IF_MTD, 0, 0));
|
||||
quanta_gsj_i2c_init(soc);
|
||||
quanta_gsj_fan_init(NPCM7XX_MACHINE(machine), soc);
|
||||
npcm7xx_load_kernel(machine, soc, &NPCM7XX_MACHINE(machine)->bootinfo);
|
||||
npcm7xx_load_kernel(machine, soc);
|
||||
}
|
||||
|
||||
static void quanta_gbs_init(MachineState *machine)
|
||||
|
|
@ -408,7 +408,7 @@ static void quanta_gbs_init(MachineState *machine)
|
|||
|
||||
quanta_gbs_i2c_init(soc);
|
||||
sdhci_attach_drive(&soc->mmc.sdhci, 0);
|
||||
npcm7xx_load_kernel(machine, soc, &NPCM7XX_MACHINE(machine)->bootinfo);
|
||||
npcm7xx_load_kernel(machine, soc);
|
||||
}
|
||||
|
||||
static void kudo_bmc_init(MachineState *machine)
|
||||
|
|
@ -427,7 +427,7 @@ static void kudo_bmc_init(MachineState *machine)
|
|||
|
||||
kudo_bmc_i2c_init(soc);
|
||||
sdhci_attach_drive(&soc->mmc.sdhci, 0);
|
||||
npcm7xx_load_kernel(machine, soc, &NPCM7XX_MACHINE(machine)->bootinfo);
|
||||
npcm7xx_load_kernel(machine, soc);
|
||||
}
|
||||
|
||||
static void mori_bmc_init(MachineState *machine)
|
||||
|
|
@ -442,7 +442,7 @@ static void mori_bmc_init(MachineState *machine)
|
|||
npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f",
|
||||
drive_get(IF_MTD, 3, 0));
|
||||
|
||||
npcm7xx_load_kernel(machine, soc, &NPCM7XX_MACHINE(machine)->bootinfo);
|
||||
npcm7xx_load_kernel(machine, soc);
|
||||
}
|
||||
|
||||
static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
|
||||
|
|
|
|||
|
|
@ -357,20 +357,22 @@ static const struct {
|
|||
},
|
||||
};
|
||||
|
||||
void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc,
|
||||
struct arm_boot_info *binfo)
|
||||
{
|
||||
binfo->loader_start = NPCM8XX_LOADER_START;
|
||||
binfo->smp_loader_start = NPCM8XX_SMP_LOADER_START;
|
||||
binfo->smp_bootreg_addr = NPCM8XX_SMP_BOOTREG_ADDR;
|
||||
binfo->gic_cpu_if_addr = NPCM8XX_GICC_BA;
|
||||
binfo->secure_boot = false;
|
||||
binfo->board_id = -1;
|
||||
binfo->board_setup_addr = NPCM8XX_BOARD_SETUP_ADDR;
|
||||
binfo->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
|
||||
binfo->ram_size = machine->ram_size;
|
||||
static struct arm_boot_info npcm8xx_binfo = {
|
||||
.loader_start = NPCM8XX_LOADER_START,
|
||||
.smp_loader_start = NPCM8XX_SMP_LOADER_START,
|
||||
.smp_bootreg_addr = NPCM8XX_SMP_BOOTREG_ADDR,
|
||||
.gic_cpu_if_addr = NPCM8XX_GICC_BA,
|
||||
.secure_boot = false,
|
||||
.board_id = -1,
|
||||
.board_setup_addr = NPCM8XX_BOARD_SETUP_ADDR,
|
||||
.psci_conduit = QEMU_PSCI_CONDUIT_SMC,
|
||||
};
|
||||
|
||||
arm_load_kernel(&soc->cpu[0], machine, binfo);
|
||||
void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc)
|
||||
{
|
||||
npcm8xx_binfo.ram_size = machine->ram_size;
|
||||
|
||||
arm_load_kernel(&soc->cpu[0], machine, &npcm8xx_binfo);
|
||||
}
|
||||
|
||||
static void npcm8xx_init_fuses(NPCM8xxState *s)
|
||||
|
|
|
|||
|
|
@ -198,7 +198,7 @@ static void npcm845_evb_init(MachineState *machine)
|
|||
npcm8xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
|
||||
npcm845_evb_i2c_init(soc);
|
||||
npcm845_evb_fan_init(NPCM8XX_MACHINE(machine), soc);
|
||||
npcm8xx_load_kernel(machine, soc, &NPCM8XX_MACHINE(machine)->bootinfo);
|
||||
npcm8xx_load_kernel(machine, soc);
|
||||
}
|
||||
|
||||
static void npcm8xx_set_soc_type(NPCM8xxMachineClass *nmc, const char *type)
|
||||
|
|
|
|||
|
|
@ -91,16 +91,14 @@ static const MemoryRegionOps static_ops = {
|
|||
#define FLASH1_SIZE (8 * MiB)
|
||||
#define FLASH2_SIZE (32 * MiB)
|
||||
|
||||
typedef struct Sx1MachineState {
|
||||
MachineState parent;
|
||||
|
||||
struct arm_boot_info bootinfo;
|
||||
} Sx1MachineState;
|
||||
static struct arm_boot_info sx1_binfo = {
|
||||
.loader_start = OMAP_EMIFF_BASE,
|
||||
.ram_size = SDRAM_SIZE,
|
||||
.board_id = 0x265,
|
||||
};
|
||||
|
||||
static void sx1_init(MachineState *machine, const int version)
|
||||
{
|
||||
/* Both sx1 and sx1-v1 embed the same state as their first member */
|
||||
Sx1MachineState *sms = (Sx1MachineState *)machine;
|
||||
struct omap_mpu_state_s *mpu;
|
||||
MachineClass *mc = MACHINE_GET_CLASS(machine);
|
||||
MemoryRegion *address_space = get_system_memory();
|
||||
|
|
@ -189,10 +187,7 @@ static void sx1_init(MachineState *machine, const int version)
|
|||
}
|
||||
|
||||
/* Load the kernel. */
|
||||
sms->bootinfo.loader_start = OMAP_EMIFF_BASE;
|
||||
sms->bootinfo.ram_size = SDRAM_SIZE;
|
||||
sms->bootinfo.board_id = 0x265;
|
||||
arm_load_kernel(mpu->cpu, machine, &sms->bootinfo);
|
||||
arm_load_kernel(mpu->cpu, machine, &sx1_binfo);
|
||||
|
||||
/* TODO: fix next line */
|
||||
//~ qemu_console_resize(ds, 640, 480);
|
||||
|
|
@ -225,7 +220,6 @@ static const TypeInfo sx1_machine_v2_type = {
|
|||
.name = MACHINE_TYPE_NAME("sx1"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = sx1_machine_v2_class_init,
|
||||
.instance_size = sizeof(Sx1MachineState),
|
||||
.interfaces = arm_machine_interfaces,
|
||||
};
|
||||
|
||||
|
|
@ -246,7 +240,6 @@ static const TypeInfo sx1_machine_v1_type = {
|
|||
.name = MACHINE_TYPE_NAME("sx1-v1"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = sx1_machine_v1_class_init,
|
||||
.instance_size = sizeof(Sx1MachineState),
|
||||
.interfaces = arm_machine_interfaces,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -28,18 +28,10 @@
|
|||
#include "hw/arm/boot.h"
|
||||
#include "hw/arm/machines-qom.h"
|
||||
|
||||
#define TYPE_ORANGEPI_MACHINE MACHINE_TYPE_NAME("orangepi-pc")
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(OrangePiMachineState, ORANGEPI_MACHINE)
|
||||
|
||||
struct OrangePiMachineState {
|
||||
MachineState parent;
|
||||
|
||||
struct arm_boot_info bootinfo;
|
||||
};
|
||||
static struct arm_boot_info orangepi_binfo;
|
||||
|
||||
static void orangepi_init(MachineState *machine)
|
||||
{
|
||||
OrangePiMachineState *opms = ORANGEPI_MACHINE(machine);
|
||||
AwH3State *h3;
|
||||
DriveInfo *di;
|
||||
BlockBackend *blk;
|
||||
|
|
@ -106,10 +98,10 @@ static void orangepi_init(MachineState *machine)
|
|||
/* Use Boot ROM to copy data from SD card to SRAM */
|
||||
allwinner_h3_bootrom_setup(h3, blk);
|
||||
}
|
||||
opms->bootinfo.loader_start = h3->memmap[AW_H3_DEV_SDRAM];
|
||||
opms->bootinfo.ram_size = machine->ram_size;
|
||||
opms->bootinfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
|
||||
arm_load_kernel(&h3->cpus[0], machine, &opms->bootinfo);
|
||||
orangepi_binfo.loader_start = h3->memmap[AW_H3_DEV_SDRAM];
|
||||
orangepi_binfo.ram_size = machine->ram_size;
|
||||
orangepi_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
|
||||
arm_load_kernel(&h3->cpus[0], machine, &orangepi_binfo);
|
||||
}
|
||||
|
||||
static void orangepi_machine_init(MachineClass *mc)
|
||||
|
|
@ -133,6 +125,4 @@ static void orangepi_machine_init(MachineClass *mc)
|
|||
mc->auto_create_sdcard = true;
|
||||
}
|
||||
|
||||
DEFINE_MACHINE_EXTENDED("orangepi-pc", MACHINE, OrangePiMachineState,
|
||||
orangepi_machine_init, false,
|
||||
arm_machine_interfaces)
|
||||
DEFINE_MACHINE_ARM("orangepi-pc", orangepi_machine_init)
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ static void raspi4_modify_dtb(const struct arm_boot_info *info, void *fdt)
|
|||
|
||||
ram_size = board_ram_size(info->board_id);
|
||||
|
||||
if (ram_size > UPPER_RAM_BASE) {
|
||||
if (info->ram_size > UPPER_RAM_BASE) {
|
||||
raspi_add_memory_node(fdt, UPPER_RAM_BASE, ram_size - UPPER_RAM_BASE);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -39,11 +39,10 @@
|
|||
|
||||
/* Board init. */
|
||||
|
||||
typedef struct RealViewMachineState {
|
||||
MachineState parent;
|
||||
|
||||
struct arm_boot_info bootinfo;
|
||||
} RealViewMachineState;
|
||||
static struct arm_boot_info realview_binfo = {
|
||||
.smp_loader_start = SMP_BOOT_ADDR,
|
||||
.smp_bootreg_addr = SMP_BOOTREG_ADDR,
|
||||
};
|
||||
|
||||
/* The following two lists must be consistent. */
|
||||
enum realview_board_type {
|
||||
|
|
@ -77,8 +76,6 @@ static void split_irq_from_named(DeviceState *src, const char* outname,
|
|||
static void realview_init(MachineState *machine,
|
||||
enum realview_board_type board_type)
|
||||
{
|
||||
/* All realview-* machines embed the same state as their first member */
|
||||
RealViewMachineState *rvms = (RealViewMachineState *)machine;
|
||||
ARMCPU *cpu = NULL;
|
||||
CPUARMState *env;
|
||||
MemoryRegion *sysmem = get_system_memory();
|
||||
|
|
@ -205,7 +202,7 @@ static void realview_init(MachineState *machine,
|
|||
}
|
||||
sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL);
|
||||
/* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */
|
||||
rvms->bootinfo.gic_cpu_if_addr = periphbase + 0x100;
|
||||
realview_binfo.gic_cpu_if_addr = periphbase + 0x100;
|
||||
} else {
|
||||
uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
|
||||
/* For now just create the nIRQ GIC, and ignore the others. */
|
||||
|
|
@ -390,12 +387,10 @@ static void realview_init(MachineState *machine,
|
|||
&error_fatal);
|
||||
memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
|
||||
|
||||
rvms->bootinfo.smp_loader_start = SMP_BOOT_ADDR;
|
||||
rvms->bootinfo.smp_bootreg_addr = SMP_BOOTREG_ADDR;
|
||||
rvms->bootinfo.ram_size = ram_size;
|
||||
rvms->bootinfo.board_id = realview_board_id[board_type];
|
||||
rvms->bootinfo.loader_start = board_type == BOARD_PB_A8 ? 0x70000000 : 0;
|
||||
arm_load_kernel(cpu, machine, &rvms->bootinfo);
|
||||
realview_binfo.ram_size = ram_size;
|
||||
realview_binfo.board_id = realview_board_id[board_type];
|
||||
realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
|
||||
arm_load_kernel(cpu, machine, &realview_binfo);
|
||||
}
|
||||
|
||||
static void realview_eb_init(MachineState *machine)
|
||||
|
|
@ -436,7 +431,6 @@ static const TypeInfo realview_eb_type = {
|
|||
.name = MACHINE_TYPE_NAME("realview-eb"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = realview_eb_class_init,
|
||||
.instance_size = sizeof(RealViewMachineState),
|
||||
.interfaces = arm_machine_interfaces,
|
||||
};
|
||||
|
||||
|
|
@ -459,7 +453,6 @@ static const TypeInfo realview_eb_mpcore_type = {
|
|||
.name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = realview_eb_mpcore_class_init,
|
||||
.instance_size = sizeof(RealViewMachineState),
|
||||
.interfaces = arm_machine_interfaces,
|
||||
};
|
||||
|
||||
|
|
@ -480,7 +473,6 @@ static const TypeInfo realview_pb_a8_type = {
|
|||
.name = MACHINE_TYPE_NAME("realview-pb-a8"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = realview_pb_a8_class_init,
|
||||
.instance_size = sizeof(RealViewMachineState),
|
||||
.interfaces = arm_machine_interfaces,
|
||||
};
|
||||
|
||||
|
|
@ -502,7 +494,6 @@ static const TypeInfo realview_pbx_a9_type = {
|
|||
.name = MACHINE_TYPE_NAME("realview-pbx-a9"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = realview_pbx_a9_class_init,
|
||||
.instance_size = sizeof(RealViewMachineState),
|
||||
.interfaces = arm_machine_interfaces,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -25,12 +25,18 @@ struct SabreliteMachineState {
|
|||
|
||||
FslIMX6State soc;
|
||||
CanBusState *canbus[FSL_IMX6_NUM_CANS];
|
||||
struct arm_boot_info bootinfo;
|
||||
};
|
||||
|
||||
#define TYPE_SABRELITE_MACHINE MACHINE_TYPE_NAME("sabrelite")
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(SabreliteMachineState, SABRELITE_MACHINE)
|
||||
|
||||
static struct arm_boot_info sabrelite_binfo = {
|
||||
/* DDR memory start */
|
||||
.loader_start = FSL_IMX6_MMDC_ADDR,
|
||||
/* No board ID, we boot from DT tree */
|
||||
.board_id = -1,
|
||||
};
|
||||
|
||||
/* No need to do any particular setup for secondary boot */
|
||||
static void sabrelite_write_secondary(ARMCPU *cpu,
|
||||
const struct arm_boot_info *info)
|
||||
|
|
@ -104,17 +110,13 @@ static void sabrelite_init(MachineState *machine)
|
|||
}
|
||||
}
|
||||
|
||||
/* DDR memory start */
|
||||
s->bootinfo.loader_start = FSL_IMX6_MMDC_ADDR;
|
||||
/* No board ID, we boot from DT tree */
|
||||
s->bootinfo.board_id = -1;
|
||||
s->bootinfo.ram_size = machine->ram_size;
|
||||
s->bootinfo.secure_boot = true;
|
||||
s->bootinfo.write_secondary_boot = sabrelite_write_secondary;
|
||||
s->bootinfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
|
||||
sabrelite_binfo.ram_size = machine->ram_size;
|
||||
sabrelite_binfo.secure_boot = true;
|
||||
sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary;
|
||||
sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
|
||||
|
||||
if (!qtest_enabled()) {
|
||||
arm_load_kernel(&s->soc.cpu[0], machine, &s->bootinfo);
|
||||
arm_load_kernel(&s->soc.cpu[0], machine, &sabrelite_binfo);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -182,16 +182,10 @@ static void vpb_sic_init(Object *obj)
|
|||
peripherals and expansion busses. For now we emulate a subset of the
|
||||
PB peripherals and just change the board ID. */
|
||||
|
||||
typedef struct VersatileMachineState {
|
||||
MachineState parent;
|
||||
|
||||
struct arm_boot_info bootinfo;
|
||||
} VersatileMachineState;
|
||||
static struct arm_boot_info versatile_binfo;
|
||||
|
||||
static void versatile_init(MachineState *machine, int board_id)
|
||||
{
|
||||
/* versatilepb and versatileab embed the same state as first member */
|
||||
VersatileMachineState *vms = (VersatileMachineState *)machine;
|
||||
Object *cpuobj;
|
||||
ARMCPU *cpu;
|
||||
MemoryRegion *sysmem = get_system_memory();
|
||||
|
|
@ -403,9 +397,9 @@ static void versatile_init(MachineState *machine, int board_id)
|
|||
VERSATILE_FLASH_SECT_SIZE,
|
||||
4, 0x0089, 0x0018, 0x0000, 0x0, 0);
|
||||
|
||||
vms->bootinfo.ram_size = machine->ram_size;
|
||||
vms->bootinfo.board_id = board_id;
|
||||
arm_load_kernel(cpu, machine, &vms->bootinfo);
|
||||
versatile_binfo.ram_size = machine->ram_size;
|
||||
versatile_binfo.board_id = board_id;
|
||||
arm_load_kernel(cpu, machine, &versatile_binfo);
|
||||
}
|
||||
|
||||
static void vpb_init(MachineState *machine)
|
||||
|
|
@ -437,7 +431,6 @@ static const TypeInfo versatilepb_type = {
|
|||
.name = MACHINE_TYPE_NAME("versatilepb"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = versatilepb_class_init,
|
||||
.instance_size = sizeof(VersatileMachineState),
|
||||
.interfaces = arm_machine_interfaces,
|
||||
};
|
||||
|
||||
|
|
@ -460,7 +453,6 @@ static const TypeInfo versatileab_type = {
|
|||
.name = MACHINE_TYPE_NAME("versatileab"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = versatileab_class_init,
|
||||
.instance_size = sizeof(VersatileMachineState),
|
||||
.interfaces = arm_machine_interfaces,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -4441,17 +4441,10 @@ static void machvirt_machine_init(void)
|
|||
}
|
||||
type_init(machvirt_machine_init);
|
||||
|
||||
static void virt_machine_11_2_options(MachineClass *mc)
|
||||
{
|
||||
}
|
||||
DEFINE_VIRT_MACHINE_AS_LATEST(11, 2)
|
||||
|
||||
static void virt_machine_11_1_options(MachineClass *mc)
|
||||
{
|
||||
virt_machine_11_2_options(mc);
|
||||
compat_props_add(mc->compat_props, hw_compat_11_1, hw_compat_11_1_len);
|
||||
}
|
||||
DEFINE_VIRT_MACHINE(11, 1)
|
||||
DEFINE_VIRT_MACHINE_AS_LATEST(11, 1)
|
||||
|
||||
static void virt_machine_11_0_options(MachineClass *mc)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -103,6 +103,8 @@ static void zynq_write_board_setup(ARMCPU *cpu,
|
|||
sizeof(board_setup_blob), BOARD_SETUP_ADDR);
|
||||
}
|
||||
|
||||
static struct arm_boot_info zynq_binfo = {};
|
||||
|
||||
static void gem_init(uint32_t base, qemu_irq irq)
|
||||
{
|
||||
DeviceState *dev;
|
||||
|
|
@ -266,7 +268,7 @@ static void zynq_init(MachineState *machine)
|
|||
busdev = SYS_BUS_DEVICE(dev);
|
||||
sysbus_realize_and_unref(busdev, &error_fatal);
|
||||
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
|
||||
zynq_machine->bootinfo.gic_cpu_if_addr = MPCORE_PERIPHBASE + 0x100;
|
||||
zynq_binfo.gic_cpu_if_addr = MPCORE_PERIPHBASE + 0x100;
|
||||
sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL);
|
||||
for (n = 0; n < smp_cpus; n++) {
|
||||
/* See "hw/intc/arm_gic.h" for the IRQ line association */
|
||||
|
|
@ -442,14 +444,13 @@ static void zynq_init(MachineState *machine)
|
|||
create_unimplemented_device("zynq.qos301_dmac", 0xF8947000, 0x130);
|
||||
create_unimplemented_device("zynq.qos301_iou", 0xF8948000, 0x130);
|
||||
|
||||
zynq_machine->bootinfo.ram_size = machine->ram_size;
|
||||
zynq_machine->bootinfo.board_id = 0xd32;
|
||||
zynq_machine->bootinfo.loader_start = 0;
|
||||
zynq_machine->bootinfo.board_setup_addr = BOARD_SETUP_ADDR;
|
||||
zynq_machine->bootinfo.write_board_setup = zynq_write_board_setup;
|
||||
zynq_binfo.ram_size = machine->ram_size;
|
||||
zynq_binfo.board_id = 0xd32;
|
||||
zynq_binfo.loader_start = 0;
|
||||
zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
|
||||
zynq_binfo.write_board_setup = zynq_write_board_setup;
|
||||
|
||||
arm_load_kernel(zynq_machine->cpu[0], machine,
|
||||
&zynq_machine->bootinfo);
|
||||
arm_load_kernel(zynq_machine->cpu[0], machine, &zynq_binfo);
|
||||
}
|
||||
|
||||
static void zynq_machine_class_init(ObjectClass *oc, const void *data)
|
||||
|
|
|
|||
|
|
@ -196,12 +196,6 @@ static void fd_init(FDrive *drv)
|
|||
|
||||
#define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
|
||||
|
||||
/* Is a diskette present in the drive? */
|
||||
static bool fd_media_present(FDrive *drv)
|
||||
{
|
||||
return drv->blk != NULL && blk_is_inserted(drv->blk);
|
||||
}
|
||||
|
||||
static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
|
||||
uint8_t last_sect, uint8_t num_sides)
|
||||
{
|
||||
|
|
@ -228,7 +222,6 @@ static int fd_offset(FDrive *drv)
|
|||
* returns 2 if track is invalid
|
||||
* returns 3 if sector is invalid
|
||||
* returns 4 if seek is disabled
|
||||
* returns 5 if no floppy is inserted
|
||||
*/
|
||||
static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
|
||||
int enable_seek)
|
||||
|
|
@ -265,7 +258,7 @@ static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
|
|||
#endif
|
||||
drv->head = head;
|
||||
if (drv->track != track) {
|
||||
if (fd_media_present(drv)) {
|
||||
if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
|
||||
drv->media_changed = 0;
|
||||
}
|
||||
ret = 1;
|
||||
|
|
@ -274,8 +267,8 @@ static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
|
|||
drv->sect = sect;
|
||||
}
|
||||
|
||||
if (!fd_media_present(drv)) {
|
||||
ret = 5;
|
||||
if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
|
||||
ret = 2;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -1483,24 +1476,14 @@ static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
|
|||
NUM_SIDES(cur_drv)));
|
||||
switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
|
||||
case 2:
|
||||
/* track/head out of range */
|
||||
/* sect too big */
|
||||
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
|
||||
fdctrl->fifo[3] = kt;
|
||||
fdctrl->fifo[4] = kh;
|
||||
fdctrl->fifo[5] = ks;
|
||||
return;
|
||||
case 5:
|
||||
/*
|
||||
* No medium: there is no address mark to be found. Guests that tell
|
||||
* an absent diskette from an unreadable one rely on ST1.MA.
|
||||
*/
|
||||
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
|
||||
fdctrl->fifo[3] = kt;
|
||||
fdctrl->fifo[4] = kh;
|
||||
fdctrl->fifo[5] = ks;
|
||||
return;
|
||||
case 3:
|
||||
/* sector too big */
|
||||
/* track too big */
|
||||
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
|
||||
fdctrl->fifo[3] = kt;
|
||||
fdctrl->fifo[4] = kh;
|
||||
|
|
@ -1808,21 +1791,14 @@ static void fdctrl_format_sector(FDCtrl *fdctrl)
|
|||
NUM_SIDES(cur_drv)));
|
||||
switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
|
||||
case 2:
|
||||
/* track/head out of range */
|
||||
/* sect too big */
|
||||
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
|
||||
fdctrl->fifo[3] = kt;
|
||||
fdctrl->fifo[4] = kh;
|
||||
fdctrl->fifo[5] = ks;
|
||||
return;
|
||||
case 5:
|
||||
/* no medium */
|
||||
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
|
||||
fdctrl->fifo[3] = kt;
|
||||
fdctrl->fifo[4] = kh;
|
||||
fdctrl->fifo[5] = ks;
|
||||
return;
|
||||
case 3:
|
||||
/* sector too big */
|
||||
/* track too big */
|
||||
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
|
||||
fdctrl->fifo[3] = kt;
|
||||
fdctrl->fifo[4] = kh;
|
||||
|
|
@ -1960,10 +1936,7 @@ static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
|
|||
|
||||
static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
|
||||
{
|
||||
FDrive *cur_drv;
|
||||
|
||||
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
||||
cur_drv = get_cur_drv(fdctrl);
|
||||
FDrive *cur_drv = get_cur_drv(fdctrl);
|
||||
|
||||
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
|
||||
timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
|
||||
|
|
@ -2330,18 +2303,6 @@ static void fdctrl_result_timer(void *opaque)
|
|||
FDCtrl *fdctrl = opaque;
|
||||
FDrive *cur_drv = get_cur_drv(fdctrl);
|
||||
|
||||
/*
|
||||
* An empty drive has no address marks to read. Completing READ ID
|
||||
* successfully, with the made-up sector ID left over from the "spinning"
|
||||
* emulation below, tells the guest that a diskette is still present after
|
||||
* it has been ejected. The only error path left was a data rate mismatch,
|
||||
* and media_rate is never reset when the medium is removed.
|
||||
*/
|
||||
if (!fd_media_present(cur_drv)) {
|
||||
FLOPPY_DPRINTF("read id on empty drive\n");
|
||||
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
|
||||
return;
|
||||
}
|
||||
/* Pretend we are spinning.
|
||||
* This is needed for Coherent, which uses READ ID to check for
|
||||
* sector interleaving.
|
||||
|
|
|
|||
|
|
@ -1030,16 +1030,6 @@ static int pflash_post_load(void *opaque, int version_id)
|
|||
{
|
||||
PFlashCFI01 *pfl = opaque;
|
||||
|
||||
/*
|
||||
* ROMD mode is not in the VMState; derive it from the migrated
|
||||
* cmd and wcycle. Only (wcycle == 0, cmd == 0x00) is read-array.
|
||||
*/
|
||||
if (pfl->wcycle == 0 && pfl->cmd == 0x00) {
|
||||
memory_region_rom_device_set_romd(&pfl->mem, true);
|
||||
} else {
|
||||
memory_region_rom_device_set_romd(&pfl->mem, false);
|
||||
}
|
||||
|
||||
if (!pfl->ro) {
|
||||
pfl->vmstate = qemu_add_vm_change_state_handler(postload_update_cb,
|
||||
pfl);
|
||||
|
|
|
|||
|
|
@ -243,8 +243,7 @@ static int write_event_data(SCLPEvent *event, EventBufferHeader *ebh)
|
|||
SCLPConsoleLM *scon = SCLPLM_CONSOLE(event);
|
||||
|
||||
len = be16_to_cpu(data->mdb.header.length);
|
||||
if (len < sizeof(data->mdb.header) ||
|
||||
len > be16_to_cpu(data->header.length) - sizeof(EventBufferHeader)) {
|
||||
if (len < sizeof(data->mdb.header)) {
|
||||
return SCLP_RC_INCONSISTENT_LENGTHS;
|
||||
}
|
||||
len -= sizeof(data->mdb.header);
|
||||
|
|
|
|||
|
|
@ -936,7 +936,6 @@ static void serial_unrealize(DeviceState *dev)
|
|||
{
|
||||
SerialState *s = SERIAL(dev);
|
||||
|
||||
g_clear_handle_id(&s->watch_tag, g_source_remove);
|
||||
qemu_chr_fe_deinit(&s->chr, false);
|
||||
|
||||
timer_free(s->modem_status_poll);
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue