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b3fa882508
The PCA9536 shares the PCA9554 register map and code path but exposes only four pins. Add a pca9536 node and check its reset defaults and output-to-input reflection are masked to the low nibble. Signed-off-by: Emmanuel Blot <emmanuel.blot@free.fr> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260709-catalina-upgrade-v1-23-82a63fead90c@free.fr Signed-off-by: Cédric Le Goater <clg@redhat.com>
223 lines
7.7 KiB
C
223 lines
7.7 KiB
C
/*
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* QTest testcase for the PCA9554/PCA9536 I/O port expanders
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*
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* Copyright (c) Meta Platforms, Inc. and affiliates. (http://www.meta.com)
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "hw/gpio/pca9554_regs.h"
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#include "libqos/i2c.h"
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#include "libqos/qgraph.h"
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#define PCA9554_TEST_ADDR 0x20
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/* Verify power-on reset defaults match the PCA9554 datasheet. */
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static void test_reset_defaults(void *obj, void *data, QGuestAllocator *alloc)
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{
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QI2CDevice *dev = (QI2CDevice *)obj;
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/* All pins are inputs, pulled high, with no polarity inversion. */
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0xFF);
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g_assert_cmphex(i2c_get8(dev, PCA9554_OUTPUT), ==, 0xFF);
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g_assert_cmphex(i2c_get8(dev, PCA9554_POLARITY), ==, 0x00);
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g_assert_cmphex(i2c_get8(dev, PCA9554_CONFIG), ==, 0xFF);
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}
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/*
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* A pin configured as output (config=0) drives its OUTPUT register level onto
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* the pin (push-pull), which the INPUT register reflects. A pin configured as
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* input (config=1) floats high through its pull-up.
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*/
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static void test_output_drives_input(void *obj, void *data,
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QGuestAllocator *alloc)
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{
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QI2CDevice *dev = (QI2CDevice *)obj;
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/* Low nibble output, high nibble input (pull-up). */
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i2c_set8(dev, PCA9554_CONFIG, 0xF0);
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i2c_set8(dev, PCA9554_OUTPUT, 0xFA);
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0xFA);
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/* All outputs, driven low then high. */
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i2c_set8(dev, PCA9554_CONFIG, 0x00);
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i2c_set8(dev, PCA9554_OUTPUT, 0x00);
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0x00);
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i2c_set8(dev, PCA9554_OUTPUT, 0xFF);
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0xFF);
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}
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/*
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* With all pins configured as inputs the pull-ups make the INPUT register read
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* all ones regardless of the OUTPUT register; switching a pin to output with
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* output=0 drives it low.
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*/
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static void test_input_pullup(void *obj, void *data, QGuestAllocator *alloc)
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{
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QI2CDevice *dev = (QI2CDevice *)obj;
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0xFF);
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i2c_set8(dev, PCA9554_OUTPUT, 0x00);
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0xFF);
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i2c_set8(dev, PCA9554_CONFIG, 0x00);
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0x00);
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}
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/*
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* Polarity inversion: reading INPUT returns the XOR of the pin levels and the
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* polarity register.
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*/
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static void test_polarity_inversion(void *obj, void *data,
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QGuestAllocator *alloc)
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{
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QI2CDevice *dev = (QI2CDevice *)obj;
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0xFF);
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i2c_set8(dev, PCA9554_POLARITY, 0xFF);
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0x00);
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i2c_set8(dev, PCA9554_POLARITY, 0x0F);
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0xF0);
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}
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/* Polarity inversion combined with output-driven pins. */
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static void test_polarity_with_output(void *obj, void *data,
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QGuestAllocator *alloc)
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{
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QI2CDevice *dev = (QI2CDevice *)obj;
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i2c_set8(dev, PCA9554_CONFIG, 0x00);
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i2c_set8(dev, PCA9554_OUTPUT, 0xA5);
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0xA5);
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i2c_set8(dev, PCA9554_POLARITY, 0xFF);
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0x5A);
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/* Inversion only affects the INPUT read, not the OUTPUT register. */
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g_assert_cmphex(i2c_get8(dev, PCA9554_OUTPUT), ==, 0xA5);
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}
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/*
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* The PCA9554 has no auto-increment: the command pointer never advances, so
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* multi-byte reads and writes all target the addressed register.
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*/
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static void test_no_autoincrement(void *obj, void *data,
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QGuestAllocator *alloc)
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{
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QI2CDevice *dev = (QI2CDevice *)obj;
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uint8_t buf[2];
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/* Distinct values in adjacent registers. */
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i2c_set8(dev, PCA9554_OUTPUT, 0xAA);
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i2c_set8(dev, PCA9554_POLARITY, 0x33);
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/* Two reads from OUTPUT return OUTPUT twice, not OUTPUT then POLARITY. */
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i2c_read_block(dev, PCA9554_OUTPUT, buf, 2);
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g_assert_cmphex(buf[0], ==, 0xAA);
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g_assert_cmphex(buf[1], ==, 0xAA);
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/* The second written byte overwrites OUTPUT; POLARITY is untouched. */
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buf[0] = 0x12;
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buf[1] = 0x34;
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i2c_write_block(dev, PCA9554_OUTPUT, buf, 2);
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g_assert_cmphex(i2c_get8(dev, PCA9554_OUTPUT), ==, 0x34);
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g_assert_cmphex(i2c_get8(dev, PCA9554_POLARITY), ==, 0x33);
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}
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/*
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* The PCA9536 shares the PCA9554 register map but only has four pins, so its
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* reset defaults and pin logic are masked to the low nibble.
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*/
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static void test_pca9536_reset_defaults(void *obj, void *data,
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QGuestAllocator *alloc)
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{
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QI2CDevice *dev = (QI2CDevice *)obj;
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0x0F);
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g_assert_cmphex(i2c_get8(dev, PCA9554_OUTPUT), ==, 0x0F);
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g_assert_cmphex(i2c_get8(dev, PCA9554_POLARITY), ==, 0x00);
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g_assert_cmphex(i2c_get8(dev, PCA9554_CONFIG), ==, 0x0F);
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}
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/* Only the four low pins are driven; the upper nibble stays low. */
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static void test_pca9536_output_drives_input(void *obj, void *data,
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QGuestAllocator *alloc)
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{
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QI2CDevice *dev = (QI2CDevice *)obj;
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i2c_set8(dev, PCA9554_CONFIG, 0x00);
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i2c_set8(dev, PCA9554_OUTPUT, 0x0A);
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0x0A);
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i2c_set8(dev, PCA9554_OUTPUT, 0x00);
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0x00);
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}
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/*
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* The four upper bits address pins that do not exist on the PCA9536, so writes
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* to the register map discard them: the writable registers read back with bits
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* [7:4] cleared, and driving them onto the pins never surfaces in INPUT.
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*/
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static void test_pca9536_ignores_upper_bits(void *obj, void *data,
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QGuestAllocator *alloc)
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{
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QI2CDevice *dev = (QI2CDevice *)obj;
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/* Bits [7:4] are dropped on write; bits [3:0] survive. */
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i2c_set8(dev, PCA9554_OUTPUT, 0xFA);
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g_assert_cmphex(i2c_get8(dev, PCA9554_OUTPUT), ==, 0x0A);
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i2c_set8(dev, PCA9554_POLARITY, 0xF5);
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g_assert_cmphex(i2c_get8(dev, PCA9554_POLARITY), ==, 0x05);
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i2c_set8(dev, PCA9554_CONFIG, 0xF3);
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g_assert_cmphex(i2c_get8(dev, PCA9554_CONFIG), ==, 0x03);
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/*
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* With all four pins as outputs, driving 0xFF only affects the low
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* nibble.
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*/
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i2c_set8(dev, PCA9554_POLARITY, 0x00);
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i2c_set8(dev, PCA9554_CONFIG, 0x00);
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i2c_set8(dev, PCA9554_OUTPUT, 0xFF);
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g_assert_cmphex(i2c_get8(dev, PCA9554_INPUT), ==, 0x0F);
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}
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static void pca9554_register_nodes(void)
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{
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QOSGraphEdgeOptions opts = {
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.extra_device_opts = "address=0x20"
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};
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add_qi2c_address(&opts, &(QI2CAddress) { PCA9554_TEST_ADDR });
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qos_node_create_driver("pca9554", i2c_device_create);
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qos_node_consumes("pca9554", "i2c-bus", &opts);
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qos_add_test("reset-defaults", "pca9554", test_reset_defaults, NULL);
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qos_add_test("output-drives-input", "pca9554", test_output_drives_input,
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NULL);
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qos_add_test("input-pullup", "pca9554", test_input_pullup, NULL);
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qos_add_test("polarity-inversion", "pca9554", test_polarity_inversion,
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NULL);
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qos_add_test("polarity-with-output", "pca9554", test_polarity_with_output,
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NULL);
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qos_add_test("no-autoincrement", "pca9554", test_no_autoincrement, NULL);
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qos_node_create_driver("pca9536", i2c_device_create);
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qos_node_consumes("pca9536", "i2c-bus", &opts);
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qos_add_test("reset-defaults", "pca9536", test_pca9536_reset_defaults,
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NULL);
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qos_add_test("output-drives-input", "pca9536",
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test_pca9536_output_drives_input, NULL);
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qos_add_test("ignores-upper-bits", "pca9536",
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test_pca9536_ignores_upper_bits, NULL);
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}
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libqos_init(pca9554_register_nodes);
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