uefi-ref/yasm
1
0
Fork 0
mirror of https://github.com/yasm/yasm synced 2026-08-26 22:26:05 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Add support for Nehalem XSAVE instructions and CPU feature.

Browse source 
svn path=/trunk/yasm/; revision=2042
This commit is contained in:
Peter Johnson 2008-02-22 04:48:56 +00:00
parent 6ced647e97
commit 11ca8fd324
6 changed files with 40 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

12
modules/arch/x86/gen_x86_insn.py
View file

@ -5323,6 +5323,18 @@ add_insn("pshaq", "sse5psh", modifiers=[0x07])
# roundps, roundpd, roundss, roundsd, ptest are in SSE4.1
#####################################################################
# Intel XSAVE instructions
#####################################################################
add_insn("xgetbv", "threebyte", modifiers=[0x0F, 0x01, 0xD0],
cpu=["XSAVE", "386"])
add_insn("xsetbv", "threebyte", modifiers=[0x0F, 0x01, 0xD1],
cpu=["XSAVE", "386", "Priv"])
add_insn("xsave", "twobytemem", modifiers=[4, 0x0F, 0xAE],
cpu=["XSAVE", "386"])
add_insn("xrstor", "twobytemem", modifiers=[5, 0x0F, 0xAE],
cpu=["XSAVE", "386"])
#####################################################################
# AMD 3DNow! instructions
#####################################################################

2
modules/arch/x86/tests/Makefile.inc
View file

@ -204,6 +204,8 @@ EXTRA_DIST += modules/arch/x86/tests/xchg64.asm
EXTRA_DIST += modules/arch/x86/tests/xchg64.hex
EXTRA_DIST += modules/arch/x86/tests/xmm64.asm
EXTRA_DIST += modules/arch/x86/tests/xmm64.hex
EXTRA_DIST += modules/arch/x86/tests/xsave.asm
EXTRA_DIST += modules/arch/x86/tests/xsave.hex
EXTRA_DIST += modules/arch/x86/tests/gas32/Makefile.inc
EXTRA_DIST += modules/arch/x86/tests/gas64/Makefile.inc

4
modules/arch/x86/tests/xsave.asm Normal file
View file

@ -0,0 +1,4 @@
xsave [0]
xrstor [0]
xgetbv
xsetbv

16
modules/arch/x86/tests/xsave.hex Normal file
View file

@ -0,0 +1,16 @@
0f
ae
26
00
00
0f
ae
2e
00
00
0f
01
d0
0f
01
d1

1
modules/arch/x86/x86arch.h
View file

@ -65,6 +65,7 @@
#define CPU_SSE42 31 /* Streaming SIMD extensions 4.2 required */
#define CPU_SSE4a 32 /* AMD Streaming SIMD extensions 4a required */
#define CPU_SSE5 33 /* AMD Streaming SIMD extensions 5 required */
#define CPU_XSAVE 33 /* Intel XSAVE instruction */
/* Technically not CPU capabilities, they do affect what instructions are
* available. These are tested against BITS==64.

6
modules/arch/x86/x86cpu.gperf
View file

@ -58,8 +58,10 @@ x86_cpu_intel(wordptr cpu, unsigned int data)
BitVector_Bit_On(cpu, CPU_Prot);
if (data >= PROC_386)
BitVector_Bit_On(cpu, CPU_SMM);
if (data >= PROC_nehalem)
if (data >= PROC_nehalem) {
BitVector_Bit_On(cpu, CPU_SSE42);
BitVector_Bit_On(cpu, CPU_XSAVE);
}
if (data >= PROC_penryn)
BitVector_Bit_On(cpu, CPU_SSE41);
if (data >= PROC_conroe)
@ -326,6 +328,8 @@ sse4, x86_cpu_set_sse4, 0
nosse4, x86_cpu_clear_sse4, 0
sse5, x86_cpu_set, CPU_SSE5
nosse5, x86_cpu_clear, CPU_SSE5
xsave, x86_cpu_set, CPU_XSAVE
noxsave, x86_cpu_clear, CPU_XSAVE
%%
void