uefi-ref/yasm
1
0
Fork 0
mirror of https://github.com/yasm/yasm synced 2026-08-26 22:26:05 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fix VGATHER/VPGATHER memory sizes.

Browse source 
These now match the memory fetch sizes in the AVX reference.

Reported by: nasm64developer
This commit is contained in:
Peter Johnson 2011-07-04 11:35:19 -07:00
parent ab721f347d
commit 3b65acb39d
2 changed files with 20 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

24
modules/arch/x86/gen_x86_insn.py
View file

@ -7028,7 +7028,7 @@ for sz in [128, 256]:
add_insn("vpblendd", "vex_66_0F3A_imm8_avx2", modifiers=[0x02])
# Vector register in EA.
add_group("gather_32x_32x",
add_group("gather_64x_64x",
cpu=["AVX2"],
modifiers=["Op2Add"],
vex=128,
@ -7036,9 +7036,9 @@ add_group("gather_32x_32x",
prefix=0x66,
opcode=[0x0F, 0x38, 0x00],
operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
Operand(type="MemXMMIndex", size=32, relaxed=True, dest="EA"),
Operand(type="MemXMMIndex", size=64, relaxed=True, dest="EA"),
Operand(type="SIMDReg", size=128, dest="VEX")])
add_group("gather_32x_32x",
add_group("gather_64x_64x",
cpu=["AVX2"],
modifiers=["Op2Add"],
vex=256,
@ -7046,10 +7046,10 @@ add_group("gather_32x_32x",
prefix=0x66,
opcode=[0x0F, 0x38, 0x00],
operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
Operand(type="MemXMMIndex", size=32, relaxed=True, dest="EA"),
Operand(type="MemXMMIndex", size=64, relaxed=True, dest="EA"),
Operand(type="SIMDReg", size=256, dest="VEX")])
add_insn("vgatherdpd", "gather_32x_32x", modifiers=[0x92])
add_insn("vpgatherdq", "gather_32x_32x", modifiers=[0x90])
add_insn("vgatherdpd", "gather_64x_64x", modifiers=[0x92])
add_insn("vpgatherdq", "gather_64x_64x", modifiers=[0x90])
add_group("gather_64x_64y",
cpu=["AVX2"],
@ -7097,7 +7097,7 @@ add_group("gather_32x_32y",
add_insn("vgatherdps", "gather_32x_32y", modifiers=[0x92])
add_insn("vpgatherdd", "gather_32x_32y", modifiers=[0x90])
add_group("gather_64x_64y_128",
add_group("gather_32x_32y_128",
cpu=["AVX2"],
modifiers=["Op2Add"],
vex=128,
@ -7105,9 +7105,9 @@ add_group("gather_64x_64y_128",
prefix=0x66,
opcode=[0x0F, 0x38, 0x00],
operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
Operand(type="MemXMMIndex", size=64, relaxed=True, dest="EA"),
Operand(type="MemXMMIndex", size=32, relaxed=True, dest="EA"),
Operand(type="SIMDReg", size=128, dest="VEX")])
add_group("gather_64x_64y_128",
add_group("gather_32x_32y_128",
cpu=["AVX2"],
modifiers=["Op2Add"],
vex=256,
@ -7115,10 +7115,10 @@ add_group("gather_64x_64y_128",
prefix=0x66,
opcode=[0x0F, 0x38, 0x00],
operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
Operand(type="MemYMMIndex", size=64, relaxed=True, dest="EA"),
Operand(type="MemYMMIndex", size=32, relaxed=True, dest="EA"),
Operand(type="SIMDReg", size=128, dest="VEX")])
add_insn("vgatherqps", "gather_64x_64y_128", modifiers=[0x93])
add_insn("vpgatherqd", "gather_64x_64y_128", modifiers=[0x91])
add_insn("vgatherqps", "gather_32x_32y_128", modifiers=[0x93])
add_insn("vpgatherqd", "gather_32x_32y_128", modifiers=[0x91])
#####################################################################
# Intel FMA instructions

16
modules/arch/x86/tests/avx2.asm
View file

@ -612,9 +612,9 @@ vpsrlvq ymm1, ymm2, ymm3 ; c4 e2 ed 45 cb
vpsrlvq ymm1, ymm2, yword [rax] ; c4 e2 ed 45 08
vgatherdpd xmm1, [rax+xmm1], xmm2 ; c4 e2 e9 92 0c 08
vgatherdpd xmm1, dword [rax+xmm1], xmm2 ; c4 e2 e9 92 0c 08
vgatherdpd xmm1, qword [rax+xmm1], xmm2 ; c4 e2 e9 92 0c 08
vgatherdpd ymm1, [rax+xmm1], ymm2 ; c4 e2 ed 92 0c 08
vgatherdpd ymm1, dword [rax+xmm1], ymm2 ; c4 e2 ed 92 0c 08
vgatherdpd ymm1, qword [rax+xmm1], ymm2 ; c4 e2 ed 92 0c 08
vgatherqpd xmm1, [rax+xmm1], xmm2 ; c4 e2 e9 93 0c 08
vgatherqpd xmm1, qword [rax+xmm1], xmm2 ; c4 e2 e9 93 0c 08
@ -627,9 +627,9 @@ vgatherdps ymm1, [rax+ymm1], ymm2 ; c4 e2 6d 92 0c 08
vgatherdps ymm1, dword [rax+ymm1], ymm2 ; c4 e2 6d 92 0c 08
vgatherqps xmm1, [rax+xmm1], xmm2 ; c4 e2 69 93 0c 08
vgatherqps xmm1, qword [rax+xmm1], xmm2 ; c4 e2 69 93 0c 08
vgatherqps xmm1, dword [rax+xmm1], xmm2 ; c4 e2 69 93 0c 08
vgatherqps xmm1, [rax+ymm1], xmm2 ; c4 e2 6d 93 0c 08
vgatherqps xmm1, qword [rax+ymm1], xmm2 ; c4 e2 6d 93 0c 08
vgatherqps xmm1, dword [rax+ymm1], xmm2 ; c4 e2 6d 93 0c 08
vpgatherdd xmm1, [rax+xmm1], xmm2 ; c4 e2 69 90 0c 08
vpgatherdd xmm1, dword [rax+xmm1], xmm2 ; c4 e2 69 90 0c 08
@ -637,14 +637,14 @@ vpgatherdd ymm1, [rax+ymm1], ymm2 ; c4 e2 6d 90 0c 08
vpgatherdd ymm1, dword [rax+ymm1], ymm2 ; c4 e2 6d 90 0c 08
vpgatherqd xmm1, [rax+xmm1], xmm2 ; c4 e2 69 91 0c 08
vpgatherqd xmm1, qword [rax+xmm1], xmm2 ; c4 e2 69 91 0c 08
vpgatherqd xmm1, dword [rax+xmm1], xmm2 ; c4 e2 69 91 0c 08
vpgatherqd xmm1, [rax+ymm1], xmm2 ; c4 e2 6d 91 0c 08
vpgatherqd xmm1, qword [rax+ymm1], xmm2 ; c4 e2 6d 91 0c 08
vpgatherqd xmm1, dword [rax+ymm1], xmm2 ; c4 e2 6d 91 0c 08
vpgatherdq xmm1, [rax+xmm1], xmm2 ; c4 e2 e9 90 0c 08
vpgatherdq xmm1, dword [rax+xmm1], xmm2 ; c4 e2 e9 90 0c 08
vpgatherdq xmm1, qword [rax+xmm1], xmm2 ; c4 e2 e9 90 0c 08
vpgatherdq ymm1, [rax+xmm1], ymm2 ; c4 e2 ed 90 0c 08
vpgatherdq ymm1, dword [rax+xmm1], ymm2 ; c4 e2 ed 90 0c 08
vpgatherdq ymm1, qword [rax+xmm1], ymm2 ; c4 e2 ed 90 0c 08
vpgatherqq xmm1, [rax+xmm1], xmm2 ; c4 e2 e9 91 0c 08
vpgatherqq xmm1, qword [rax+xmm1], xmm2 ; c4 e2 e9 91 0c 08