From 3bf0ed3927ba03884fe5c24ffabcae964b1d8e89 Mon Sep 17 00:00:00 2001 From: Peter Johnson Date: Sun, 29 May 2011 13:14:22 -0700 Subject: [PATCH] Fix lar and lsl second operand size. Also support 32-bit second operand for extra compatibility against ISA documentation, although only the low 16 bits are used. Fixes #261. --- modules/arch/x86/gen_x86_insn.py | 20 +++- modules/arch/x86/tests/Makefile.inc | 2 + modules/arch/x86/tests/larlsl.asm | 59 +++++++++ modules/arch/x86/tests/larlsl.hex | 178 ++++++++++++++++++++++++++++ 4 files changed, 257 insertions(+), 2 deletions(-) create mode 100644 modules/arch/x86/tests/larlsl.asm create mode 100644 modules/arch/x86/tests/larlsl.hex diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py index 56af2735..a91e4e1e 100755 --- a/modules/arch/x86/gen_x86_insn.py +++ b/modules/arch/x86/gen_x86_insn.py @@ -3081,8 +3081,24 @@ add_insn("nop", "onebyte", modifiers=[0x90]) # # Protection control # -add_insn("lar", "bsfr", modifiers=[0x02], cpu=["286", "Prot"]) -add_insn("lsl", "bsfr", modifiers=[0x03], cpu=["286", "Prot"]) +for sfx, sz, sz2 in zip("wlq", [16, 32, 64], [16, 32, 32]): + add_group("larlsl", + suffix=sfx, + modifiers=["Op1Add"], + opersize=sz, + opcode=[0x0F, 0x00], + operands=[Operand(type="Reg", size=sz, dest="Spare"), + Operand(type="Reg", size=sz2, dest="EA")]) + add_group("larlsl", + suffix=sfx, + modifiers=["Op1Add"], + opersize=sz, + opcode=[0x0F, 0x00], + operands=[Operand(type="Reg", size=sz, dest="Spare"), + Operand(type="RM", size=16, relaxed=True, dest="EA")]) + +add_insn("lar", "larlsl", modifiers=[0x02], cpu=["286", "Prot"]) +add_insn("lsl", "larlsl", modifiers=[0x03], cpu=["286", "Prot"]) add_group("arpl", suffix="w", diff --git a/modules/arch/x86/tests/Makefile.inc b/modules/arch/x86/tests/Makefile.inc index f46fa074..8058f2d8 100644 --- a/modules/arch/x86/tests/Makefile.inc +++ b/modules/arch/x86/tests/Makefile.inc @@ -95,6 +95,8 @@ EXTRA_DIST += modules/arch/x86/tests/jmp64-6.asm EXTRA_DIST += modules/arch/x86/tests/jmp64-6.hex EXTRA_DIST += modules/arch/x86/tests/jmpfar.asm EXTRA_DIST += modules/arch/x86/tests/jmpfar.hex +EXTRA_DIST += modules/arch/x86/tests/larlsl.asm +EXTRA_DIST += modules/arch/x86/tests/larlsl.hex EXTRA_DIST += modules/arch/x86/tests/lds.asm EXTRA_DIST += modules/arch/x86/tests/lds.hex EXTRA_DIST += modules/arch/x86/tests/loopadsz.asm diff --git a/modules/arch/x86/tests/larlsl.asm b/modules/arch/x86/tests/larlsl.asm new file mode 100644 index 00000000..51c3feca --- /dev/null +++ b/modules/arch/x86/tests/larlsl.asm @@ -0,0 +1,59 @@ +[bits 16] +lar ax, bx +lar ax, [bx] +lar ax, word [bx] +lar eax, bx +lar eax, ebx +lar eax, [bx] +lar eax, word [bx] + +lsl ax, bx +lsl ax, [bx] +lsl ax, word [bx] +lsl eax, bx +lsl eax, ebx +lsl eax, [bx] +lsl eax, word [bx] + +[bits 32] +lar ax, bx +lar ax, [ebx] +lar ax, word [ebx] +lar eax, bx +lar eax, ebx +lar eax, [ebx] +lar eax, word [ebx] + +lsl ax, bx +lsl ax, [ebx] +lsl ax, word [ebx] +lsl eax, bx +lsl eax, ebx +lsl eax, [ebx] +lsl eax, word [ebx] + +[bits 64] +lar ax, bx +lar ax, [rbx] +lar ax, word [rbx] +lar eax, bx +lar eax, ebx +lar eax, [rbx] +lar eax, word [rbx] +lar rax, bx +lar rax, ebx +lar rax, [rbx] +lar rax, word [rbx] + +lsl ax, bx +lsl ax, [rbx] +lsl ax, word [rbx] +lsl eax, bx +lsl eax, ebx +lsl eax, [rbx] +lsl eax, word [rbx] +lsl rax, bx +lsl rax, ebx +lsl rax, [rbx] +lsl rax, word [rbx] + diff --git a/modules/arch/x86/tests/larlsl.hex b/modules/arch/x86/tests/larlsl.hex new file mode 100644 index 00000000..38c8b973 --- /dev/null +++ b/modules/arch/x86/tests/larlsl.hex @@ -0,0 +1,178 @@ +0f +02 +c3 +0f +02 +07 +0f +02 +07 +66 +0f +02 +c3 +66 +0f +02 +c3 +66 +0f +02 +07 +66 +0f +02 +07 +0f +03 +c3 +0f +03 +07 +0f +03 +07 +66 +0f +03 +c3 +66 +0f +03 +c3 +66 +0f +03 +07 +66 +0f +03 +07 +66 +0f +02 +c3 +66 +0f +02 +03 +66 +0f +02 +03 +0f +02 +c3 +0f +02 +c3 +0f +02 +03 +0f +02 +03 +66 +0f +03 +c3 +66 +0f +03 +03 +66 +0f +03 +03 +0f +03 +c3 +0f +03 +c3 +0f +03 +03 +0f +03 +03 +66 +0f +02 +c3 +66 +0f +02 +03 +66 +0f +02 +03 +0f +02 +c3 +0f +02 +c3 +0f +02 +03 +0f +02 +03 +48 +0f +02 +c3 +48 +0f +02 +c3 +48 +0f +02 +03 +48 +0f +02 +03 +66 +0f +03 +c3 +66 +0f +03 +03 +66 +0f +03 +03 +0f +03 +c3 +0f +03 +c3 +0f +03 +03 +0f +03 +03 +48 +0f +03 +c3 +48 +0f +03 +c3 +48 +0f +03 +03 +48 +0f +03 +03