mirror of
https://github.com/markqvist/OpenModem
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146 lines
6 KiB
C
146 lines
6 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2010,2011 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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* \brief SAM3 interrupt definitions.
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*/
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#ifndef SAM3_INTS_H
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#define SAM3_INTS_H
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/**
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* Defines for the fault assignments.
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*/
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/*\{*/
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#define FAULT_NMI 2 ///< NMI fault
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#define FAULT_HARD 3 ///< Hard fault
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#define FAULT_MPU 4 ///< MPU fault
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#define FAULT_BUS 5 ///< Bus fault
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#define FAULT_USAGE 6 ///< Usage fault
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#define FAULT_SVCALL 11 ///< SVCall
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#define FAULT_DEBUG 12 ///< Debug monitor
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#define FAULT_PENDSV 14 ///< PendSV
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#define FAULT_SYSTICK 15 ///< System Tick
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/*\}*/
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/**
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* Defines for the interrupt assignments.
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*/
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/*\{*/
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#define INT_PERIPH_BASE 16
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#if CPU_CM3_SAM3N
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#define INT_SUPC (INT_PERIPH_BASE + SUPC_ID)
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#define INT_RSTC (INT_PERIPH_BASE + RSTC_ID)
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#define INT_RTC (INT_PERIPH_BASE + RTC_ID)
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#define INT_RTT (INT_PERIPH_BASE + RTT_ID)
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#define INT_WDT (INT_PERIPH_BASE + WDT_ID)
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#define INT_PMC (INT_PERIPH_BASE + PMC_ID)
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#define INT_EFC (INT_PERIPH_BASE + EFC_ID)
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#define INT_UART0 (INT_PERIPH_BASE + UART0_ID)
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#define INT_UART1 (INT_PERIPH_BASE + UART1_ID)
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#define INT_PIOA (INT_PERIPH_BASE + PIOA_ID)
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#define INT_PIOB (INT_PERIPH_BASE + PIOB_ID)
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#define INT_PIOC (INT_PERIPH_BASE + PIOC_ID)
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#define INT_US0 (INT_PERIPH_BASE + US0_ID)
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#define INT_US1 (INT_PERIPH_BASE + US1_ID)
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#define INT_TWI0 (INT_PERIPH_BASE + TWI0_ID)
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#define INT_TWI1 (INT_PERIPH_BASE + TWI1_ID)
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#define INT_SPI0 (INT_PERIPH_BASE + SPI0_ID)
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#define INT_TC0 (INT_PERIPH_BASE + TC0_ID)
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#define INT_TC1 (INT_PERIPH_BASE + TC1_ID)
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#define INT_TC2 (INT_PERIPH_BASE + TC2_ID)
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#define INT_TC3 (INT_PERIPH_BASE + TC3_ID)
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#define INT_TC4 (INT_PERIPH_BASE + TC4_ID)
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#define INT_TC5 (INT_PERIPH_BASE + TC5_ID)
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#define INT_ADC (INT_PERIPH_BASE + ADC_ID)
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#define INT_DACC (INT_PERIPH_BASE + DACC_ID)
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#define INT_PWM (INT_PERIPH_BASE + PWM_ID)
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// Total number of interrupts.
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#define NUM_INTERRUPTS 48
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#elif CPU_CM3_SAM3X
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#define INT_SUPC (INT_PERIPH_BASE + SUPC_ID)
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#define INT_RSTC (INT_PERIPH_BASE + RSTC_ID)
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#define INT_RTC (INT_PERIPH_BASE + RTC_ID)
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#define INT_RTT (INT_PERIPH_BASE + RTT_ID)
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#define INT_WDT (INT_PERIPH_BASE + WDT_ID)
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#define INT_PMC (INT_PERIPH_BASE + PMC_ID)
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#define INT_EEFC0 (INT_PERIPH_BASE + EEFC0_ID)
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#define INT_EEFC1 (INT_PERIPH_BASE + EEFC1_ID)
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#define INT_UART0 (INT_PERIPH_BASE + UART0_ID)
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#define INT_SMC_SDRAMC (INT_PERIPH_BASE + SMC_SDRAMC_ID)
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#define INT_SDRAMC (INT_PERIPH_BASE + SDRAMC_ID)
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#define INT_PIOA (INT_PERIPH_BASE + PIOA_ID)
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#define INT_PIOB (INT_PERIPH_BASE + PIOB_ID)
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#define INT_PIOC (INT_PERIPH_BASE + PIOC_ID)
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#define INT_PIOD (INT_PERIPH_BASE + PIOD_ID)
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#define INT_PIOE (INT_PERIPH_BASE + PIOE_ID)
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#define INT_PIOF (INT_PERIPH_BASE + PIOF_ID)
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#define INT_US0 (INT_PERIPH_BASE + US0_ID)
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#define INT_US1 (INT_PERIPH_BASE + US1_ID)
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#define INT_US2 (INT_PERIPH_BASE + US2_ID)
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#define INT_US3 (INT_PERIPH_BASE + US3_ID)
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#define INT_HSMCI (INT_PERIPH_BASE + HSMCI_ID)
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#define INT_TWI0 (INT_PERIPH_BASE + TWI0_ID)
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#define INT_TWI1 (INT_PERIPH_BASE + TWI1_ID)
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#define INT_SPI0 (INT_PERIPH_BASE + SPI0_ID)
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#define INT_SPI1 (INT_PERIPH_BASE + SPI1_ID)
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#define INT_SSC (INT_PERIPH_BASE + SSC_ID)
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#define INT_TC0 (INT_PERIPH_BASE + TC0_ID)
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#define INT_TC1 (INT_PERIPH_BASE + TC1_ID)
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#define INT_TC2 (INT_PERIPH_BASE + TC2_ID)
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#define INT_TC3 (INT_PERIPH_BASE + TC3_ID)
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#define INT_TC4 (INT_PERIPH_BASE + TC4_ID)
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#define INT_TC5 (INT_PERIPH_BASE + TC5_ID)
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#define INT_TC6 (INT_PERIPH_BASE + TC6_ID)
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#define INT_TC7 (INT_PERIPH_BASE + TC7_ID)
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#define INT_TC8 (INT_PERIPH_BASE + TC8_ID)
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#define INT_PWM (INT_PERIPH_BASE + PWM_ID)
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#define INT_ADC (INT_PERIPH_BASE + ADC_ID)
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#define INT_DACC (INT_PERIPH_BASE + DACC_ID)
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#define INT_DMAC (INT_PERIPH_BASE + DMAC_ID)
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#define INT_UOTGHS (INT_PERIPH_BASE + UOTGHS_ID)
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#define INT_TRNG (INT_PERIPH_BASE + TRNG_ID)
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#define INT_EMAC (INT_PERIPH_BASE + EMAC_ID)
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#define INT_CAN0 (INT_PERIPH_BASE + CAN0_ID)
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#define INT_CAN1 (INT_PERIPH_BASE + CAN1_ID)
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// Total number of interrupts.
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#define NUM_INTERRUPTS 61
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#else
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#error Peripheral IDs undefined
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#endif
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/*\}*/
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#endif /* SAM3_INTS_H */
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