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Add M68K ColdFire ISA support (#2927)

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* regenerate arch/M68K/M68KInstructionTable.inc

* Add M68K ColdFire ISA support

* Apply suggestions from code review

Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>

* Clarify M68K EA validation and detail checks

* Normalize M68K memory operand details

* Update docs/cs_v6_release_guide.md

---------

Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
This commit is contained in:
billow 2026-05-22 23:04:35 +08:00 • committed by GitHub
parent a020137171
commit 4eeceba201
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GPG key ID: B5690EEEBB952194
20 changed files with 16417 additions and 11424 deletions
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1174
arch/M68K/M68KDisassembler.c
View file

File diff suppressed because it is too large Load diff

103
arch/M68K/M68KDisassembler.h
View file

@ -44,31 +44,28 @@
#define BIT_1E(A) ((A) & 0x40000000)
#define BIT_1F(A) ((A) & 0x80000000)
/* These are the CPU types understood by this disassembler */
#define TYPE_68000 1
#define TYPE_68010 2
#define TYPE_68020 4
#define TYPE_68030 8
#define TYPE_68040 16
#define TYPE_68060 32
#define TYPE_CPU32 64
/* These are the M68K feature masks understood by this disassembler. */
#define M68000_ONLY CS_MODE_M68K_000
#define M68000_ONLY TYPE_68000
#define M68010_ONLY TYPE_68010
#define M68010_LESS (TYPE_68000 | TYPE_68010)
#define M68010_ONLY CS_MODE_M68K_010
#define M68010_LESS (CS_MODE_M68K_000 | CS_MODE_M68K_010)
#define M68010_PLUS \
(TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68060)
(CS_MODE_M68K_010 | CS_MODE_M68K_020 | CS_MODE_M68K_030 | \
CS_MODE_M68K_040 | CS_MODE_M68K_060)
#define M68020_ONLY TYPE_68020
#define M68020_LESS (TYPE_68010 | TYPE_68020)
#define M68020_PLUS (TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68060)
#define M68020_ONLY CS_MODE_M68K_020
#define M68020_LESS (CS_MODE_M68K_010 | CS_MODE_M68K_020)
#define M68020_PLUS \
(CS_MODE_M68K_020 | CS_MODE_M68K_030 | CS_MODE_M68K_040 | \
CS_MODE_M68K_060)
#define M68030_ONLY TYPE_68030
#define M68030_LESS (TYPE_68010 | TYPE_68020 | TYPE_68030)
#define M68030_PLUS (TYPE_68030 | TYPE_68040 | TYPE_68060)
#define M68030_ONLY CS_MODE_M68K_030
#define M68030_LESS (CS_MODE_M68K_010 | CS_MODE_M68K_020 | CS_MODE_M68K_030)
#define M68030_PLUS (CS_MODE_M68K_030 | CS_MODE_M68K_040 | CS_MODE_M68K_060)
#define M68040_PLUS (TYPE_68040 | TYPE_68060)
#define M68040_PLUS (CS_MODE_M68K_040 | CS_MODE_M68K_060)
typedef uint32_t m68k_feature_mask;
/* Extension word formats */
#define EXT_8BIT_DISPLACEMENT(A) ((A) & 0xff)
@ -123,6 +120,10 @@
/* 6-bit coprocessor condition (bits 5:0 of IR). */
#define M68K_IR_CONDITION(info) ((info)->ir & 0x3f)
/* 4-bit condition selector used by Bcc/DBcc/Scc/TRAPcc. */
#define M68K_IR_CONDITION_NIBBLE(info) (((info)->ir >> 8) & 0xf)
#define M68K_CONDITION_FALSE 1
/* cinv/cpush: select cpush(1) vs cinv(0) -- bit 5 of IR. */
#define M68K_IR_IS_CPUSH(info) (((info)->ir >> 5) & 1)
@ -187,36 +188,36 @@
#define M68K_FPOP_FSSQRT_RAW 0x01 /* 0x41 & 0x3f */
#define M68K_FPOP_FDSQRT_RAW 0x05 /* 0x45 & 0x3f */
/* ── CPU-type guard macros ───────────────────────────────────────────
/* ── Feature guard macros ────────────────────────────────────────────
* These reference the `info` parameter available at each call site.
* They early-return from the calling function on type mismatch. */
* They early-return from the calling function on guard mismatch. */
#define LIMIT_CPU_TYPES(info, ALLOWED_CPU_TYPES) \
#define LIMIT_FEATURE(info, FEATURES) \
do { \
if (!(info->type & ALLOWED_CPU_TYPES)) { \
if (!m68k_has_feature(info, FEATURES)) { \
d68000_invalid(info); \
return; \
} \
} while (0)
/* Like LIMIT_CPU_TYPES but also reverses the instruction word consumption,
/* Like LIMIT_FEATURE but also reverses the instruction word consumption,
* so the invalid instruction produces size=0 (not decoded) instead of size=2.
* Use for handlers that replace d68000_invalid in the dispatch table. */
#define LIMIT_CPU_TYPES_UNDECODED(info, ALLOWED_CPU_TYPES) \
#define LIMIT_FEATURE_UNDECODED(info, FEATURES) \
do { \
if (!(info->type & ALLOWED_CPU_TYPES)) { \
if (!m68k_has_feature(info, FEATURES)) { \
info->pc -= 2; \
d68000_invalid(info); \
return; \
} \
} while (0)
/* Like LIMIT_CPU_TYPES but also rejects CPU32. CPU32 shares TYPE_68020 but
* lacks some 68020 instructions (CAS, CAS2, CHK.L, PACK, UNPK). */
#define LIMIT_CPU_TYPES_NOT_CPU32(info, ALLOWED_CPU_TYPES) \
/* Like LIMIT_FEATURE but also rejects a feature subset. CPU32 implies 68020
* but lacks some 68020 instructions (CAS, CAS2, CHK.L, PACK, UNPK). */
#define LIMIT_FEATURE_EXCLUDING(info, FEATURES, EXCLUDED_FEATURES) \
do { \
if (!(info->type & (ALLOWED_CPU_TYPES)) || \
(info->type & TYPE_CPU32)) { \
if (!m68k_has_feature(info, FEATURES) || \
m68k_has_feature(info, EXCLUDED_FEATURES)) { \
d68000_invalid(info); \
return; \
} \
@ -232,21 +233,6 @@
} \
} while (0)
/* Require CpID == MMU or CpID == FPU.
* CpID MMU is rejected on CPU32 (no PMMU). Used by cpSAVE/cpRESTORE. */
#define REQUIRE_CPID_FPU_OR_PMMU(info) \
do { \
int _cpid = M68K_CPID(info); \
if (_cpid == M68K_CPID_MMU && ((info)->type & TYPE_CPU32)) { \
d68000_invalid(info); \
return; \
} \
if (_cpid != M68K_CPID_MMU && _cpid != M68K_CPID_FPU) { \
d68000_invalid(info); \
return; \
} \
} while (0)
/* ── EA / immediate convenience aliases ─────────────────────────────
* Shorthand wrappers around the sized get_ea_mode_str / get_imm_str
* functions. These expand at the call site where 'info' is in scope. */
@ -281,7 +267,7 @@ typedef struct m68k_info {
MCInst *inst;
unsigned int pc; /* program counter */
unsigned int ir; /* instruction register */
unsigned int type;
m68k_feature_mask features;
unsigned int address_mask; /* Address mask to simulate address lines */
cs_m68k extension;
uint16_t regs_read
@ -294,6 +280,27 @@ typedef struct m68k_info {
uint8_t groups_count;
} m68k_info;
static inline bool m68k_has_feature(const m68k_info *info,
m68k_feature_mask features)
{
m68k_feature_mask available = info->features;
if (available & CS_MODE_M68K_CPU32)
available |= CS_MODE_M68K_020;
if (available & CS_MODE_M68K_CF_ISA_A_PLUS)
available |= CS_MODE_M68K_CF_ISA_A;
if (available & CS_MODE_M68K_CF_ISA_B)
available |= CS_MODE_M68K_CF_ISA_A | CS_MODE_M68K_CF_ISA_A_PLUS;
if (available & CS_MODE_M68K_CF_ISA_C)
available |= CS_MODE_M68K_CF_ISA_A;
if (available & CS_MODE_M68K_CF_EMAC)
available |= CS_MODE_M68K_CF_MAC;
if (available & CS_MODE_M68K_CF_EMAC_B)
available |= CS_MODE_M68K_CF_EMAC | CS_MODE_M68K_CF_MAC;
return (available & features) != 0;
}
bool M68K_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);

201
arch/M68K/M68KInstPrinter.c
View file

@ -21,83 +21,101 @@
static const char s_spacing[] = " ";
static const char *const s_reg_names[] = {
"invalid", "d0", "d1", "d2", "d3", "d4", "d5", "d6",
"d7", "a0", "a1", "a2", "a3", "a4", "a5", "a6",
"a7", "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6",
"fp7", "pc", "sr", "ccr", "sfc", "dfc", "usp", "vbr",
"cacr", "caar", "msp", "isp", "tc", "itt0", "itt1", "dtt0",
"dtt1", "mmusr", "urp", "srp",
"invalid", "d0", "d1", "d2", "d3", "d4", "d5", "d6",
"d7", "a0", "a1", "a2", "a3", "a4", "a5", "a6",
"a7", "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6",
"fp7", "pc", "sr", "ccr", "sfc", "dfc", "usp", "vbr",
"cacr", "caar", "msp", "isp", "tc", "itt0", "itt1", "dtt0",
"dtt1", "mmusr", "urp", "srp",
"fpcr", "fpsr", "fpiar",
"fpcr", "fpsr", "fpiar",
"tt0", "tt1", "crp",
"tt0", "tt1", "crp", "acc", "acc0", "acc1", "acc2", "acc3",
"accext01", "accext23", "macsr", "mask",
};
static const char *const s_instruction_names[] = {
"invalid", "abcd", "add", "adda", "addi", "addq",
"addx", "and", "andi", "asl", "asr", "bhs",
"blo", "bhi", "bls", "bcc", "bcs", "bne",
"beq", "bvc", "bvs", "bpl", "bmi", "bge",
"blt", "bgt", "ble", "bra", "bsr", "bchg",
"bclr", "bset", "btst", "bfchg", "bfclr", "bfexts",
"bfextu", "bfffo", "bfins", "bfset", "bftst", "bkpt",
"callm", "cas", "cas2", "chk", "chk2", "clr",
"cmp", "cmpa", "cmpi", "cmpm", "cmp2", "cinvl",
"cinvp", "cinva", "cpushl", "cpushp", "cpusha", "dbt",
"dbf", "dbhi", "dbls", "dbcc", "dbcs", "dbne",
"dbeq", "dbvc", "dbvs", "dbpl", "dbmi", "dbge",
"dblt", "dbgt", "dble", "dbra", "divs", "divsl",
"divu", "divul", "eor", "eori", "exg", "ext",
"extb", "fabs", "fsabs", "fdabs", "facos", "fadd",
"fsadd", "fdadd", "fasin", "fatan", "fatanh", "fbf",
"fbeq", "fbogt", "fboge", "fbolt", "fbole", "fbogl",
"fbor", "fbun", "fbueq", "fbugt", "fbuge", "fbult",
"fbule", "fbne", "fbt", "fbsf", "fbseq", "fbgt",
"fbge", "fblt", "fble", "fbgl", "fbgle", "fbngle",
"fbngl", "fbnle", "fbnlt", "fbnge", "fbngt", "fbsne",
"fbst", "fcmp", "fcos", "fcosh", "fdbf", "fdbeq",
"fdbogt", "fdboge", "fdbolt", "fdbole", "fdbogl", "fdbor",
"fdbun", "fdbueq", "fdbugt", "fdbuge", "fdbult", "fdbule",
"fdbne", "fdbt", "fdbsf", "fdbseq", "fdbgt", "fdbge",
"fdblt", "fdble", "fdbgl", "fdbgle", "fdbngle", "fdbngl",
"fdbnle", "fdbnlt", "fdbnge", "fdbngt", "fdbsne", "fdbst",
"fdiv", "fsdiv", "fddiv", "fetox", "fetoxm1", "fgetexp",
"fgetman", "fint", "fintrz", "flog10", "flog2", "flogn",
"flognp1", "fmod", "fmove", "fsmove", "fdmove", "fmovecr",
"fmovem", "fmul", "fsmul", "fdmul", "fneg", "fsneg",
"fdneg", "fnop", "frem", "frestore", "fsave", "fscale",
"fsgldiv", "fsglmul", "fsin", "fsincos", "fsinh", "fsqrt",
"fssqrt", "fdsqrt", "fsf", "fseq", "fsogt", "fsoge",
"fsolt", "fsole", "fsogl", "fsor", "fsun", "fsueq",
"fsugt", "fsuge", "fsult", "fsule", "fsne", "fst",
"fssf", "fsseq", "fsgt", "fsge", "fslt", "fsle",
"fsgl", "fsgle", "fsngle", "fsngl", "fsnle", "fsnlt",
"fsnge", "fsngt", "fssne", "fsst", "fsub", "fssub",
"fdsub", "ftan", "ftanh", "ftentox", "ftrapf", "ftrapeq",
"ftrapogt", "ftrapoge", "ftrapolt", "ftrapole", "ftrapogl", "ftrapor",
"ftrapun", "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule",
"ftrapne", "ftrapt", "ftrapsf", "ftrapseq", "ftrapgt", "ftrapge",
"ftraplt", "ftraple", "ftrapgl", "ftrapgle", "ftrapngle", "ftrapngl",
"ftrapnle", "ftrapnlt", "ftrapnge", "ftrapngt", "ftrapsne", "ftrapst",
"ftst", "ftwotox", "halt", "illegal", "jmp", "jsr",
"lea", "link", "lpstop", "lsl", "lsr", "move",
"movea", "movec", "movem", "movep", "moveq", "moves",
"move16", "muls", "mulu", "nbcd", "neg", "negx",
"nop", "not", "or", "ori", "pack", "pea",
"pflush", "pflusha", "pflushan", "pflushn", "ploadr", "ploadw",
"plpar", "plpaw", "pmove", "pmovefd", "ptestr", "ptestw",
"pulse", "rems", "remu", "reset", "rol", "ror",
"roxl", "roxr", "rtd", "rte", "rtm", "rtr",
"rts", "sbcd", "st", "sf", "shi", "sls",
"scc", "shs", "scs", "slo", "sne", "seq",
"svc", "svs", "spl", "smi", "sge", "slt",
"sgt", "sle", "stop", "sub", "suba", "subi",
"subq", "subx", "swap", "tas", "trap", "trapv",
"trapt", "trapf", "traphi", "trapls", "trapcc", "traphs",
"trapcs", "traplo", "trapne", "trapeq", "trapvc", "trapvs",
"trappl", "trapmi", "trapge", "traplt", "trapgt", "traple",
"tst", "unlk", "unpk", "bgnd", "tbls", "tblu",
"tblsn", "tblun",
"invalid", "abcd", "add", "adda", "addi",
"addq", "addx", "and", "andi", "asl",
"asr", "bhs", "blo", "bhi", "bls",
"bcc", "bcs", "bne", "beq", "bvc",
"bvs", "bpl", "bmi", "bge", "blt",
"bgt", "ble", "bra", "bsr", "bchg",
"bclr", "bset", "btst", "bitrev", "byterev",
"bfchg", "bfclr", "bfexts", "bfextu", "bfffo",
"bfins", "bfset", "bftst", "bkpt", "callm",
"cas", "cas2", "chk", "chk2", "clr",
"cmp", "cmpa", "cmpi", "cmpm", "cmp2",
"cinvl", "cinvp", "cinva", "cpushl", "cpushp",
"cpusha", "dbt", "dbf", "dbhi", "dbls",
"dbcc", "dbcs", "dbne", "dbeq", "dbvc",
"dbvs", "dbpl", "dbmi", "dbge", "dblt",
"dbgt", "dble", "dbra", "divs", "divsl",
"divu", "divul", "eor", "eori", "exg",
"ext", "extb", "ff1", "fabs", "fsabs",
"fdabs", "facos", "fadd", "fsadd", "fdadd",
"fasin", "fatan", "fatanh", "fbf", "fbeq",
"fbogt", "fboge", "fbolt", "fbole", "fbogl",
"fbor", "fbun", "fbueq", "fbugt", "fbuge",
"fbult", "fbule", "fbne", "fbt", "fbsf",
"fbseq", "fbgt", "fbge", "fblt", "fble",
"fbgl", "fbgle", "fbngle", "fbngl", "fbnle",
"fbnlt", "fbnge", "fbngt", "fbsne", "fbst",
"fcmp", "fcos", "fcosh", "fdbf", "fdbeq",
"fdbogt", "fdboge", "fdbolt", "fdbole", "fdbogl",
"fdbor", "fdbun", "fdbueq", "fdbugt", "fdbuge",
"fdbult", "fdbule", "fdbne", "fdbt", "fdbsf",
"fdbseq", "fdbgt", "fdbge", "fdblt", "fdble",
"fdbgl", "fdbgle", "fdbngle", "fdbngl", "fdbnle",
"fdbnlt", "fdbnge", "fdbngt", "fdbsne", "fdbst",
"fdiv", "fsdiv", "fddiv", "fetox", "fetoxm1",
"fgetexp", "fgetman", "fint", "fintrz", "flog10",
"flog2", "flogn", "flognp1", "fmod", "fmove",
"fsmove", "fdmove", "fmovecr", "fmovem", "fmul",
"fsmul", "fdmul", "fneg", "fsneg", "fdneg",
"fnop", "frem", "frestore", "fsave", "fscale",
"fsgldiv", "fsglmul", "fsin", "fsincos", "fsinh",
"fsqrt", "fssqrt", "fdsqrt", "fsf", "fseq",
"fsogt", "fsoge", "fsolt", "fsole", "fsogl",
"fsor", "fsun", "fsueq", "fsugt", "fsuge",
"fsult", "fsule", "fsne", "fst", "fssf",
"fsseq", "fsgt", "fsge", "fslt", "fsle",
"fsgl", "fsgle", "fsngle", "fsngl", "fsnle",
"fsnlt", "fsnge", "fsngt", "fssne", "fsst",
"fsub", "fssub", "fdsub", "ftan", "ftanh",
"ftentox", "ftrapf", "ftrapeq", "ftrapogt", "ftrapoge",
"ftrapolt", "ftrapole", "ftrapogl", "ftrapor", "ftrapun",
"ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule",
"ftrapne", "ftrapt", "ftrapsf", "ftrapseq", "ftrapgt",
"ftrapge", "ftraplt", "ftraple", "ftrapgl", "ftrapgle",
"ftrapngle", "ftrapngl", "ftrapnle", "ftrapnlt", "ftrapnge",
"ftrapngt", "ftrapsne", "ftrapst", "ftst", "ftwotox",
"halt", "illegal", "intouch", "jmp", "jsr",
"lea", "link", "lpstop", "lsl", "lsr",
"mac", "move", "movea", "movec", "movem",
"movep", "moveq", "moves", "move16", "mov3q",
"movclr", "msac", "muls", "mulu", "mvs",
"mvz", "nbcd", "neg", "negx", "nop",
"not", "or", "ori", "pack", "pea",
"pflush", "pflusha", "pflushan", "pflushn", "ploadr",
"ploadw", "plpar", "plpaw", "pmove", "pmovefd",
"ptestr", "ptestw", "pulse", "rems", "remu",
"reset", "rol", "ror", "roxl", "roxr",
"rtd", "rte", "rtm", "rtr", "rts",
"sats", "sbcd", "st", "sf", "shi",
"sls", "scc", "shs", "scs", "slo",
"sne", "seq", "svc", "svs", "spl",
"smi", "sge", "slt", "sgt", "sle",
"stop", "strldsr", "sub", "suba", "subi",
"subq", "subx", "swap", "tas", "trap",
"trapv", "trapt", "trapf", "traphi", "trapls",
"trapcc", "traphs", "trapcs", "traplo", "trapne",
"trapeq", "trapvc", "trapvs", "trappl", "trapmi",
"trapge", "traplt", "trapgt", "traple", "tst",
"unlk", "unpk", "wddata", "wdebug", "bgnd",
"tbls", "tblu", "tblsn", "tblun", "cp0bcbusy",
"cp0ld", "cp0nop", "cp0st", "cp1bcbusy", "cp1ld",
"cp1nop", "cp1st", "tpf",
};
#endif
@ -154,6 +172,15 @@ static void registerPair(SStream *O, const cs_m68k_op *op)
s_reg_names[op->reg_pair.reg_1]);
}
static void printRegisterName(SStream *O, const cs_m68k_op *op)
{
SStream_concat(O, "%s", getRegName(op->reg));
if (op->flags & M68K_OP_FLAG_REG_LOWER)
SStream_concat0(O, "l");
else if (op->flags & M68K_OP_FLAG_REG_UPPER)
SStream_concat0(O, "u");
}
static void printScaleFactor(SStream *O, uint8_t scale, int threshold)
{
if (scale > threshold)
@ -221,26 +248,29 @@ static void printIndex8BitDisp(SStream *O, unsigned int pc,
static void printRegAddrMode(SStream *O, unsigned int pc, const cs_m68k_op *op)
{
m68k_reg base_reg = op->type == M68K_OP_MEM ? op->mem.base_reg :
op->reg;
switch (op->address_mode) {
case M68K_AM_REG_DIRECT_DATA:
SStream_concat(O, "d%" PRId32, (op->reg - M68K_REG_D0));
printRegisterName(O, op);
break;
case M68K_AM_REG_DIRECT_ADDR:
SStream_concat(O, "a%" PRId32, (op->reg - M68K_REG_A0));
printRegisterName(O, op);
break;
case M68K_AM_REGI_ADDR:
SStream_concat(O, "(a%" PRId32 ")", (op->reg - M68K_REG_A0));
SStream_concat(O, "(a%" PRId32 ")", (base_reg - M68K_REG_A0));
break;
case M68K_AM_REGI_ADDR_POST_INC:
SStream_concat(O, "(a%" PRId32 ")+", (op->reg - M68K_REG_A0));
SStream_concat(O, "(a%" PRId32 ")+", (base_reg - M68K_REG_A0));
break;
case M68K_AM_REGI_ADDR_PRE_DEC:
SStream_concat(O, "-(a%" PRId32 ")", (op->reg - M68K_REG_A0));
SStream_concat(O, "-(a%" PRId32 ")", (base_reg - M68K_REG_A0));
break;
case M68K_AM_REGI_ADDR_DISP:
SStream_concat(O, "%s$%" PRIx16 "(a%" PRId32 ")",
op->mem.disp < 0 ? "-" : "", abs(op->mem.disp),
(op->mem.base_reg - M68K_REG_A0));
(base_reg - M68K_REG_A0));
break;
case M68K_AM_PCI_DISP:
SStream_concat(O, "$%" PRIx32 "(pc)", pc + 2 + op->mem.disp);
@ -344,7 +374,13 @@ static void printAddressingMode(SStream *O, unsigned int pc,
registerPair(O, op);
break;
case M68K_OP_REG:
SStream_concat(O, "%s", s_reg_names[op->reg]);
printRegisterName(O, op);
break;
case M68K_OP_SHIFT:
if (op->flags & M68K_OP_FLAG_SHIFT_LEFT)
SStream_concat0(O, "<<");
else if (op->flags & M68K_OP_FLAG_SHIFT_RIGHT)
SStream_concat0(O, ">>");
break;
default:
break;
@ -361,10 +397,10 @@ static void printAddressingMode(SStream *O, unsigned int pc,
printRegAddrMode(O, pc, op);
break;
case M68K_AM_ABSOLUTE_DATA_SHORT:
SStream_concat(O, "$%" PRIx32 ".w", (uint32_t)op->imm);
SStream_concat(O, "$%" PRIx32 ".w", (uint32_t)op->mem.address);
break;
case M68K_AM_ABSOLUTE_DATA_LONG:
SStream_concat(O, "$%" PRIx64 ".l", (uint64_t)op->imm);
SStream_concat(O, "$%" PRIx64 ".l", (uint64_t)op->mem.address);
break;
case M68K_AM_IMMEDIATE:
printImmediate(O, inst, op);
@ -390,6 +426,8 @@ static void printAddressingMode(SStream *O, unsigned int pc,
}
printBitfield(O, op);
if (op->flags & M68K_OP_FLAG_MEM_UPDATE)
SStream_concat0(O, "&");
}
static void printCAS2(SStream *O, unsigned int pc, const cs_m68k *ext)
@ -420,6 +458,7 @@ static void printCacheOp(SStream *O, unsigned int pc, const cs_m68k *ext)
printAddressingMode(O, pc, ext, &ext->operands[i]);
}
}
#endif
static void printOpSize(SStream *O, const cs_m68k *ext)

15996
arch/M68K/M68KInstructionTable.inc
View file

File diff suppressed because it is too large Load diff

75
bindings/python/capstone/__init__.py
View file

@ -88,6 +88,24 @@ __all__ = [
"CS_MODE_M68K_040",
"CS_MODE_M68K_060",
"CS_MODE_M68K_CPU32",
"CS_MODE_M68K_CF_ISA_A",
"CS_MODE_M68K_CF_ISA_A_PLUS",
"CS_MODE_M68K_CF_ISA_B",
"CS_MODE_M68K_CF_ISA_C",
"CS_MODE_M68K_CF_USP",
"CS_MODE_M68K_CF_DIV",
"CS_MODE_M68K_CF_MAC",
"CS_MODE_M68K_CF_EMAC",
"CS_MODE_M68K_CF_EMAC_B",
"CS_MODE_M68K_CF_FPU",
"CS_MODE_M68K_COLDFIRE",
"CS_MODE_M68K_CFV1",
"CS_MODE_M68K_CFV2",
"CS_MODE_M68K_CFV3",
"CS_MODE_M68K_CFV4",
"CS_MODE_M68K_CFV4E",
"CS_MODE_M68K_CFV5",
"CS_MODE_M68K_FEATURE_MASK",
"CS_MODE_M680X_6301",
"CS_MODE_M680X_6309",
"CS_MODE_M680X_6800",
@ -358,6 +376,56 @@ CS_MODE_M68K_030 = 1 << 4 # M68K 68030 mode
CS_MODE_M68K_040 = 1 << 5 # M68K 68040 mode
CS_MODE_M68K_060 = 1 << 6 # M68K 68060 mode
CS_MODE_M68K_CPU32 = 1 << 7
CS_MODE_M68K_CF_ISA_A = 1 << 8
CS_MODE_M68K_CF_ISA_A_PLUS = 1 << 9
CS_MODE_M68K_CF_ISA_B = 1 << 10
CS_MODE_M68K_CF_ISA_C = 1 << 11
CS_MODE_M68K_CF_USP = 1 << 12
CS_MODE_M68K_CF_DIV = 1 << 13
CS_MODE_M68K_CF_MAC = 1 << 14
CS_MODE_M68K_CF_EMAC = 1 << 15
CS_MODE_M68K_CF_EMAC_B = 1 << 16
CS_MODE_M68K_CF_FPU = 1 << 17
CS_MODE_M68K_COLDFIRE = (
CS_MODE_M68K_CF_ISA_A
| CS_MODE_M68K_CF_ISA_A_PLUS
| CS_MODE_M68K_CF_ISA_B
| CS_MODE_M68K_CF_ISA_C
| CS_MODE_M68K_CF_USP
| CS_MODE_M68K_CF_DIV
| CS_MODE_M68K_CF_MAC
| CS_MODE_M68K_CF_EMAC
| CS_MODE_M68K_CF_EMAC_B
| CS_MODE_M68K_CF_FPU
)
CS_MODE_M68K_CFV1 = CS_MODE_M68K_CF_ISA_C | CS_MODE_M68K_CF_USP
CS_MODE_M68K_CFV2 = CS_MODE_M68K_CF_ISA_A | CS_MODE_M68K_CF_DIV
CS_MODE_M68K_CFV3 = CS_MODE_M68K_CF_ISA_A | CS_MODE_M68K_CF_DIV
CS_MODE_M68K_CFV4 = CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_DIV
CS_MODE_M68K_CFV4E = (
CS_MODE_M68K_CF_ISA_B
| CS_MODE_M68K_CF_DIV
| CS_MODE_M68K_CF_USP
| CS_MODE_M68K_CF_EMAC
| CS_MODE_M68K_CF_FPU
)
CS_MODE_M68K_CFV5 = (
CS_MODE_M68K_CF_ISA_C
| CS_MODE_M68K_CF_USP
| CS_MODE_M68K_CF_DIV
| CS_MODE_M68K_CF_EMAC
| CS_MODE_M68K_CF_EMAC_B
)
CS_MODE_M68K_FEATURE_MASK = (
CS_MODE_M68K_000
| CS_MODE_M68K_010
| CS_MODE_M68K_020
| CS_MODE_M68K_030
| CS_MODE_M68K_040
| CS_MODE_M68K_060
| CS_MODE_M68K_CPU32
| CS_MODE_M68K_COLDFIRE
)
CS_MODE_BIG_ENDIAN = 1 << 31 # big-endian mode
CS_MODE_MIPS16 = CS_MODE_16 # Generic mips16
CS_MODE_MIPS32 = CS_MODE_32 # Generic mips32
@ -634,7 +702,7 @@ elif sys.platform in ("win32", "cygwin"):
_lib = "capstone.dll"
else:
_lib = "libcapstone.so"
mode = getattr(os, 'RTLD_DEEPBIND', 0)
mode = getattr(os, "RTLD_DEEPBIND", 0)
_found = False
@ -647,10 +715,7 @@ def _load_lib(path):
# if we're on linux, try again with .so.5 extension
if lib_file.endswith(".so"):
if os.path.exists(lib_file + ".{}".format(CS_VERSION_MAJOR)):
return ctypes.CDLL(
lib_file + ".{}".format(CS_VERSION_MAJOR),
mode=mode
)
return ctypes.CDLL(lib_file + ".{}".format(CS_VERSION_MAJOR), mode=mode)
return None

86
bindings/python/capstone/m68k.py
View file

@ -4,54 +4,61 @@ import ctypes
from . import copy_ctypes_list
from .m68k_const import *
# define the API
class M68KOpMem(ctypes.Structure):
_fields_ = (
('base_reg', ctypes.c_uint),
('index_reg', ctypes.c_uint),
('in_base_reg', ctypes.c_uint),
('in_disp', ctypes.c_int),
('out_disp', ctypes.c_int),
('disp', ctypes.c_short),
('scale', ctypes.c_ubyte),
('bitfield', ctypes.c_ubyte),
('width', ctypes.c_ubyte),
('offset', ctypes.c_ubyte),
('index_size', ctypes.c_ubyte),
('in_disp_size', ctypes.c_ubyte),
('out_disp_size', ctypes.c_ubyte),
('disp_size', ctypes.c_ubyte),
("base_reg", ctypes.c_uint),
("index_reg", ctypes.c_uint),
("in_base_reg", ctypes.c_uint),
("in_disp", ctypes.c_int),
("out_disp", ctypes.c_int),
("disp", ctypes.c_short),
("scale", ctypes.c_ubyte),
("bitfield", ctypes.c_ubyte),
("width", ctypes.c_ubyte),
("offset", ctypes.c_ubyte),
("index_size", ctypes.c_ubyte),
("in_disp_size", ctypes.c_ubyte),
("out_disp_size", ctypes.c_ubyte),
("disp_size", ctypes.c_ubyte),
("address", ctypes.c_uint64),
)
class M68KOpRegPair(ctypes.Structure):
_fields_ = (
('reg_0', ctypes.c_uint),
('reg_1', ctypes.c_uint),
("reg_0", ctypes.c_uint),
("reg_1", ctypes.c_uint),
)
class M68KOpValue(ctypes.Union):
_fields_ = (
('imm', ctypes.c_int64),
('dimm', ctypes.c_double),
('simm', ctypes.c_float),
('reg', ctypes.c_uint),
('reg_pair', M68KOpRegPair),
("imm", ctypes.c_int64),
("dimm", ctypes.c_double),
("simm", ctypes.c_float),
("reg", ctypes.c_uint),
("reg_pair", M68KOpRegPair),
)
class M68KOpBrDisp(ctypes.Structure):
_fields_ = (
('disp', ctypes.c_int),
('disp_size', ctypes.c_ubyte),
("disp", ctypes.c_int),
("disp_size", ctypes.c_ubyte),
)
class M68KOp(ctypes.Structure):
_fields_ = (
('value', M68KOpValue),
('mem', M68KOpMem),
('br_disp', M68KOpBrDisp),
('register_bits', ctypes.c_uint),
('type', ctypes.c_uint),
('address_mode', ctypes.c_uint),
("value", M68KOpValue),
("mem", M68KOpMem),
("br_disp", M68KOpBrDisp),
("register_bits", ctypes.c_uint),
("type", ctypes.c_uint),
("address_mode", ctypes.c_uint),
("flags", ctypes.c_ubyte),
)
@property
@ -69,7 +76,7 @@ class M68KOp(ctypes.Structure):
@property
def reg(self):
return self.value.reg
@property
def reg_pair(self):
return self.value.reg_pair
@ -82,22 +89,25 @@ class M68KOp(ctypes.Structure):
def register_bits(self):
return self.register_bits
class M68KOpSize(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('size', ctypes.c_uint),
("type", ctypes.c_uint),
("size", ctypes.c_uint),
)
def get(a):
return copy_ctypes_list(type, size)
class CsM68K(ctypes.Structure):
M68K_OPERAND_COUNT = 4
M68K_OPERAND_COUNT = 6
_fields_ = (
('operands', M68KOp * M68K_OPERAND_COUNT),
('op_size', M68KOpSize),
('op_count', ctypes.c_uint8),
("operands", M68KOp * M68K_OPERAND_COUNT),
("op_size", M68KOpSize),
("op_count", ctypes.c_uint8),
)
def get_arch_info(a):
return (copy_ctypes_list(a.operands[:a.op_count]), a.op_size)
return (copy_ctypes_list(a.operands[: a.op_count]), a.op_size)

763
bindings/python/capstone/m68k_const.py
View file

@ -1,6 +1,19 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
from . import (
CS_OP_INVALID,
CS_OP_REG,
CS_OP_IMM,
CS_OP_FP,
CS_OP_PRED,
CS_OP_SPECIAL,
CS_OP_MEM,
CS_OP_MEM_REG,
CS_OP_MEM_IMM,
UINT16_MAX,
UINT8_MAX,
)
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py]
M68K_OPERAND_COUNT = 4
M68K_OPERAND_COUNT = 6
M68K_REG_INVALID = 0
M68K_REG_D0 = 1
@ -49,7 +62,19 @@ M68K_REG_SRP = 43
M68K_REG_FPCR = 44
M68K_REG_FPSR = 45
M68K_REG_FPIAR = 46
M68K_REG_ENDING = 47
M68K_REG_TT0 = 47
M68K_REG_TT1 = 48
M68K_REG_CRP = 49
M68K_REG_ACC = 50
M68K_REG_ACC0 = 51
M68K_REG_ACC1 = 52
M68K_REG_ACC2 = 53
M68K_REG_ACC3 = 54
M68K_REG_ACCEXT01 = 55
M68K_REG_ACCEXT23 = 56
M68K_REG_MACSR = 57
M68K_REG_MASK = 58
M68K_REG_ENDING = 59
M68K_AM_NONE = 0
M68K_AM_REG_DIRECT_DATA = 1
@ -74,12 +99,20 @@ M68K_AM_BRANCH_DISPLACEMENT = 19
M68K_OP_INVALID = CS_OP_INVALID
M68K_OP_REG = CS_OP_REG
M68K_OP_IMM = CS_OP_IMM
M68K_OP_FP_SINGLE = CS_OP_SPECIAL+0
M68K_OP_FP_DOUBLE = CS_OP_SPECIAL+1
M68K_OP_REG_BITS = CS_OP_SPECIAL+2
M68K_OP_REG_PAIR = CS_OP_SPECIAL+3
M68K_OP_BR_DISP = CS_OP_SPECIAL+4
M68K_OP_FP_SINGLE = CS_OP_SPECIAL + 0
M68K_OP_FP_DOUBLE = CS_OP_SPECIAL + 1
M68K_OP_REG_BITS = CS_OP_SPECIAL + 2
M68K_OP_REG_PAIR = CS_OP_SPECIAL + 3
M68K_OP_BR_DISP = CS_OP_SPECIAL + 4
M68K_OP_SHIFT = CS_OP_SPECIAL + 5
M68K_OP_MEM = CS_OP_MEM
M68K_OP_FLAG_NONE = 0
M68K_OP_FLAG_REG_LOWER = 1
M68K_OP_FLAG_REG_UPPER = 2
M68K_OP_FLAG_SHIFT_LEFT = 4
M68K_OP_FLAG_SHIFT_RIGHT = 8
M68K_OP_FLAG_MEM_UPDATE = 16
M68K_BF_REG_FLAG = 0x80
M68K_OP_BR_DISP_SIZE_INVALID = 0
M68K_OP_BR_DISP_SIZE_BYTE = 1
@ -133,349 +166,377 @@ M68K_INS_BCHG = 29
M68K_INS_BCLR = 30
M68K_INS_BSET = 31
M68K_INS_BTST = 32
M68K_INS_BFCHG = 33
M68K_INS_BFCLR = 34
M68K_INS_BFEXTS = 35
M68K_INS_BFEXTU = 36
M68K_INS_BFFFO = 37
M68K_INS_BFINS = 38
M68K_INS_BFSET = 39
M68K_INS_BFTST = 40
M68K_INS_BKPT = 41
M68K_INS_CALLM = 42
M68K_INS_CAS = 43
M68K_INS_CAS2 = 44
M68K_INS_CHK = 45
M68K_INS_CHK2 = 46
M68K_INS_CLR = 47
M68K_INS_CMP = 48
M68K_INS_CMPA = 49
M68K_INS_CMPI = 50
M68K_INS_CMPM = 51
M68K_INS_CMP2 = 52
M68K_INS_CINVL = 53
M68K_INS_CINVP = 54
M68K_INS_CINVA = 55
M68K_INS_CPUSHL = 56
M68K_INS_CPUSHP = 57
M68K_INS_CPUSHA = 58
M68K_INS_DBT = 59
M68K_INS_DBF = 60
M68K_INS_DBHI = 61
M68K_INS_DBLS = 62
M68K_INS_DBCC = 63
M68K_INS_DBCS = 64
M68K_INS_DBNE = 65
M68K_INS_DBEQ = 66
M68K_INS_DBVC = 67
M68K_INS_DBVS = 68
M68K_INS_DBPL = 69
M68K_INS_DBMI = 70
M68K_INS_DBGE = 71
M68K_INS_DBLT = 72
M68K_INS_DBGT = 73
M68K_INS_DBLE = 74
M68K_INS_DBRA = 75
M68K_INS_DIVS = 76
M68K_INS_DIVSL = 77
M68K_INS_DIVU = 78
M68K_INS_DIVUL = 79
M68K_INS_EOR = 80
M68K_INS_EORI = 81
M68K_INS_EXG = 82
M68K_INS_EXT = 83
M68K_INS_EXTB = 84
M68K_INS_FABS = 85
M68K_INS_FSABS = 86
M68K_INS_FDABS = 87
M68K_INS_FACOS = 88
M68K_INS_FADD = 89
M68K_INS_FSADD = 90
M68K_INS_FDADD = 91
M68K_INS_FASIN = 92
M68K_INS_FATAN = 93
M68K_INS_FATANH = 94
M68K_INS_FBF = 95
M68K_INS_FBEQ = 96
M68K_INS_FBOGT = 97
M68K_INS_FBOGE = 98
M68K_INS_FBOLT = 99
M68K_INS_FBOLE = 100
M68K_INS_FBOGL = 101
M68K_INS_FBOR = 102
M68K_INS_FBUN = 103
M68K_INS_FBUEQ = 104
M68K_INS_FBUGT = 105
M68K_INS_FBUGE = 106
M68K_INS_FBULT = 107
M68K_INS_FBULE = 108
M68K_INS_FBNE = 109
M68K_INS_FBT = 110
M68K_INS_FBSF = 111
M68K_INS_FBSEQ = 112
M68K_INS_FBGT = 113
M68K_INS_FBGE = 114
M68K_INS_FBLT = 115
M68K_INS_FBLE = 116
M68K_INS_FBGL = 117
M68K_INS_FBGLE = 118
M68K_INS_FBNGLE = 119
M68K_INS_FBNGL = 120
M68K_INS_FBNLE = 121
M68K_INS_FBNLT = 122
M68K_INS_FBNGE = 123
M68K_INS_FBNGT = 124
M68K_INS_FBSNE = 125
M68K_INS_FBST = 126
M68K_INS_FCMP = 127
M68K_INS_FCOS = 128
M68K_INS_FCOSH = 129
M68K_INS_FDBF = 130
M68K_INS_FDBEQ = 131
M68K_INS_FDBOGT = 132
M68K_INS_FDBOGE = 133
M68K_INS_FDBOLT = 134
M68K_INS_FDBOLE = 135
M68K_INS_FDBOGL = 136
M68K_INS_FDBOR = 137
M68K_INS_FDBUN = 138
M68K_INS_FDBUEQ = 139
M68K_INS_FDBUGT = 140
M68K_INS_FDBUGE = 141
M68K_INS_FDBULT = 142
M68K_INS_FDBULE = 143
M68K_INS_FDBNE = 144
M68K_INS_FDBT = 145
M68K_INS_FDBSF = 146
M68K_INS_FDBSEQ = 147
M68K_INS_FDBGT = 148
M68K_INS_FDBGE = 149
M68K_INS_FDBLT = 150
M68K_INS_FDBLE = 151
M68K_INS_FDBGL = 152
M68K_INS_FDBGLE = 153
M68K_INS_FDBNGLE = 154
M68K_INS_FDBNGL = 155
M68K_INS_FDBNLE = 156
M68K_INS_FDBNLT = 157
M68K_INS_FDBNGE = 158
M68K_INS_FDBNGT = 159
M68K_INS_FDBSNE = 160
M68K_INS_FDBST = 161
M68K_INS_FDIV = 162
M68K_INS_FSDIV = 163
M68K_INS_FDDIV = 164
M68K_INS_FETOX = 165
M68K_INS_FETOXM1 = 166
M68K_INS_FGETEXP = 167
M68K_INS_FGETMAN = 168
M68K_INS_FINT = 169
M68K_INS_FINTRZ = 170
M68K_INS_FLOG10 = 171
M68K_INS_FLOG2 = 172
M68K_INS_FLOGN = 173
M68K_INS_FLOGNP1 = 174
M68K_INS_FMOD = 175
M68K_INS_FMOVE = 176
M68K_INS_FSMOVE = 177
M68K_INS_FDMOVE = 178
M68K_INS_FMOVECR = 179
M68K_INS_FMOVEM = 180
M68K_INS_FMUL = 181
M68K_INS_FSMUL = 182
M68K_INS_FDMUL = 183
M68K_INS_FNEG = 184
M68K_INS_FSNEG = 185
M68K_INS_FDNEG = 186
M68K_INS_FNOP = 187
M68K_INS_FREM = 188
M68K_INS_FRESTORE = 189
M68K_INS_FSAVE = 190
M68K_INS_FSCALE = 191
M68K_INS_FSGLDIV = 192
M68K_INS_FSGLMUL = 193
M68K_INS_FSIN = 194
M68K_INS_FSINCOS = 195
M68K_INS_FSINH = 196
M68K_INS_FSQRT = 197
M68K_INS_FSSQRT = 198
M68K_INS_FDSQRT = 199
M68K_INS_FSF = 200
M68K_INS_FSBEQ = 201
M68K_INS_FSOGT = 202
M68K_INS_FSOGE = 203
M68K_INS_FSOLT = 204
M68K_INS_FSOLE = 205
M68K_INS_FSOGL = 206
M68K_INS_FSOR = 207
M68K_INS_FSUN = 208
M68K_INS_FSUEQ = 209
M68K_INS_FSUGT = 210
M68K_INS_FSUGE = 211
M68K_INS_FSULT = 212
M68K_INS_FSULE = 213
M68K_INS_FSNE = 214
M68K_INS_FST = 215
M68K_INS_FSSF = 216
M68K_INS_FSSEQ = 217
M68K_INS_FSGT = 218
M68K_INS_FSGE = 219
M68K_INS_FSLT = 220
M68K_INS_FSLE = 221
M68K_INS_FSGL = 222
M68K_INS_FSGLE = 223
M68K_INS_FSNGLE = 224
M68K_INS_FSNGL = 225
M68K_INS_FSNLE = 226
M68K_INS_FSNLT = 227
M68K_INS_FSNGE = 228
M68K_INS_FSNGT = 229
M68K_INS_FSSNE = 230
M68K_INS_FSST = 231
M68K_INS_FSUB = 232
M68K_INS_FSSUB = 233
M68K_INS_FDSUB = 234
M68K_INS_FTAN = 235
M68K_INS_FTANH = 236
M68K_INS_FTENTOX = 237
M68K_INS_FTRAPF = 238
M68K_INS_FTRAPEQ = 239
M68K_INS_FTRAPOGT = 240
M68K_INS_FTRAPOGE = 241
M68K_INS_FTRAPOLT = 242
M68K_INS_FTRAPOLE = 243
M68K_INS_FTRAPOGL = 244
M68K_INS_FTRAPOR = 245
M68K_INS_FTRAPUN = 246
M68K_INS_FTRAPUEQ = 247
M68K_INS_FTRAPUGT = 248
M68K_INS_FTRAPUGE = 249
M68K_INS_FTRAPULT = 250
M68K_INS_FTRAPULE = 251
M68K_INS_FTRAPNE = 252
M68K_INS_FTRAPT = 253
M68K_INS_FTRAPSF = 254
M68K_INS_FTRAPSEQ = 255
M68K_INS_FTRAPGT = 256
M68K_INS_FTRAPGE = 257
M68K_INS_FTRAPLT = 258
M68K_INS_FTRAPLE = 259
M68K_INS_FTRAPGL = 260
M68K_INS_FTRAPGLE = 261
M68K_INS_FTRAPNGLE = 262
M68K_INS_FTRAPNGL = 263
M68K_INS_FTRAPNLE = 264
M68K_INS_FTRAPNLT = 265
M68K_INS_FTRAPNGE = 266
M68K_INS_FTRAPNGT = 267
M68K_INS_FTRAPSNE = 268
M68K_INS_FTRAPST = 269
M68K_INS_FTST = 270
M68K_INS_FTWOTOX = 271
M68K_INS_HALT = 272
M68K_INS_ILLEGAL = 273
M68K_INS_JMP = 274
M68K_INS_JSR = 275
M68K_INS_LEA = 276
M68K_INS_LINK = 277
M68K_INS_LPSTOP = 278
M68K_INS_LSL = 279
M68K_INS_LSR = 280
M68K_INS_MOVE = 281
M68K_INS_MOVEA = 282
M68K_INS_MOVEC = 283
M68K_INS_MOVEM = 284
M68K_INS_MOVEP = 285
M68K_INS_MOVEQ = 286
M68K_INS_MOVES = 287
M68K_INS_MOVE16 = 288
M68K_INS_MULS = 289
M68K_INS_MULU = 290
M68K_INS_NBCD = 291
M68K_INS_NEG = 292
M68K_INS_NEGX = 293
M68K_INS_NOP = 294
M68K_INS_NOT = 295
M68K_INS_OR = 296
M68K_INS_ORI = 297
M68K_INS_PACK = 298
M68K_INS_PEA = 299
M68K_INS_PFLUSH = 300
M68K_INS_PFLUSHA = 301
M68K_INS_PFLUSHAN = 302
M68K_INS_PFLUSHN = 303
M68K_INS_PLOADR = 304
M68K_INS_PLOADW = 305
M68K_INS_PLPAR = 306
M68K_INS_PLPAW = 307
M68K_INS_PMOVE = 308
M68K_INS_PMOVEFD = 309
M68K_INS_PTESTR = 310
M68K_INS_PTESTW = 311
M68K_INS_PULSE = 312
M68K_INS_REMS = 313
M68K_INS_REMU = 314
M68K_INS_RESET = 315
M68K_INS_ROL = 316
M68K_INS_ROR = 317
M68K_INS_ROXL = 318
M68K_INS_ROXR = 319
M68K_INS_RTD = 320
M68K_INS_RTE = 321
M68K_INS_RTM = 322
M68K_INS_RTR = 323
M68K_INS_RTS = 324
M68K_INS_SBCD = 325
M68K_INS_ST = 326
M68K_INS_SF = 327
M68K_INS_SHI = 328
M68K_INS_SLS = 329
M68K_INS_SCC = 330
M68K_INS_SHS = 331
M68K_INS_SCS = 332
M68K_INS_SLO = 333
M68K_INS_SNE = 334
M68K_INS_SEQ = 335
M68K_INS_SVC = 336
M68K_INS_SVS = 337
M68K_INS_SPL = 338
M68K_INS_SMI = 339
M68K_INS_SGE = 340
M68K_INS_SLT = 341
M68K_INS_SGT = 342
M68K_INS_SLE = 343
M68K_INS_STOP = 344
M68K_INS_SUB = 345
M68K_INS_SUBA = 346
M68K_INS_SUBI = 347
M68K_INS_SUBQ = 348
M68K_INS_SUBX = 349
M68K_INS_SWAP = 350
M68K_INS_TAS = 351
M68K_INS_TRAP = 352
M68K_INS_TRAPV = 353
M68K_INS_TRAPT = 354
M68K_INS_TRAPF = 355
M68K_INS_TRAPHI = 356
M68K_INS_TRAPLS = 357
M68K_INS_TRAPCC = 358
M68K_INS_TRAPHS = 359
M68K_INS_TRAPCS = 360
M68K_INS_TRAPLO = 361
M68K_INS_TRAPNE = 362
M68K_INS_TRAPEQ = 363
M68K_INS_TRAPVC = 364
M68K_INS_TRAPVS = 365
M68K_INS_TRAPPL = 366
M68K_INS_TRAPMI = 367
M68K_INS_TRAPGE = 368
M68K_INS_TRAPLT = 369
M68K_INS_TRAPGT = 370
M68K_INS_TRAPLE = 371
M68K_INS_TST = 372
M68K_INS_UNLK = 373
M68K_INS_UNPK = 374
M68K_INS_ENDING = 375
M68K_INS_BITREV = 33
M68K_INS_BYTEREV = 34
M68K_INS_BFCHG = 35
M68K_INS_BFCLR = 36
M68K_INS_BFEXTS = 37
M68K_INS_BFEXTU = 38
M68K_INS_BFFFO = 39
M68K_INS_BFINS = 40
M68K_INS_BFSET = 41
M68K_INS_BFTST = 42
M68K_INS_BKPT = 43
M68K_INS_CALLM = 44
M68K_INS_CAS = 45
M68K_INS_CAS2 = 46
M68K_INS_CHK = 47
M68K_INS_CHK2 = 48
M68K_INS_CLR = 49
M68K_INS_CMP = 50
M68K_INS_CMPA = 51
M68K_INS_CMPI = 52
M68K_INS_CMPM = 53
M68K_INS_CMP2 = 54
M68K_INS_CINVL = 55
M68K_INS_CINVP = 56
M68K_INS_CINVA = 57
M68K_INS_CPUSHL = 58
M68K_INS_CPUSHP = 59
M68K_INS_CPUSHA = 60
M68K_INS_DBT = 61
M68K_INS_DBF = 62
M68K_INS_DBHI = 63
M68K_INS_DBLS = 64
M68K_INS_DBCC = 65
M68K_INS_DBCS = 66
M68K_INS_DBNE = 67
M68K_INS_DBEQ = 68
M68K_INS_DBVC = 69
M68K_INS_DBVS = 70
M68K_INS_DBPL = 71
M68K_INS_DBMI = 72
M68K_INS_DBGE = 73
M68K_INS_DBLT = 74
M68K_INS_DBGT = 75
M68K_INS_DBLE = 76
M68K_INS_DBRA = 77
M68K_INS_DIVS = 78
M68K_INS_DIVSL = 79
M68K_INS_DIVU = 80
M68K_INS_DIVUL = 81
M68K_INS_EOR = 82
M68K_INS_EORI = 83
M68K_INS_EXG = 84
M68K_INS_EXT = 85
M68K_INS_EXTB = 86
M68K_INS_FF1 = 87
M68K_INS_FABS = 88
M68K_INS_FSABS = 89
M68K_INS_FDABS = 90
M68K_INS_FACOS = 91
M68K_INS_FADD = 92
M68K_INS_FSADD = 93
M68K_INS_FDADD = 94
M68K_INS_FASIN = 95
M68K_INS_FATAN = 96
M68K_INS_FATANH = 97
M68K_INS_FBF = 98
M68K_INS_FBEQ = 99
M68K_INS_FBOGT = 100
M68K_INS_FBOGE = 101
M68K_INS_FBOLT = 102
M68K_INS_FBOLE = 103
M68K_INS_FBOGL = 104
M68K_INS_FBOR = 105
M68K_INS_FBUN = 106
M68K_INS_FBUEQ = 107
M68K_INS_FBUGT = 108
M68K_INS_FBUGE = 109
M68K_INS_FBULT = 110
M68K_INS_FBULE = 111
M68K_INS_FBNE = 112
M68K_INS_FBT = 113
M68K_INS_FBSF = 114
M68K_INS_FBSEQ = 115
M68K_INS_FBGT = 116
M68K_INS_FBGE = 117
M68K_INS_FBLT = 118
M68K_INS_FBLE = 119
M68K_INS_FBGL = 120
M68K_INS_FBGLE = 121
M68K_INS_FBNGLE = 122
M68K_INS_FBNGL = 123
M68K_INS_FBNLE = 124
M68K_INS_FBNLT = 125
M68K_INS_FBNGE = 126
M68K_INS_FBNGT = 127
M68K_INS_FBSNE = 128
M68K_INS_FBST = 129
M68K_INS_FCMP = 130
M68K_INS_FCOS = 131
M68K_INS_FCOSH = 132
M68K_INS_FDBF = 133
M68K_INS_FDBEQ = 134
M68K_INS_FDBOGT = 135
M68K_INS_FDBOGE = 136
M68K_INS_FDBOLT = 137
M68K_INS_FDBOLE = 138
M68K_INS_FDBOGL = 139
M68K_INS_FDBOR = 140
M68K_INS_FDBUN = 141
M68K_INS_FDBUEQ = 142
M68K_INS_FDBUGT = 143
M68K_INS_FDBUGE = 144
M68K_INS_FDBULT = 145
M68K_INS_FDBULE = 146
M68K_INS_FDBNE = 147
M68K_INS_FDBT = 148
M68K_INS_FDBSF = 149
M68K_INS_FDBSEQ = 150
M68K_INS_FDBGT = 151
M68K_INS_FDBGE = 152
M68K_INS_FDBLT = 153
M68K_INS_FDBLE = 154
M68K_INS_FDBGL = 155
M68K_INS_FDBGLE = 156
M68K_INS_FDBNGLE = 157
M68K_INS_FDBNGL = 158
M68K_INS_FDBNLE = 159
M68K_INS_FDBNLT = 160
M68K_INS_FDBNGE = 161
M68K_INS_FDBNGT = 162
M68K_INS_FDBSNE = 163
M68K_INS_FDBST = 164
M68K_INS_FDIV = 165
M68K_INS_FSDIV = 166
M68K_INS_FDDIV = 167
M68K_INS_FETOX = 168
M68K_INS_FETOXM1 = 169
M68K_INS_FGETEXP = 170
M68K_INS_FGETMAN = 171
M68K_INS_FINT = 172
M68K_INS_FINTRZ = 173
M68K_INS_FLOG10 = 174
M68K_INS_FLOG2 = 175
M68K_INS_FLOGN = 176
M68K_INS_FLOGNP1 = 177
M68K_INS_FMOD = 178
M68K_INS_FMOVE = 179
M68K_INS_FSMOVE = 180
M68K_INS_FDMOVE = 181
M68K_INS_FMOVECR = 182
M68K_INS_FMOVEM = 183
M68K_INS_FMUL = 184
M68K_INS_FSMUL = 185
M68K_INS_FDMUL = 186
M68K_INS_FNEG = 187
M68K_INS_FSNEG = 188
M68K_INS_FDNEG = 189
M68K_INS_FNOP = 190
M68K_INS_FREM = 191
M68K_INS_FRESTORE = 192
M68K_INS_FSAVE = 193
M68K_INS_FSCALE = 194
M68K_INS_FSGLDIV = 195
M68K_INS_FSGLMUL = 196
M68K_INS_FSIN = 197
M68K_INS_FSINCOS = 198
M68K_INS_FSINH = 199
M68K_INS_FSQRT = 200
M68K_INS_FSSQRT = 201
M68K_INS_FDSQRT = 202
M68K_INS_FSF = 203
M68K_INS_FSBEQ = 204
M68K_INS_FSOGT = 205
M68K_INS_FSOGE = 206
M68K_INS_FSOLT = 207
M68K_INS_FSOLE = 208
M68K_INS_FSOGL = 209
M68K_INS_FSOR = 210
M68K_INS_FSUN = 211
M68K_INS_FSUEQ = 212
M68K_INS_FSUGT = 213
M68K_INS_FSUGE = 214
M68K_INS_FSULT = 215
M68K_INS_FSULE = 216
M68K_INS_FSNE = 217
M68K_INS_FST = 218
M68K_INS_FSSF = 219
M68K_INS_FSSEQ = 220
M68K_INS_FSGT = 221
M68K_INS_FSGE = 222
M68K_INS_FSLT = 223
M68K_INS_FSLE = 224
M68K_INS_FSGL = 225
M68K_INS_FSGLE = 226
M68K_INS_FSNGLE = 227
M68K_INS_FSNGL = 228
M68K_INS_FSNLE = 229
M68K_INS_FSNLT = 230
M68K_INS_FSNGE = 231
M68K_INS_FSNGT = 232
M68K_INS_FSSNE = 233
M68K_INS_FSST = 234
M68K_INS_FSUB = 235
M68K_INS_FSSUB = 236
M68K_INS_FDSUB = 237
M68K_INS_FTAN = 238
M68K_INS_FTANH = 239
M68K_INS_FTENTOX = 240
M68K_INS_FTRAPF = 241
M68K_INS_FTRAPEQ = 242
M68K_INS_FTRAPOGT = 243
M68K_INS_FTRAPOGE = 244
M68K_INS_FTRAPOLT = 245
M68K_INS_FTRAPOLE = 246
M68K_INS_FTRAPOGL = 247
M68K_INS_FTRAPOR = 248
M68K_INS_FTRAPUN = 249
M68K_INS_FTRAPUEQ = 250
M68K_INS_FTRAPUGT = 251
M68K_INS_FTRAPUGE = 252
M68K_INS_FTRAPULT = 253
M68K_INS_FTRAPULE = 254
M68K_INS_FTRAPNE = 255
M68K_INS_FTRAPT = 256
M68K_INS_FTRAPSF = 257
M68K_INS_FTRAPSEQ = 258
M68K_INS_FTRAPGT = 259
M68K_INS_FTRAPGE = 260
M68K_INS_FTRAPLT = 261
M68K_INS_FTRAPLE = 262
M68K_INS_FTRAPGL = 263
M68K_INS_FTRAPGLE = 264
M68K_INS_FTRAPNGLE = 265
M68K_INS_FTRAPNGL = 266
M68K_INS_FTRAPNLE = 267
M68K_INS_FTRAPNLT = 268
M68K_INS_FTRAPNGE = 269
M68K_INS_FTRAPNGT = 270
M68K_INS_FTRAPSNE = 271
M68K_INS_FTRAPST = 272
M68K_INS_FTST = 273
M68K_INS_FTWOTOX = 274
M68K_INS_HALT = 275
M68K_INS_ILLEGAL = 276
M68K_INS_INTOUCH = 277
M68K_INS_JMP = 278
M68K_INS_JSR = 279
M68K_INS_LEA = 280
M68K_INS_LINK = 281
M68K_INS_LPSTOP = 282
M68K_INS_LSL = 283
M68K_INS_LSR = 284
M68K_INS_MAC = 285
M68K_INS_MOVE = 286
M68K_INS_MOVEA = 287
M68K_INS_MOVEC = 288
M68K_INS_MOVEM = 289
M68K_INS_MOVEP = 290
M68K_INS_MOVEQ = 291
M68K_INS_MOVES = 292
M68K_INS_MOVE16 = 293
M68K_INS_MOV3Q = 294
M68K_INS_MOVCLR = 295
M68K_INS_MSAC = 296
M68K_INS_MULS = 297
M68K_INS_MULU = 298
M68K_INS_MVS = 299
M68K_INS_MVZ = 300
M68K_INS_NBCD = 301
M68K_INS_NEG = 302
M68K_INS_NEGX = 303
M68K_INS_NOP = 304
M68K_INS_NOT = 305
M68K_INS_OR = 306
M68K_INS_ORI = 307
M68K_INS_PACK = 308
M68K_INS_PEA = 309
M68K_INS_PFLUSH = 310
M68K_INS_PFLUSHA = 311
M68K_INS_PFLUSHAN = 312
M68K_INS_PFLUSHN = 313
M68K_INS_PLOADR = 314
M68K_INS_PLOADW = 315
M68K_INS_PLPAR = 316
M68K_INS_PLPAW = 317
M68K_INS_PMOVE = 318
M68K_INS_PMOVEFD = 319
M68K_INS_PTESTR = 320
M68K_INS_PTESTW = 321
M68K_INS_PULSE = 322
M68K_INS_REMS = 323
M68K_INS_REMU = 324
M68K_INS_RESET = 325
M68K_INS_ROL = 326
M68K_INS_ROR = 327
M68K_INS_ROXL = 328
M68K_INS_ROXR = 329
M68K_INS_RTD = 330
M68K_INS_RTE = 331
M68K_INS_RTM = 332
M68K_INS_RTR = 333
M68K_INS_RTS = 334
M68K_INS_SATS = 335
M68K_INS_SBCD = 336
M68K_INS_ST = 337
M68K_INS_SF = 338
M68K_INS_SHI = 339
M68K_INS_SLS = 340
M68K_INS_SCC = 341
M68K_INS_SHS = 342
M68K_INS_SCS = 343
M68K_INS_SLO = 344
M68K_INS_SNE = 345
M68K_INS_SEQ = 346
M68K_INS_SVC = 347
M68K_INS_SVS = 348
M68K_INS_SPL = 349
M68K_INS_SMI = 350
M68K_INS_SGE = 351
M68K_INS_SLT = 352
M68K_INS_SGT = 353
M68K_INS_SLE = 354
M68K_INS_STOP = 355
M68K_INS_STRLDSR = 356
M68K_INS_SUB = 357
M68K_INS_SUBA = 358
M68K_INS_SUBI = 359
M68K_INS_SUBQ = 360
M68K_INS_SUBX = 361
M68K_INS_SWAP = 362
M68K_INS_TAS = 363
M68K_INS_TRAP = 364
M68K_INS_TRAPV = 365
M68K_INS_TRAPT = 366
M68K_INS_TRAPF = 367
M68K_INS_TRAPHI = 368
M68K_INS_TRAPLS = 369
M68K_INS_TRAPCC = 370
M68K_INS_TRAPHS = 371
M68K_INS_TRAPCS = 372
M68K_INS_TRAPLO = 373
M68K_INS_TRAPNE = 374
M68K_INS_TRAPEQ = 375
M68K_INS_TRAPVC = 376
M68K_INS_TRAPVS = 377
M68K_INS_TRAPPL = 378
M68K_INS_TRAPMI = 379
M68K_INS_TRAPGE = 380
M68K_INS_TRAPLT = 381
M68K_INS_TRAPGT = 382
M68K_INS_TRAPLE = 383
M68K_INS_TST = 384
M68K_INS_UNLK = 385
M68K_INS_UNPK = 386
M68K_INS_WDDATA = 387
M68K_INS_WDEBUG = 388
M68K_INS_BGND = 389
M68K_INS_TBLS = 390
M68K_INS_TBLU = 391
M68K_INS_TBLSN = 392
M68K_INS_TBLUN = 393
M68K_INS_CP0BCBUSY = 394
M68K_INS_CP0LD = 395
M68K_INS_CP0NOP = 396
M68K_INS_CP0ST = 397
M68K_INS_CP1BCBUSY = 398
M68K_INS_CP1LD = 399
M68K_INS_CP1NOP = 400
M68K_INS_CP1ST = 401
M68K_INS_TPF = 402
M68K_INS_ENDING = 403
M68K_GRP_INVALID = 0
M68K_GRP_JUMP = 1

63
bindings/python/cstest_py/src/cstest_py/details.py
View file

@ -69,13 +69,20 @@ from capstone.m68k_const import (
M68K_OP_FP_DOUBLE,
M68K_OP_FP_SINGLE,
M68K_OP_MEM,
M68K_OP_SHIFT,
)
from capstone.mips_const import MIPS_OP_REG, MIPS_OP_IMM, MIPS_OP_MEM
from capstone.mos65xx_const import MOS65XX_OP_REG, MOS65XX_OP_MEM, MOS65XX_OP_IMM
from capstone.riscv import RISCV_OP_FP
from capstone.riscv_const import RISCV_OP_CSR, RISCV_OP_MEM, RISCV_OP_IMM, RISCV_OP_REG
from capstone.sh_const import SH_OP_REG, SH_OP_MEM, SH_OP_IMM
from capstone.sparc_const import SPARC_OP_REG, SPARC_OP_IMM, SPARC_OP_MEM, SPARC_OP_ASI, SPARC_OP_MEMBAR_TAG
from capstone.sparc_const import (
SPARC_OP_REG,
SPARC_OP_IMM,
SPARC_OP_MEM,
SPARC_OP_ASI,
SPARC_OP_MEMBAR_TAG,
)
from capstone.systemz_const import SYSTEMZ_OP_REG, SYSTEMZ_OP_IMM, SYSTEMZ_OP_MEM
from capstone.tms320c64x_const import (
TMS320C64X_OP_REG,
@ -401,10 +408,14 @@ def test_expected_x86(actual: CsInsn, expected: dict) -> bool:
def test_expected_ppc(actual: CsInsn, expected: dict) -> bool:
if "bc" in expected and not compare_uint8(actual.bc.bo, expected["bc"].get("bo"), "bo"):
if "bc" in expected and not compare_uint8(
actual.bc.bo, expected["bc"].get("bo"), "bo"
):
return False
if "bc" in expected and not compare_uint8(actual.bc.bi, expected["bc"].get("bi"), "bi"):
if "bc" in expected and not compare_uint8(
actual.bc.bi, expected["bc"].get("bi"), "bi"
):
return False
if "bc" in expected and not compare_enum(
@ -591,9 +602,7 @@ def test_expected_arm(actual: CsInsn, expected: dict) -> bool:
if not compare_int8(aop.neon_lane, eop.get("neon_lane"), "neon_lane"):
return False
if not compare_int32(
aop.vector_index, eop.get("vector_index"), "vector_index"
):
if not compare_int32(aop.vector_index, eop.get("vector_index"), "vector_index"):
return False
if not compare_tbool(aop.subtracted, eop.get("subtracted"), "subtracted"):
@ -715,9 +724,7 @@ def test_expected_aarch64(actual: CsInsn, expected: dict) -> bool:
if not compare_tbool(aop.is_vreg, eop.get("is_vreg"), "is_vreg"):
return False
if not compare_int32(
aop.vector_index, eop.get("vector_index"), "vector_index"
):
if not compare_int32(aop.vector_index, eop.get("vector_index"), "vector_index"):
return False
if not compare_tbool(
@ -760,32 +767,24 @@ def test_expected_aarch64(actual: CsInsn, expected: dict) -> bool:
if not compare_fp(aop.value.fp, eop.get("fp"), "fp"):
return False
elif aop.type == AARCH64_OP_SYSREG:
if not compare_enum(
aop.sysop.sub_type, eop.get("sub_type"), "sub_type"
):
if not compare_enum(aop.sysop.sub_type, eop.get("sub_type"), "sub_type"):
return False
if not compare_int32(
aop.sysop.reg.raw_val, eop.get("sys_raw_val"), "sys_raw_val"
):
return False
elif aop.type == AARCH64_OP_SYSIMM:
if not compare_enum(
aop.sysop.sub_type, eop.get("sub_type"), "sub_type"
):
if not compare_enum(aop.sysop.sub_type, eop.get("sub_type"), "sub_type"):
return False
if not compare_int32(
aop.sysop.imm.raw_val, eop.get("sys_raw_val"), "sys_raw_val"
):
return False
# EXACTFPIMM operands
if not compare_fp(
aop.fp, eop.get("fp"), "fp"
):
if not compare_fp(aop.fp, eop.get("fp"), "fp"):
return False
elif aop.type == AARCH64_OP_SYSALIAS:
if not compare_enum(
aop.sysop.sub_type, eop.get("sub_type"), "sub_type"
):
if not compare_enum(aop.sysop.sub_type, eop.get("sub_type"), "sub_type"):
return False
if not compare_int32(
aop.sysop.alias.raw_val, eop.get("sys_raw_val"), "sys_raw_val"
@ -1114,6 +1113,8 @@ def test_expected_m68k(actual: CsInsn, expected: dict) -> bool:
return False
if not compare_enum(aop.address_mode, eop.get("address_mode"), "address_mode"):
return False
if not compare_bit_flags(aop.flags, eop.get("flags"), "flags"):
return False
if aop.type == M68K_OP_REG:
if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
@ -1148,6 +1149,9 @@ def test_expected_m68k(actual: CsInsn, expected: dict) -> bool:
elif aop.type == M68K_OP_FP_SINGLE:
if not compare_fp(aop.simm, eop.get("simm"), "simm"):
return False
elif aop.type == M68K_OP_SHIFT:
# Shift direction is stored in aop.flags and compared above.
pass
elif aop.type == M68K_OP_MEM:
if "mem" not in eop:
continue
@ -1185,9 +1189,7 @@ def test_expected_m68k(actual: CsInsn, expected: dict) -> bool:
return False
if not compare_int16(aop.mem.disp, eop["mem"].get("disp"), "disp"):
return False
if not compare_int32(
aop.mem.in_disp, eop["mem"].get("in_disp"), "in_disp"
):
if not compare_int32(aop.mem.in_disp, eop["mem"].get("in_disp"), "in_disp"):
return False
if not compare_int32(
aop.mem.out_disp, eop["mem"].get("out_disp"), "out_disp"
@ -1203,6 +1205,10 @@ def test_expected_m68k(actual: CsInsn, expected: dict) -> bool:
return False
if not compare_uint8(aop.mem.offset, eop["mem"].get("offset"), "offset"):
return False
if not compare_uint64(
aop.mem.address, eop["mem"].get("address"), "address"
):
return False
else:
raise ValueError("Operand type not handled.")
return True
@ -1351,7 +1357,9 @@ def test_expected_riscv(actual: CsInsn, expected: dict) -> bool:
if not compare_fp(aop.dimm, eop.get("dimm"), "dimm"):
return False
elif aop.type == RISCV_OP_CSR:
if not compare_uint16(aop.csr, capstone.riscv.SYSREG_NAME_TO_VAL[eop.get("csr")], "csr"):
if not compare_uint16(
aop.csr, capstone.riscv.SYSREG_NAME_TO_VAL[eop.get("csr")], "csr"
):
return False
else:
raise ValueError("Operand type not handled.")
@ -1399,9 +1407,7 @@ def test_expected_SystemZ(actual: CsInsn, expected: dict) -> bool:
len(actual.operands), len(expected.get("operands")), "operands_count"
):
return False
elif not compare_enum(
actual.format, expected.get("format"), "format"
):
elif not compare_enum(actual.format, expected.get("format"), "format"):
return False
for aop, eop in zip(actual.operands, expected["operands"]):
@ -1563,6 +1569,7 @@ def test_expected_wasm(actual: CsInsn, expected: dict) -> bool:
raise ValueError("Operand type not handled.")
return True
def test_expected_arc(actual: CsInsn, expected: dict) -> bool:
if "operands" not in expected:
return True

53
contrib/m68k_instruction_tbl_gen/M68KInstructionTblGen.c
View file

@ -37,8 +37,7 @@ typedef struct {
static opcode_struct g_opcode_info[] = {
/* opcode handler mask match ea_mask mask2 match2*/
{ "d68000_1010", 0xf000, 0xa000, 0x000 },
{ "d68000_1111", 0xf000, 0xf000, 0x000 },
{ "dcf_1111", 0xf000, 0xf000, 0x000 },
{ "d68000_abcd_rr", 0xf1f8, 0xc100, 0x000 },
{ "d68000_abcd_mm", 0xf1f8, 0xc108, 0x000 },
{ "d68000_add_er_8", 0xf1c0, 0xd000, 0xbff },
@ -112,6 +111,8 @@ static opcode_struct g_opcode_info[] = {
{ "d68020_bsr_32", 0xffff, 0x61ff, 0x000 },
{ "d68000_btst_r", 0xf1c0, 0x0100, 0xbff },
{ "d68000_btst_s", 0xffc0, 0x0800, 0xbfb },
{ "dcf_bitrev", 0xfff8, 0x00c0, 0x000 },
{ "dcf_byterev", 0xfff8, 0x02c0, 0x000 },
{ "d68020_callm", 0xffc0, 0x06c0, 0x27b, 0xff00, 0x0000 },
{ "d68020_cas_8", 0xffc0, 0x0ac0, 0x3f8, 0xfe38, 0x0000 },
{ "d68020_cas_16", 0xffc0, 0x0cc0, 0x3f8, 0xfe38, 0x0000 },
@ -146,6 +147,20 @@ static opcode_struct g_opcode_info[] = {
{ "d68000_cmpm_8", 0xf1f8, 0xb108, 0x000 },
{ "d68000_cmpm_16", 0xf1f8, 0xb148, 0x000 },
{ "d68000_cmpm_32", 0xf1f8, 0xb188, 0x000 },
{ "dcf_cp0bcbusy", 0xfff8, 0xfcc0, 0x000 },
{ "dcf_cp1bcbusy", 0xfff8, 0xfec0, 0x000 },
{ "dcf_coproc_ldst", 0xffc0, 0xfc00, 0xfc0 },
{ "dcf_coproc_ldst", 0xffc0, 0xfc40, 0xfc0 },
{ "dcf_coproc_ldst", 0xffc0, 0xfc80, 0xfc0 },
{ "dcf_coproc_ldst", 0xffc0, 0xfd00, 0xfc0 },
{ "dcf_coproc_ldst", 0xffc0, 0xfd40, 0xfc0 },
{ "dcf_coproc_ldst", 0xffc0, 0xfd80, 0xfc0 },
{ "dcf_coproc_ldst", 0xffc0, 0xfe00, 0xfc0 },
{ "dcf_coproc_ldst", 0xffc0, 0xfe40, 0xfc0 },
{ "dcf_coproc_ldst", 0xffc0, 0xfe80, 0xfc0 },
{ "dcf_coproc_ldst", 0xffc0, 0xff00, 0xfc0 },
{ "dcf_coproc_ldst", 0xffc0, 0xff40, 0xfc0 },
{ "dcf_coproc_ldst", 0xffc0, 0xff80, 0xfc0 },
{ "d68020_cpbcc_16", 0xf1c0, 0xf080, 0x000 },
{ "d68020_cpbcc_32", 0xf1c0, 0xf0c0, 0x000 },
{ "d68020_cpdbcc", 0xf1f8, 0xf048, 0x000 },
@ -176,7 +191,9 @@ static opcode_struct g_opcode_info[] = {
{ "d68020_extb_32", 0xfff8, 0x49c0, 0x000 },
{ "d68000_ext_16", 0xfff8, 0x4880, 0x000 },
{ "d68000_ext_32", 0xfff8, 0x48c0, 0x000 },
{ "dcf_ff1", 0xfff8, 0x04c0, 0x000 },
{ "d68000_illegal", 0xffff, 0x4afc, 0x000 },
{ "dcf_intouch", 0xfff8, 0xf428, 0x000 },
{ "d68000_jmp", 0xffc0, 0x4ec0, 0x27b },
{ "d68000_jsr", 0xffc0, 0x4e80, 0x27b },
{ "d68000_lea", 0xf1c0, 0x41c0, 0x27b },
@ -208,6 +225,24 @@ static opcode_struct g_opcode_info[] = {
{ "d68000_move_to_usp", 0xfff8, 0x4e60, 0x000 },
{ "d68000_move_fr_usp", 0xfff8, 0x4e68, 0x000 },
{ "d68010_movec", 0xfffe, 0x4e7a, 0x000 },
{ "dcf_movclr_accn_reg", 0xf9f0, 0xa1c0, 0x000 },
{ "dcf_move_acc_reg", 0xfff0, 0xa180, 0x000 },
{ "dcf_move_accn_reg", 0xf9f0, 0xa180, 0x000 },
{ "dcf_move_acc_acc", 0xf9fc, 0xa110, 0x000 },
{ "dcf_move_reg_acc", 0xfff0, 0xa100, 0x000 },
{ "dcf_move_reg_accn", 0xf9f0, 0xa100, 0x000 },
{ "dcf_move_imm_acc", 0xffff, 0xa13c, 0x000 },
{ "dcf_move_imm_accn", 0xf9ff, 0xa13c, 0x000 },
{ "dcf_move_accext_reg", 0xfbf0, 0xab80, 0x000 },
{ "dcf_move_reg_accext", 0xfbc0, 0xab00, 0xc00 },
{ "dcf_move_imm_accext", 0xfbff, 0xab3c, 0x000 },
{ "dcf_move_macsr_reg", 0xfff0, 0xa980, 0x000 },
{ "dcf_move_reg_macsr", 0xfff0, 0xa900, 0x000 },
{ "dcf_move_imm_macsr", 0xffff, 0xa93c, 0x000 },
{ "dcf_move_mask_reg", 0xfff0, 0xad80, 0x000 },
{ "dcf_move_reg_mask", 0xfff0, 0xad00, 0x000 },
{ "dcf_move_imm_mask", 0xffff, 0xad3c, 0x000 },
{ "dcf_move_macsr_ccr", 0xffff, 0xa9c0, 0x000 },
{ "d68000_movem_pd_16", 0xfff8, 0x48a0, 0x000 },
{ "d68000_movem_pd_32", 0xfff8, 0x48e0, 0x000 },
{ "d68000_movem_re_16", 0xffc0, 0x4880, 0x2f8 },
@ -218,10 +253,17 @@ static opcode_struct g_opcode_info[] = {
{ "d68000_movep_er_32", 0xf1f8, 0x0148, 0x000 },
{ "d68000_movep_re_16", 0xf1f8, 0x0188, 0x000 },
{ "d68000_movep_re_32", 0xf1f8, 0x01c8, 0x000 },
{ "dcf_mov3q", 0xf1c0, 0xa140, 0xfff },
{ "dcf_mac_arith", 0xf000, 0xa000, 0xc00 },
{ "dcf_mac_arith", 0xf000, 0xa000, 0x3c0 },
{ "d68010_moves_8", 0xffc0, 0x0e00, 0x3f8, 0x07ff, 0x0000 },
{ "d68010_moves_16", 0xffc0, 0x0e40, 0x3f8, 0x07ff, 0x0000 },
{ "d68010_moves_32", 0xffc0, 0x0e80, 0x3f8, 0x07ff, 0x0000 },
{ "d68000_moveq", 0xf100, 0x7000, 0x000 },
{ "dcf_mvs_8", 0xf1c0, 0x7100, 0xbff },
{ "dcf_mvs_16", 0xf1c0, 0x7140, 0xfff },
{ "dcf_mvz_8", 0xf1c0, 0x7180, 0xbff },
{ "dcf_mvz_16", 0xf1c0, 0x71c0, 0xfff },
{ "d68040_move16_pi_pi", 0xfff8, 0xf620, 0x000, 0x8fff, 0x8000 },
{ "d68040_move16_pi_al", 0xfff8, 0xf600, 0x000 },
{ "d68040_move16_al_pi", 0xfff8, 0xf608, 0x000 },
@ -296,6 +338,7 @@ static opcode_struct g_opcode_info[] = {
{ "d68000_sbcd_mm", 0xf1f8, 0x8108, 0x000 },
{ "d68000_scc", 0xf0c0, 0x50c0, 0xbf8 },
{ "d68000_stop", 0xffff, 0x4e72, 0x000 },
{ "dcf_strldsr", 0xffff, 0x40e7, 0x000, 0xffff, 0x46fc },
{ "d68060_lpstop", 0xffff, 0xf800, 0x000 },
{ "d68cpu32_tbl", 0xffc0, 0xf800, 0x000 },
{ "d68040_pflush", 0xffe0, 0xf500, 0x000 },
@ -325,6 +368,7 @@ static opcode_struct g_opcode_info[] = {
{ "d68000_subx_mm_16", 0xf1f8, 0x9148, 0x000 },
{ "d68000_subx_mm_32", 0xf1f8, 0x9188, 0x000 },
{ "d68000_swap", 0xfff8, 0x4840, 0x000 },
{ "dcf_sats", 0xfff8, 0x4c80, 0x000 },
{ "d68000_tas", 0xffc0, 0x4ac0, 0xbf8 },
{ "d68000_trap", 0xfff0, 0x4e40, 0x000 },
{ "d68020_trapcc_0", 0xf0ff, 0x50fc, 0x000 },
@ -348,6 +392,11 @@ static opcode_struct g_opcode_info[] = {
{ "d68000_unlk", 0xfff8, 0x4e58, 0x000 },
{ "d68020_unpk_rr", 0xf1f8, 0x8180, 0x000 },
{ "d68020_unpk_mm", 0xf1f8, 0x8188, 0x000 },
{ "dcf_wddata", 0xffc0, 0xfb00, 0x3f8 },
{ "dcf_wddata", 0xffc0, 0xfb40, 0x3f8 },
{ "dcf_wddata", 0xffc0, 0xfb80, 0x3f8 },
{ "dcf_wdebug", 0xfff8, 0xfbd0, 0x000, 0xffff, 0x0003 },
{ "dcf_wdebug", 0xfff8, 0xfbe8, 0x000, 0xffff, 0x0003 },
{ 0, 0, 0, 0 }
};

4
cs.c
View file

@ -166,9 +166,7 @@ typedef struct cs_arch_config {
{ \
M68K_global_init, \
M68K_option, \
~(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_000 | CS_MODE_M68K_010 | \
CS_MODE_M68K_020 | CS_MODE_M68K_030 | CS_MODE_M68K_040 | \
CS_MODE_M68K_060 | CS_MODE_M68K_CPU32), \
~(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_FEATURE_MASK), \
}
#define CS_ARCH_CONFIG_TMS320C64X \
{ \

14
cstool/cstool.c
View file

@ -428,6 +428,20 @@ static struct {
{ "m68k40", "m68k, 68040", CS_ARCH_M68K, CS_MODE_M68K_040 },
{ "m68k60", "m68k, 68060", CS_ARCH_M68K, CS_MODE_M68K_060 },
{ "m68kcpu32", "m68k, cpu32", CS_ARCH_M68K, CS_MODE_M68K_CPU32 },
{ "m68kcf", "m68k, ColdFire all features", CS_ARCH_M68K,
CS_MODE_BIG_ENDIAN | CS_MODE_M68K_COLDFIRE },
{ "m68kcfv1", "m68k, ColdFire V1", CS_ARCH_M68K,
CS_MODE_BIG_ENDIAN | CS_MODE_M68K_CFV1 },
{ "m68kcfv2", "m68k, ColdFire V2", CS_ARCH_M68K,
CS_MODE_BIG_ENDIAN | CS_MODE_M68K_CFV2 },
{ "m68kcfv3", "m68k, ColdFire V3", CS_ARCH_M68K,
CS_MODE_BIG_ENDIAN | CS_MODE_M68K_CFV3 },
{ "m68kcfv4", "m68k, ColdFire V4", CS_ARCH_M68K,
CS_MODE_BIG_ENDIAN | CS_MODE_M68K_CFV4 },
{ "m68kcfv4e", "m68k, ColdFire V4e", CS_ARCH_M68K,
CS_MODE_BIG_ENDIAN | CS_MODE_M68K_CFV4E },
{ "m68kcfv5", "m68k, ColdFire V5", CS_ARCH_M68K,
CS_MODE_BIG_ENDIAN | CS_MODE_M68K_CFV5 },
{ "tms320c64x", "tms320c64x, big endian", CS_ARCH_TMS320C64X,
CS_MODE_BIG_ENDIAN },

40
cstool/cstool_m68k.c
View file

@ -6,6 +6,7 @@
//
//
#include <inttypes.h>
#include <stdio.h>
#include <capstone/capstone.h>
#include "cstool.h"
@ -38,8 +39,38 @@ static const char *s_addressing_modes[] = {
"Absolute Data Addressing - Short",
"Absolute Data Addressing - Long",
"Immediate value",
"Branch displacement",
};
static void print_operand_flags(unsigned int op_index, uint8_t flags)
{
int need_sep = 0;
if (!flags)
return;
printf("\t\t\toperands[%u].flags: ", op_index);
if (flags & M68K_OP_FLAG_REG_LOWER) {
printf("REG_LOWER");
need_sep = 1;
}
if (flags & M68K_OP_FLAG_REG_UPPER) {
printf("%sREG_UPPER", need_sep ? ", " : "");
need_sep = 1;
}
if (flags & M68K_OP_FLAG_SHIFT_LEFT) {
printf("%sSHIFT_LEFT", need_sep ? ", " : "");
need_sep = 1;
}
if (flags & M68K_OP_FLAG_SHIFT_RIGHT) {
printf("%sSHIFT_RIGHT", need_sep ? ", " : "");
need_sep = 1;
}
if (flags & M68K_OP_FLAG_MEM_UPDATE)
printf("%sMEM_UPDATE", need_sep ? ", " : "");
printf("\n");
}
static void print_read_write_regs(cs_detail *detail, csh handle)
{
int i;
@ -96,6 +127,11 @@ void print_insn_detail_m68k(csh handle, cs_insn *ins)
printf("\t\t\toperands[%u].mem.base: REG = %s\n",
i,
cs_reg_name(handle, op->mem.base_reg));
if (op->address_mode == M68K_AM_ABSOLUTE_DATA_SHORT ||
op->address_mode == M68K_AM_ABSOLUTE_DATA_LONG)
printf("\t\t\toperands[%u].mem.address: 0x%" PRIx64
"\n",
i, op->mem.address);
if (op->mem.index_reg != M68K_REG_INVALID) {
printf("\t\t\toperands[%u].mem.index: REG = %s\n",
i,
@ -121,6 +157,10 @@ void print_insn_detail_m68k(csh handle, cs_insn *ins)
printf("\t\toperands[%u].type: FP_DOUBLE\n", i);
printf("\t\t\toperands[%u].dimm: %lf\n", i, op->dimm);
break;
case M68K_OP_SHIFT:
printf("\t\toperands[%u].type: SHIFT\n", i);
break;
}
print_operand_flags(i, op->flags);
}
}

5
docs/cs_v6_release_guide.md
View file

@ -281,8 +281,8 @@ Nonetheless, we hope this additional information is useful to you.
**M68K**
- Architecture support added for `cpu32`, `M68060`.
- Enhanced bitfield instructions, PC-relative addressing, and immediate value type handling.
- Architecture support added for `cpu32`, `M68060`, and ColdFire variants (`CFV1`, `CFV2`, `CFV3`, `CFV4`, `CFV4E`, `CFV5`), including feature flags for USP, DIV, MAC/EMAC, and FPU instructions.
- Expanded operand details for bitfield instructions, PC-relative addressing, immediate value types, and memory addressing metadata.
- Expanded integration tests and refactored invalid assembly edge cases.
**UX**
@ -482,6 +482,7 @@ Such an instruction is ill-defined in LLVM and should be fixed upstream.
| m68k_op_mem.in_disp, m68k_op_mem.out_disp | These fields are now signed instead of unsigned. | The M68K architecture uses sign extended displacements for effective address calculation. |
| m68k_op_mem.disp_size | Defines if the .disp field was encoded as a byte (false) or word (true) | Necessary for accurate printing. |
| m68k_op_mem.in_disp_size, m68k_op_mem.out_disp_size | Defines if the .in_disp and .out_disp fields respectively were encoded as words (false) or longs (true) | Necessary for accurate printing. |
| `M68K_OP_MEM` storage | Memory operands now store base registers in `m68k_op_mem.base_reg` and absolute addresses in `m68k_op_mem.address`; `op->reg` and `op->imm` are only used for register and immediate operands. | Keeps memory-addressing details in `m68k_op_mem` consistently. |
### Notes about AArch64, SystemZ and ARM renaming

30
include/capstone/capstone.h
View file

@ -164,6 +164,36 @@ typedef enum cs_mode {
CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode
CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode
CS_MODE_M68K_CPU32 = 1 << 7,
CS_MODE_M68K_CF_ISA_A = 1 << 8, ///< ColdFire ISA_A
CS_MODE_M68K_CF_ISA_A_PLUS = 1 << 9, ///< ColdFire ISA_A+
CS_MODE_M68K_CF_ISA_B = 1 << 10, ///< ColdFire ISA_B
CS_MODE_M68K_CF_ISA_C = 1 << 11, ///< ColdFire ISA_C
CS_MODE_M68K_CF_USP = 1 << 12, ///< ColdFire USP instructions
CS_MODE_M68K_CF_DIV = 1 << 13, ///< ColdFire hardware divide
CS_MODE_M68K_CF_MAC = 1 << 14, ///< ColdFire MAC
CS_MODE_M68K_CF_EMAC = 1 << 15, ///< ColdFire EMAC
CS_MODE_M68K_CF_EMAC_B = 1 << 16, ///< ColdFire EMAC_B
CS_MODE_M68K_CF_FPU = 1 << 17, ///< ColdFire FPU
CS_MODE_M68K_COLDFIRE = CS_MODE_M68K_CF_ISA_A |
CS_MODE_M68K_CF_ISA_A_PLUS |
CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_ISA_C |
CS_MODE_M68K_CF_USP | CS_MODE_M68K_CF_DIV |
CS_MODE_M68K_CF_MAC | CS_MODE_M68K_CF_EMAC |
CS_MODE_M68K_CF_EMAC_B | CS_MODE_M68K_CF_FPU,
CS_MODE_M68K_CFV1 = CS_MODE_M68K_CF_ISA_C | CS_MODE_M68K_CF_USP,
CS_MODE_M68K_CFV2 = CS_MODE_M68K_CF_ISA_A | CS_MODE_M68K_CF_DIV,
CS_MODE_M68K_CFV3 = CS_MODE_M68K_CF_ISA_A | CS_MODE_M68K_CF_DIV,
CS_MODE_M68K_CFV4 = CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_DIV,
CS_MODE_M68K_CFV4E = CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_DIV |
CS_MODE_M68K_CF_USP | CS_MODE_M68K_CF_EMAC |
CS_MODE_M68K_CF_FPU,
CS_MODE_M68K_CFV5 = CS_MODE_M68K_CF_ISA_C | CS_MODE_M68K_CF_USP |
CS_MODE_M68K_CF_DIV | CS_MODE_M68K_CF_EMAC |
CS_MODE_M68K_CF_EMAC_B,
CS_MODE_M68K_FEATURE_MASK = CS_MODE_M68K_000 | CS_MODE_M68K_010 |
CS_MODE_M68K_020 | CS_MODE_M68K_030 |
CS_MODE_M68K_040 | CS_MODE_M68K_060 |
CS_MODE_M68K_CPU32 | CS_MODE_M68K_COLDFIRE,
CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode
CS_MODE_MIPS16 = CS_MODE_16, ///< Generic mips16
CS_MODE_MIPS32 = CS_MODE_32, ///< Generic mips32

51
include/capstone/m68k.h
View file

@ -15,7 +15,7 @@ extern "C" {
#pragma warning(disable : 4201)
#endif
#define M68K_OPERAND_COUNT 4
#define M68K_OPERAND_COUNT 6
/// M68K registers and special registers
typedef enum m68k_reg {
@ -76,6 +76,15 @@ typedef enum m68k_reg {
M68K_REG_TT0,
M68K_REG_TT1,
M68K_REG_CRP,
M68K_REG_ACC,
M68K_REG_ACC0,
M68K_REG_ACC1,
M68K_REG_ACC2,
M68K_REG_ACC3,
M68K_REG_ACCEXT01,
M68K_REG_ACCEXT23,
M68K_REG_MACSR,
M68K_REG_MASK,
M68K_REG_ENDING, // <-- mark the end of the list of registers
} m68k_reg;
@ -126,9 +135,24 @@ typedef enum m68k_op_type {
// Register pair in the same op (upper 4 bits for first reg, lower for second)
M68K_OP_REG_PAIR = CS_OP_SPECIAL + 3,
M68K_OP_BR_DISP = CS_OP_SPECIAL + 4, ///< Branch displacement
/// Shift-direction pseudo operand.
/// Shift direction is set in cs_m68k_op.flags
M68K_OP_SHIFT = CS_OP_SPECIAL + 5,
M68K_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
} m68k_op_type;
/// Per-operand modifier flags.
typedef enum m68k_op_flags {
M68K_OP_FLAG_NONE = 0,
M68K_OP_FLAG_REG_LOWER =
1 << 0, ///< Lower half of a ColdFire MAC word register operand
M68K_OP_FLAG_REG_UPPER =
1 << 1, ///< Upper half of a ColdFire MAC word register operand
M68K_OP_FLAG_SHIFT_LEFT = 1 << 2, ///< ColdFire MAC left-shift operand
M68K_OP_FLAG_SHIFT_RIGHT = 1 << 3, ///< ColdFire MAC right-shift operand
M68K_OP_FLAG_MEM_UPDATE = 1 << 4, ///< ColdFire MAC memory update marker
} m68k_op_flags;
/// Instruction's operand referring to memory
/// This is associated with M68K_OP_MEM operand type above
typedef struct m68k_op_mem {
@ -146,6 +170,7 @@ typedef struct m68k_op_mem {
uint8_t in_disp_size; ///< 0 = word, 1 = long
uint8_t out_disp_size; ///< 0 = word, 1 = long
uint8_t disp_size; ///< 0 = byte, 1 = word
uint64_t address; ///< absolute address for absolute MEM operands
} m68k_op_mem;
/// Bitfield offset/width helpers for m68k_op_mem.
@ -189,6 +214,7 @@ typedef struct cs_m68k_op {
uint32_t register_bits; ///< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)
m68k_op_type type;
m68k_address_mode address_mode; ///< M68K addressing mode for this op
uint8_t flags; ///< Operand modifier flags, see m68k_op_flags.
} cs_m68k_op;
/// Operation size of the CPU instructions
@ -270,6 +296,8 @@ typedef enum m68k_insn {
M68K_INS_BCLR,
M68K_INS_BSET,
M68K_INS_BTST,
M68K_INS_BITREV,
M68K_INS_BYTEREV,
M68K_INS_BFCHG,
M68K_INS_BFCLR,
M68K_INS_BFEXTS,
@ -322,6 +350,7 @@ typedef enum m68k_insn {
M68K_INS_EXG,
M68K_INS_EXT,
M68K_INS_EXTB,
M68K_INS_FF1,
M68K_INS_FABS,
M68K_INS_FSABS,
M68K_INS_FDABS,
@ -511,6 +540,7 @@ typedef enum m68k_insn {
M68K_INS_FTWOTOX,
M68K_INS_HALT,
M68K_INS_ILLEGAL,
M68K_INS_INTOUCH,
M68K_INS_JMP,
M68K_INS_JSR,
M68K_INS_LEA,
@ -518,6 +548,7 @@ typedef enum m68k_insn {
M68K_INS_LPSTOP,
M68K_INS_LSL,
M68K_INS_LSR,
M68K_INS_MAC,
M68K_INS_MOVE,
M68K_INS_MOVEA,
M68K_INS_MOVEC,
@ -526,8 +557,13 @@ typedef enum m68k_insn {
M68K_INS_MOVEQ,
M68K_INS_MOVES,
M68K_INS_MOVE16,
M68K_INS_MOV3Q,
M68K_INS_MOVCLR,
M68K_INS_MSAC,
M68K_INS_MULS,
M68K_INS_MULU,
M68K_INS_MVS,
M68K_INS_MVZ,
M68K_INS_NBCD,
M68K_INS_NEG,
M68K_INS_NEGX,
@ -562,6 +598,7 @@ typedef enum m68k_insn {
M68K_INS_RTM,
M68K_INS_RTR,
M68K_INS_RTS,
M68K_INS_SATS,
M68K_INS_SBCD,
M68K_INS_ST,
M68K_INS_SF,
@ -582,6 +619,7 @@ typedef enum m68k_insn {
M68K_INS_SGT,
M68K_INS_SLE,
M68K_INS_STOP,
M68K_INS_STRLDSR,
M68K_INS_SUB,
M68K_INS_SUBA,
M68K_INS_SUBI,
@ -612,11 +650,22 @@ typedef enum m68k_insn {
M68K_INS_TST,
M68K_INS_UNLK,
M68K_INS_UNPK,
M68K_INS_WDDATA,
M68K_INS_WDEBUG,
M68K_INS_BGND,
M68K_INS_TBLS,
M68K_INS_TBLU,
M68K_INS_TBLSN,
M68K_INS_TBLUN,
M68K_INS_CP0BCBUSY,
M68K_INS_CP0LD,
M68K_INS_CP0NOP,
M68K_INS_CP0ST,
M68K_INS_CP1BCBUSY,
M68K_INS_CP1LD,
M68K_INS_CP1NOP,
M68K_INS_CP1ST,
M68K_INS_TPF,
M68K_INS_ENDING, // <-- mark the end of the list of instructions
} m68k_insn;

11
suite/cstest/include/test_detail_m68k.h
View file

@ -23,6 +23,7 @@ typedef struct {
uint8_t bitfield;
uint8_t width;
uint8_t offset;
uint64_t address;
} TestDetailM68KOpMem;
static const cyaml_schema_field_t test_detail_m68k_op_mem_mapping_schema[] = {
@ -51,6 +52,8 @@ static const cyaml_schema_field_t test_detail_m68k_op_mem_mapping_schema[] = {
width),
CYAML_FIELD_UINT("offset", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem,
offset),
CYAML_FIELD_UINT("address", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem,
address),
CYAML_FIELD_INT("in_disp_size",
CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
TestDetailM68KOpMem, in_disp_size),
@ -80,9 +83,11 @@ typedef struct {
float simm;
TestDetailM68KOpMem *mem;
char **flags;
size_t flags_count;
} TestDetailM68KOp;
static const cyaml_schema_value_t test_detail_m68k_op_sys_psr_schema = {
static const cyaml_schema_value_t test_detail_m68k_op_flag_schema = {
CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED),
};
@ -111,6 +116,10 @@ static const cyaml_schema_field_t test_detail_m68k_op_mapping_schema[] = {
CYAML_FIELD_FLOAT("simm", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, simm),
CYAML_FIELD_MAPPING_PTR("mem", CYAML_FLAG_OPTIONAL, TestDetailM68KOp,
mem, test_detail_m68k_op_mem_mapping_schema),
CYAML_FIELD_SEQUENCE("flags", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
TestDetailM68KOp, flags,
&test_detail_m68k_op_flag_schema, 0,
CYAML_UNLIMITED),
CYAML_FIELD_END
};

26
suite/cstest/include/test_mapping.h
View file

@ -103,7 +103,27 @@ static const cs_enum_id_map test_mode_map[] = {
{ .str = "CS_MODE_M68K_030", .val = CS_MODE_M68K_030 },
{ .str = "CS_MODE_M68K_040", .val = CS_MODE_M68K_040 },
{ .str = "CS_MODE_M68K_060", .val = CS_MODE_M68K_060 },
{ .str = "CS_MODE_M68K_CFV1", .val = CS_MODE_M68K_CFV1 },
{ .str = "CS_MODE_M68K_CFV2", .val = CS_MODE_M68K_CFV2 },
{ .str = "CS_MODE_M68K_CFV3", .val = CS_MODE_M68K_CFV3 },
{ .str = "CS_MODE_M68K_CFV4", .val = CS_MODE_M68K_CFV4 },
{ .str = "CS_MODE_M68K_CFV4E", .val = CS_MODE_M68K_CFV4E },
{ .str = "CS_MODE_M68K_CFV5", .val = CS_MODE_M68K_CFV5 },
{ .str = "CS_MODE_M68K_CF_DIV", .val = CS_MODE_M68K_CF_DIV },
{ .str = "CS_MODE_M68K_CF_EMAC", .val = CS_MODE_M68K_CF_EMAC },
{ .str = "CS_MODE_M68K_CF_EMAC_B", .val = CS_MODE_M68K_CF_EMAC_B },
{ .str = "CS_MODE_M68K_CF_FPU", .val = CS_MODE_M68K_CF_FPU },
{ .str = "CS_MODE_M68K_CF_ISA_A", .val = CS_MODE_M68K_CF_ISA_A },
{ .str = "CS_MODE_M68K_CF_ISA_A_PLUS",
.val = CS_MODE_M68K_CF_ISA_A_PLUS },
{ .str = "CS_MODE_M68K_CF_ISA_B", .val = CS_MODE_M68K_CF_ISA_B },
{ .str = "CS_MODE_M68K_CF_ISA_C", .val = CS_MODE_M68K_CF_ISA_C },
{ .str = "CS_MODE_M68K_CF_MAC", .val = CS_MODE_M68K_CF_MAC },
{ .str = "CS_MODE_M68K_CF_USP", .val = CS_MODE_M68K_CF_USP },
{ .str = "CS_MODE_M68K_COLDFIRE", .val = CS_MODE_M68K_COLDFIRE },
{ .str = "CS_MODE_M68K_CPU32", .val = CS_MODE_M68K_CPU32 },
{ .str = "CS_MODE_M68K_FEATURE_MASK",
.val = CS_MODE_M68K_FEATURE_MASK },
{ .str = "CS_MODE_MCLASS", .val = CS_MODE_MCLASS },
{ .str = "CS_MODE_MICRO", .val = CS_MODE_MICRO },
{ .str = "CS_MODE_MICRO32R3", .val = CS_MODE_MICRO32R3 },
@ -918,6 +938,11 @@ static const cs_enum_id_map cs_enum_map[] = {
.val = M68K_OP_BR_DISP_SIZE_LONG },
{ .str = "M68K_OP_BR_DISP_SIZE_WORD",
.val = M68K_OP_BR_DISP_SIZE_WORD },
{ .str = "M68K_OP_FLAG_MEM_UPDATE", .val = M68K_OP_FLAG_MEM_UPDATE },
{ .str = "M68K_OP_FLAG_REG_LOWER", .val = M68K_OP_FLAG_REG_LOWER },
{ .str = "M68K_OP_FLAG_REG_UPPER", .val = M68K_OP_FLAG_REG_UPPER },
{ .str = "M68K_OP_FLAG_SHIFT_LEFT", .val = M68K_OP_FLAG_SHIFT_LEFT },
{ .str = "M68K_OP_FLAG_SHIFT_RIGHT", .val = M68K_OP_FLAG_SHIFT_RIGHT },
{ .str = "M68K_OP_FP_DOUBLE", .val = M68K_OP_FP_DOUBLE },
{ .str = "M68K_OP_FP_SINGLE", .val = M68K_OP_FP_SINGLE },
{ .str = "M68K_OP_IMM", .val = M68K_OP_IMM },
@ -925,6 +950,7 @@ static const cs_enum_id_map cs_enum_map[] = {
{ .str = "M68K_OP_REG", .val = M68K_OP_REG },
{ .str = "M68K_OP_REG_BITS", .val = M68K_OP_REG_BITS },
{ .str = "M68K_OP_REG_PAIR", .val = M68K_OP_REG_PAIR },
{ .str = "M68K_OP_SHIFT", .val = M68K_OP_SHIFT },
{ .str = "M68K_SIZE_TYPE_CPU", .val = M68K_SIZE_TYPE_CPU },
{ .str = "M68K_SIZE_TYPE_FPU", .val = M68K_SIZE_TYPE_FPU },
{ .str = "MIPS_INS_ADDIU", .val = MIPS_INS_ADDIU },

2
suite/cstest/src/test_case.c
View file

@ -65,7 +65,7 @@ char *test_input_stringify(const TestInput *test_input, const char *prefix)
cs_mem_free(byte_seq);
return NULL;
}
char opt_seq[128] = { 0 };
char opt_seq[512] = { 0 };
str_append_no_realloc(opt_seq, sizeof(opt_seq), "[");
for (size_t i = 0; i < test_input->options_count; ++i) {
str_append_no_realloc(opt_seq, sizeof(opt_seq),

18
suite/cstest/src/test_detail_m68k.c
View file

@ -29,6 +29,7 @@ TestDetailM68KOpMem *test_detail_m68k_op_mem_clone(TestDetailM68KOpMem *mem)
clone->bitfield = mem->bitfield;
clone->width = mem->width;
clone->offset = mem->offset;
clone->address = mem->address;
clone->in_disp_size = mem->in_disp_size;
clone->out_disp_size = mem->out_disp_size;
clone->disp_size = mem->disp_size;
@ -112,6 +113,11 @@ TestDetailM68KOp *test_detail_m68k_op_clone(TestDetailM68KOp *op)
clone->br_disp = op->br_disp;
clone->br_disp_size = op->br_disp_size;
clone->register_bits = op->register_bits;
clone->flags_count = op->flags_count;
if (op->flags_count > 0)
clone->flags = cs_mem_calloc(sizeof(char *), op->flags_count);
for (size_t i = 0; i < clone->flags_count; ++i)
clone->flags[i] = op->flags[i] ? strdup(op->flags[i]) : NULL;
clone->mem = op->mem ? test_detail_m68k_op_mem_clone(op->mem) : NULL;
return clone;
@ -127,6 +133,9 @@ void test_detail_m68k_op_free(TestDetailM68KOp *op)
cs_mem_free(op->reg_pair_0);
cs_mem_free(op->reg_pair_1);
cs_mem_free(op->address_mode);
for (size_t i = 0; i < op->flags_count; ++i)
cs_mem_free(op->flags[i]);
cs_mem_free(op->flags);
test_detail_m68k_op_mem_free(op->mem);
cs_mem_free(op);
}
@ -147,6 +156,8 @@ bool test_expected_m68k(csh *handle, cs_m68k *actual, TestDetailM68K *expected)
TestDetailM68KOp *eop = expected->operands[i];
compare_enum_ret(op->type, eop->type, false);
compare_enum_ret(op->address_mode, eop->address_mode, false);
compare_bit_flags_ret(op->flags, eop->flags, eop->flags_count,
false);
switch (op->type) {
default:
fprintf(stderr,
@ -181,6 +192,9 @@ bool test_expected_m68k(csh *handle, cs_m68k *actual, TestDetailM68K *expected)
compare_uint8_ret(op->br_disp.disp_size,
eop->br_disp_size, false);
break;
case M68K_OP_SHIFT:
// Shift direction is stored in op->flags and compared above.
break;
case M68K_OP_MEM:
if (!eop->mem) {
break;
@ -221,6 +235,10 @@ bool test_expected_m68k(csh *handle, cs_m68k *actual, TestDetailM68K *expected)
compare_uint8_ret(op->mem.offset,
eop->mem->offset, false);
}
if (eop->mem->address) {
compare_uint64_ret(op->mem.address,
eop->mem->address, false);
}
compare_tbool_ret(op->mem.in_disp_size,
eop->mem->in_disp_size, false);
compare_tbool_ret(op->mem.out_disp_size,

9126
tests/details/m68k.yaml
View file

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