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PPC LLVM 18 (#2540)

Browse source 
* Update PPC module to LLVM 18.

**New**

(According to LLVM changelog)

- Added DFP instruction.
- Added the SCV instruction.

**Changes**

- Memory decoder were simplified by decoding disponent and base reg separately.
- `DFORM` -> `DFORM_BASE`
- Use inverted `MCInstDesc` table.
- Replace the many declared printer in PPCInstPrinter with `static inlines`.
- Renamed groups to upper case.
- Switched to `ARCH_add_cs_detail_X()` function names.
- Remove `PPCInstPrinter.h` because it is no longer used.

* Fix: Use correct directory name.

* Fix segfaults and add asserts for these NULL cases.

* Allow to map a single LLVM option to multiple CS options

* Add default endian option to the MCUpdater

* Fix setter for Little endian

* Add SPE option to cstool

* Fix QPX instructions.

Due to 4b43ef3e5c
the names of the operands were matched.
Because FRT dosn't exist in the XForm_1 class,
the generated tables didn't decoded them.

* Fix: AbsAddr should be printed as unsigned.

* Fix S12 immediate printing for PC memory operands

* Fix MCUpdater tests

* Update PPCRegisterInfo_stripRegisterPrefix

* Add support for selection of Power versions

* Run clang-format

* Fix feature check

* Allow to overwrite in multi-mode

* Add some more flags

* Fix order and map name

* Add new test files.

* Fix checks for features.

Only enables PowerX feature checks of a Power architecture is enabled
and the feature is in the list of it.

* Print byte sequence with space between comma.

This helps with copy and search of the byte string in the test files.

* Fix tests broken due to feature toggles

* Shorten generated names.

* Update bindings
This commit is contained in:
Rot127 2024-12-05 11:26:33 +00:00 • committed by GitHub
parent e46838ed97
commit 93a104c009
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
69 changed files with 87378 additions and 40235 deletions
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1
CMakeLists.txt
View file

@ -323,7 +323,6 @@ if(CAPSTONE_PPC_SUPPORT)
)
set(HEADERS_PPC
arch/PowerPC/PPCInstrInfo.h
arch/PowerPC/PPCInstPrinter.h
arch/PowerPC/PPCLinkage.h
arch/PowerPC/PPCMapping.h
arch/PowerPC/PPCMCTargetDesc.h

5
Mapping.c
View file

@ -4,6 +4,7 @@
#include "Mapping.h"
#include "capstone/capstone.h"
#include "cs_priv.h"
#include "utils.h"
// create a cache for fast id lookup
@ -40,9 +41,13 @@ unsigned short insn_find(const insn_map *insns, unsigned int max,
// Returns the id or -1 if not found.
int name2id(const name_map *map, int max, const char *name)
{
CS_ASSERT_RET_VAL(map && name, -1);
int i;
for (i = 0; i < max; i++) {
if (!map[i].name) {
return -1;
}
if (!strcmp(map[i].name, name)) {
return map[i].id;
}

219
arch/PowerPC/PPCDisassembler.c
View file

@ -104,6 +104,14 @@ static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
return decodeRegisterClass(Inst, RegNo, FRegs);
}
static DecodeStatus DecodeFpRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
{
if (RegNo > 30 || (RegNo & 1))
return MCDisassembler_Fail;
return decodeRegisterClass(Inst, RegNo >> 1, FpRegs);
}
static DecodeStatus DecodeVFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
@ -257,29 +265,39 @@ static DecodeStatus DecodeQFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
N)(MCInst * Inst, uint64_t Imm, \
int64_t Address, const void *Decoder) \
{ \
if (!isUIntN(N, Imm)) \
return MCDisassembler_Fail; \
MCOperand_CreateImm0(Inst, (Imm)); \
return MCDisassembler_Success; \
}
DEFINE_decodeUImmOperand(5) DEFINE_decodeUImmOperand(16)
DEFINE_decodeUImmOperand(6) DEFINE_decodeUImmOperand(10)
DEFINE_decodeUImmOperand(8) DEFINE_decodeUImmOperand(7)
DEFINE_decodeUImmOperand(12)
DEFINE_decodeUImmOperand(1);
DEFINE_decodeUImmOperand(2);
DEFINE_decodeUImmOperand(3);
DEFINE_decodeUImmOperand(4);
DEFINE_decodeUImmOperand(5);
DEFINE_decodeUImmOperand(6);
DEFINE_decodeUImmOperand(7);
DEFINE_decodeUImmOperand(8);
DEFINE_decodeUImmOperand(10);
DEFINE_decodeUImmOperand(12);
DEFINE_decodeUImmOperand(16);
#define DEFINE_decodeSImmOperand(N) \
static DecodeStatus CONCAT(decodeSImmOperand, \
N)(MCInst * Inst, uint64_t Imm, \
int64_t Address, const void *Decoder) \
{ \
MCOperand_CreateImm0(Inst, (SignExtend64(Imm, N))); \
if (!isUIntN(N, Imm)) \
return MCDisassembler_Fail; \
MCOperand_CreateImm0(Inst, (SignExtend64((Imm), N))); \
return MCDisassembler_Success; \
}
DEFINE_decodeSImmOperand(16)
DEFINE_decodeSImmOperand(5)
DEFINE_decodeSImmOperand(34)
DEFINE_decodeSImmOperand(16);
DEFINE_decodeSImmOperand(5);
DEFINE_decodeSImmOperand(34);
static DecodeStatus
decodeImmZeroOperand(MCInst *Inst, uint64_t Imm, int64_t Address,
const void *Decoder)
static DecodeStatus decodeImmZeroOperand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
if (Imm != 0)
return MCDisassembler_Fail;
@ -297,158 +315,65 @@ static DecodeStatus decodeVSRpEvenOperands(MCInst *Inst, uint64_t RegNo,
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the memri field (imm, reg), which has the low 16-bits as the
// displacement and the next 5 bits as the register #.
uint64_t Base = Imm >> 16;
uint64_t Disp = Imm & 0xFFFF;
switch (MCInst_getOpcode(Inst)) {
default:
break;
case PPC_LBZU:
case PPC_LHAU:
case PPC_LHZU:
case PPC_LWZU:
case PPC_LFSU:
case PPC_LFDU:
// Add the tied output operand.
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
break;
case PPC_STBU:
case PPC_STHU:
case PPC_STWU:
case PPC_STFSU:
case PPC_STFDU:
MCInst_insert0(Inst, 0,
MCOperand_CreateReg1(Inst, RRegsNoR0[Base]));
break;
}
MCOperand_CreateImm0(Inst, (SignExtend64(Disp, 16)));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the memrix field (imm, reg), which has the low 14-bits as the
// displacement and the next 5 bits as the register #.
uint64_t Base = Imm >> 14;
uint64_t Disp = Imm & 0x3FFF;
if (MCInst_getOpcode(Inst) == PPC_LDU)
// Add the tied output operand.
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
else if (MCInst_getOpcode(Inst) == PPC_STDU)
MCInst_insert0(Inst, 0,
MCOperand_CreateReg1(Inst, RRegsNoR0[Base]));
MCOperand_CreateImm0(Inst, (SignExtend64(Disp << 2, 16)));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRIHashOperands(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
// Decode the memrix field for a hash store or hash check operation.
// The field is composed of a register and an immediate value that is 6 bits
// and covers the range -8 to -512. The immediate is always negative and 2s
// complement which is why we sign extend a 7 bit value.
const uint64_t Base = Imm >> 6;
const int64_t Disp = SignExtend64((Imm & 0x3F) + 64, 7) * 8;
MCOperand_CreateImm0(Inst, (Disp));
MCOperand_CreateReg0(Inst, (RRegs[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRIX16Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the memrix16 field (imm, reg), which has the low 12-bits as the
// displacement with 16-byte aligned, and the next 5 bits as the register #.
uint64_t Base = Imm >> 12;
uint64_t Disp = Imm & 0xFFF;
MCOperand_CreateImm0(Inst, (SignExtend64(Disp << 4, 16)));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeMemRI34PCRelOperands(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
// Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as
// the displacement, and the next 5 bits as an immediate 0.
uint64_t Base = Imm >> 34;
uint64_t Disp = Imm & 0x3FFFFFFFFUL;
MCOperand_CreateImm0(Inst, (SignExtend64(Disp, 34)));
return decodeImmZeroOperand(Inst, Base, Address, Decoder);
}
static DecodeStatus decodeMemRI34Operands(MCInst *Inst, uint64_t Imm,
static DecodeStatus decodeDispSPE8Operand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the memri34 field (imm, reg), which has the low 34-bits as the
// displacement, and the next 5 bits as the register #.
uint64_t Base = Imm >> 34;
uint64_t Disp = Imm & 0x3FFFFFFFFUL;
// Decode the dispSPE8 field, which has 5-bits, 8-byte aligned.
MCOperand_CreateImm0(Inst, (SignExtend64(Disp, 34)));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeSPE8Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the spe8disp field (imm, reg), which has the low 5-bits as the
// displacement with 8-byte aligned, and the next 5 bits as the register #.
uint64_t Base = Imm >> 5;
uint64_t Disp = Imm & 0x1F;
MCOperand_CreateImm0(Inst, (Disp << 3));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeSPE4Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
static DecodeStatus decodeDispSPE4Operand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the spe4disp field (imm, reg), which has the low 5-bits as the
// displacement with 4-byte aligned, and the next 5 bits as the register #.
// Decode the dispSPE8 field, which has 5-bits, 4-byte aligned.
uint64_t Base = Imm >> 5;
uint64_t Disp = Imm & 0x1F;
MCOperand_CreateImm0(Inst, (Disp << 2));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeSPE2Operands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
static DecodeStatus decodeDispSPE2Operand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the spe2disp field (imm, reg), which has the low 5-bits as the
// displacement with 2-byte aligned, and the next 5 bits as the register #.
// Decode the dispSPE8 field, which has 5-bits, 2-byte aligned.
uint64_t Base = Imm >> 5;
uint64_t Disp = Imm & 0x1F;
MCOperand_CreateImm0(Inst, (Disp << 1));
MCOperand_CreateReg0(Inst, (RRegsNoR0[Base]));
return MCDisassembler_Success;
}
static DecodeStatus decodeDispRIXOperand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// The rix displacement is an immediate shifted by 2
MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 2), 16)));
return MCDisassembler_Success;
}
static DecodeStatus decodeDispRIX16Operand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// The rix16 displacement has 12-bits which are shifted by 4.
MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 4), 16)));
return MCDisassembler_Success;
}
static DecodeStatus decodeDispRIHashOperand(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
// Decode the disp field for a hash store or hash check operation.
// The field is composed of an immediate value that is 6 bits
// and covers the range -8 to -512. The immediate is always negative and 2s
// complement which is why we sign extend a 7 bit value.
const int64_t Disp = SignExtend64(((Imm & 0x3F) + 64), 7) * 8;
MCOperand_CreateImm0(Inst, (Disp));
return MCDisassembler_Success;
}
@ -486,7 +411,7 @@ DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
uint32_t BaseInst = readBytes32(MI, Bytes + 4);
uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
DecodeStatus result =
decodeInstruction_4(DecoderTable64, MI, Inst, Address);
decodeInstruction_4(DecoderTable64, MI, Inst, Address, NULL);
if (result != MCDisassembler_Fail) {
*Size = 8;
return result;
@ -505,22 +430,22 @@ DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
if (PPC_getFeatureBits(MI->csh->mode, PPC_FeatureQPX)) {
DecodeStatus result = decodeInstruction_4(DecoderTableQPX32, MI,
Inst, Address);
Inst, Address, NULL);
if (result != MCDisassembler_Fail)
return result;
} else if (PPC_getFeatureBits(MI->csh->mode, PPC_FeatureSPE)) {
DecodeStatus result = decodeInstruction_4(DecoderTableSPE32, MI,
Inst, Address);
Inst, Address, NULL);
if (result != MCDisassembler_Fail)
return result;
} else if (PPC_getFeatureBits(MI->csh->mode, PPC_FeaturePS)) {
DecodeStatus result = decodeInstruction_4(DecoderTablePS32, MI,
Inst, Address);
Inst, Address, NULL);
if (result != MCDisassembler_Fail)
return result;
}
return decodeInstruction_4(DecoderTable32, MI, Inst, Address);
return decodeInstruction_4(DecoderTable32, MI, Inst, Address, NULL);
}
DecodeStatus PPC_LLVM_getInstruction(csh handle, const uint8_t *Bytes,

15208
arch/PowerPC/PPCGenAsmWriter.inc
View file

File diff suppressed because it is too large Load diff

523
arch/PowerPC/PPCGenCSAliasMnemMap.inc
View file

@ -1,6 +1,6 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
@ -102,6 +102,16 @@
{ PPC_INS_ALIAS_TENDALL_, "tendall." },
{ PPC_INS_ALIAS_TSUSPEND_, "tsuspend." },
{ PPC_INS_ALIAS_TRESUME_, "tresume." },
{ PPC_INS_ALIAS_WAIT, "wait" },
{ PPC_INS_ALIAS_WAITRSV, "waitrsv" },
{ PPC_INS_ALIAS_SYNC, "sync" },
{ PPC_INS_ALIAS_PTESYNC, "ptesync" },
{ PPC_INS_ALIAS_PHWSYNC, "phwsync" },
{ PPC_INS_ALIAS_PLWSYNC, "plwsync" },
{ PPC_INS_ALIAS_STNCISYNC, "stncisync" },
{ PPC_INS_ALIAS_STCISYNC, "stcisync" },
{ PPC_INS_ALIAS_STSYNC, "stsync" },
{ PPC_INS_ALIAS_PADDI, "paddi" },
{ PPC_INS_ALIAS_DCI, "dci" },
{ PPC_INS_ALIAS_DCCCI, "dccci" },
{ PPC_INS_ALIAS_ICI, "ici" },
@ -111,11 +121,7 @@
{ PPC_INS_ALIAS_MTFSF, "mtfsf" },
{ PPC_INS_ALIAS_MTFSF_, "mtfsf." },
{ PPC_INS_ALIAS_SC, "sc" },
{ PPC_INS_ALIAS_SYNC, "sync" },
{ PPC_INS_ALIAS_LWSYNC, "lwsync" },
{ PPC_INS_ALIAS_PTESYNC, "ptesync" },
{ PPC_INS_ALIAS_WAIT, "wait" },
{ PPC_INS_ALIAS_WAITRSV, "waitrsv" },
{ PPC_INS_ALIAS_WAITIMPL, "waitimpl" },
{ PPC_INS_ALIAS_MBAR, "mbar" },
{ PPC_INS_ALIAS_CRSET, "crset" },
@ -186,6 +192,9 @@
{ PPC_INS_ALIAS_TLBRELO, "tlbrelo" },
{ PPC_INS_ALIAS_TLBWEHI, "tlbwehi" },
{ PPC_INS_ALIAS_TLBWELO, "tlbwelo" },
{ PPC_INS_ALIAS_TLBILXLPID, "tlbilxlpid" },
{ PPC_INS_ALIAS_TLBILXPID, "tlbilxpid" },
{ PPC_INS_ALIAS_TLBILXVA, "tlbilxva" },
{ PPC_INS_ALIAS_ROTLDI, "rotldi" },
{ PPC_INS_ALIAS_ROTLDI_, "rotldi." },
{ PPC_INS_ALIAS_ROTLD, "rotld" },
@ -193,14 +202,14 @@
{ PPC_INS_ALIAS_CLRLDI, "clrldi" },
{ PPC_INS_ALIAS_CLRLDI_, "clrldi." },
{ PPC_INS_ALIAS_LNIA, "lnia" },
{ PPC_INS_ALIAS_BCp, "bc+" },
{ PPC_INS_ALIAS_BCAp, "bca+" },
{ PPC_INS_ALIAS_BCLp, "bcl+" },
{ PPC_INS_ALIAS_BCLAp, "bcla+" },
{ PPC_INS_ALIAS_BCm, "bc-" },
{ PPC_INS_ALIAS_BCAm, "bca-" },
{ PPC_INS_ALIAS_BCLm, "bcl-" },
{ PPC_INS_ALIAS_BCLAm, "bcla-" },
{ PPC_INS_ALIAS_BCp, "bcp" },
{ PPC_INS_ALIAS_BCAp, "bcap" },
{ PPC_INS_ALIAS_BCLp, "bclp" },
{ PPC_INS_ALIAS_BCLAp, "bclap" },
{ PPC_INS_ALIAS_BCm, "bcm" },
{ PPC_INS_ALIAS_BCAm, "bcam" },
{ PPC_INS_ALIAS_BCLm, "bclm" },
{ PPC_INS_ALIAS_BCLAm, "bclam" },
{ PPC_INS_ALIAS_BT, "bt" },
{ PPC_INS_ALIAS_BTA, "bta" },
{ PPC_INS_ALIAS_BTLR, "btlr" },
@ -217,28 +226,28 @@
{ PPC_INS_ALIAS_BDNZL, "bdnzl" },
{ PPC_INS_ALIAS_BDNZLA, "bdnzla" },
{ PPC_INS_ALIAS_BDNZ, "bdnz" },
{ PPC_INS_ALIAS_BDZLp, "bdzl+" },
{ PPC_INS_ALIAS_BDZLAp, "bdzla+" },
{ PPC_INS_ALIAS_BDZp, "bdz+" },
{ PPC_INS_ALIAS_BDNZLp, "bdnzl+" },
{ PPC_INS_ALIAS_BDNZLAp, "bdnzla+" },
{ PPC_INS_ALIAS_BDNZp, "bdnz+" },
{ PPC_INS_ALIAS_BDZLm, "bdzl-" },
{ PPC_INS_ALIAS_BDZLAm, "bdzla-" },
{ PPC_INS_ALIAS_BDZm, "bdz-" },
{ PPC_INS_ALIAS_BDNZLm, "bdnzl-" },
{ PPC_INS_ALIAS_BDNZLAm, "bdnzla-" },
{ PPC_INS_ALIAS_BDNZm, "bdnz-" },
{ PPC_INS_ALIAS_BDZLp, "bdzlp" },
{ PPC_INS_ALIAS_BDZLAp, "bdzlap" },
{ PPC_INS_ALIAS_BDZp, "bdzp" },
{ PPC_INS_ALIAS_BDNZLp, "bdnzlp" },
{ PPC_INS_ALIAS_BDNZLAp, "bdnzlap" },
{ PPC_INS_ALIAS_BDNZp, "bdnzp" },
{ PPC_INS_ALIAS_BDZLm, "bdzlm" },
{ PPC_INS_ALIAS_BDZLAm, "bdzlam" },
{ PPC_INS_ALIAS_BDZm, "bdzm" },
{ PPC_INS_ALIAS_BDNZLm, "bdnzlm" },
{ PPC_INS_ALIAS_BDNZLAm, "bdnzlam" },
{ PPC_INS_ALIAS_BDNZm, "bdnzm" },
{ PPC_INS_ALIAS_BDNZLR, "bdnzlr" },
{ PPC_INS_ALIAS_BDNZLRL, "bdnzlrl" },
{ PPC_INS_ALIAS_BDZLRp, "bdzlr+" },
{ PPC_INS_ALIAS_BDZLRLp, "bdzlrl+" },
{ PPC_INS_ALIAS_BDNZLRp, "bdnzlr+" },
{ PPC_INS_ALIAS_BDNZLRLp, "bdnzlrl+" },
{ PPC_INS_ALIAS_BDZLRm, "bdzlr-" },
{ PPC_INS_ALIAS_BDZLRLm, "bdzlrl-" },
{ PPC_INS_ALIAS_BDNZLRm, "bdnzlr-" },
{ PPC_INS_ALIAS_BDNZLRLm, "bdnzlrl-" },
{ PPC_INS_ALIAS_BDZLRp, "bdzlrp" },
{ PPC_INS_ALIAS_BDZLRLp, "bdzlrlp" },
{ PPC_INS_ALIAS_BDNZLRp, "bdnzlrp" },
{ PPC_INS_ALIAS_BDNZLRLp, "bdnzlrlp" },
{ PPC_INS_ALIAS_BDZLRm, "bdzlrm" },
{ PPC_INS_ALIAS_BDZLRLm, "bdzlrlm" },
{ PPC_INS_ALIAS_BDNZLRm, "bdnzlrm" },
{ PPC_INS_ALIAS_BDNZLRLm, "bdnzlrlm" },
{ PPC_INS_ALIAS_BF, "bf" },
{ PPC_INS_ALIAS_BFA, "bfa" },
{ PPC_INS_ALIAS_BFLR, "bflr" },
@ -247,38 +256,38 @@
{ PPC_INS_ALIAS_BFLRL, "bflrl" },
{ PPC_INS_ALIAS_BFCTR, "bfctr" },
{ PPC_INS_ALIAS_BFCTRL, "bfctrl" },
{ PPC_INS_ALIAS_BTm, "bt-" },
{ PPC_INS_ALIAS_BTAm, "bta-" },
{ PPC_INS_ALIAS_BTLRm, "btlr-" },
{ PPC_INS_ALIAS_BTLm, "btl-" },
{ PPC_INS_ALIAS_BTLAm, "btla-" },
{ PPC_INS_ALIAS_BTLRLm, "btlrl-" },
{ PPC_INS_ALIAS_BTCTRm, "btctr-" },
{ PPC_INS_ALIAS_BTCTRLm, "btctrl-" },
{ PPC_INS_ALIAS_BFm, "bf-" },
{ PPC_INS_ALIAS_BFAm, "bfa-" },
{ PPC_INS_ALIAS_BFLRm, "bflr-" },
{ PPC_INS_ALIAS_BFLm, "bfl-" },
{ PPC_INS_ALIAS_BFLAm, "bfla-" },
{ PPC_INS_ALIAS_BFLRLm, "bflrl-" },
{ PPC_INS_ALIAS_BFCTRm, "bfctr-" },
{ PPC_INS_ALIAS_BFCTRLm, "bfctrl-" },
{ PPC_INS_ALIAS_BTp, "bt+" },
{ PPC_INS_ALIAS_BTAp, "bta+" },
{ PPC_INS_ALIAS_BTLRp, "btlr+" },
{ PPC_INS_ALIAS_BTLp, "btl+" },
{ PPC_INS_ALIAS_BTLAp, "btla+" },
{ PPC_INS_ALIAS_BTLRLp, "btlrl+" },
{ PPC_INS_ALIAS_BTCTRp, "btctr+" },
{ PPC_INS_ALIAS_BTCTRLp, "btctrl+" },
{ PPC_INS_ALIAS_BFp, "bf+" },
{ PPC_INS_ALIAS_BFAp, "bfa+" },
{ PPC_INS_ALIAS_BFLRp, "bflr+" },
{ PPC_INS_ALIAS_BFLp, "bfl+" },
{ PPC_INS_ALIAS_BFLAp, "bfla+" },
{ PPC_INS_ALIAS_BFLRLp, "bflrl+" },
{ PPC_INS_ALIAS_BFCTRp, "bfctr+" },
{ PPC_INS_ALIAS_BFCTRLp, "bfctrl+" },
{ PPC_INS_ALIAS_BTm, "btm" },
{ PPC_INS_ALIAS_BTAm, "btam" },
{ PPC_INS_ALIAS_BTLRm, "btlrm" },
{ PPC_INS_ALIAS_BTLm, "btlm" },
{ PPC_INS_ALIAS_BTLAm, "btlam" },
{ PPC_INS_ALIAS_BTLRLm, "btlrlm" },
{ PPC_INS_ALIAS_BTCTRm, "btctrm" },
{ PPC_INS_ALIAS_BTCTRLm, "btctrlm" },
{ PPC_INS_ALIAS_BFm, "bfm" },
{ PPC_INS_ALIAS_BFAm, "bfam" },
{ PPC_INS_ALIAS_BFLRm, "bflrm" },
{ PPC_INS_ALIAS_BFLm, "bflm" },
{ PPC_INS_ALIAS_BFLAm, "bflam" },
{ PPC_INS_ALIAS_BFLRLm, "bflrlm" },
{ PPC_INS_ALIAS_BFCTRm, "bfctrm" },
{ PPC_INS_ALIAS_BFCTRLm, "bfctrlm" },
{ PPC_INS_ALIAS_BTp, "btp" },
{ PPC_INS_ALIAS_BTAp, "btap" },
{ PPC_INS_ALIAS_BTLRp, "btlrp" },
{ PPC_INS_ALIAS_BTLp, "btlp" },
{ PPC_INS_ALIAS_BTLAp, "btlap" },
{ PPC_INS_ALIAS_BTLRLp, "btlrlp" },
{ PPC_INS_ALIAS_BTCTRp, "btctrp" },
{ PPC_INS_ALIAS_BTCTRLp, "btctrlp" },
{ PPC_INS_ALIAS_BFp, "bfp" },
{ PPC_INS_ALIAS_BFAp, "bfap" },
{ PPC_INS_ALIAS_BFLRp, "bflrp" },
{ PPC_INS_ALIAS_BFLp, "bflp" },
{ PPC_INS_ALIAS_BFLAp, "bflap" },
{ PPC_INS_ALIAS_BFLRLp, "bflrlp" },
{ PPC_INS_ALIAS_BFCTRp, "bfctrp" },
{ PPC_INS_ALIAS_BFCTRLp, "bfctrlp" },
{ PPC_INS_ALIAS_BDNZT, "bdnzt" },
{ PPC_INS_ALIAS_BDNZTA, "bdnzta" },
{ PPC_INS_ALIAS_BDNZTLR, "bdnztlr" },
@ -319,22 +328,22 @@
{ PPC_INS_ALIAS_BLTLA, "bltla" },
{ PPC_INS_ALIAS_BLTLRL, "bltlrl" },
{ PPC_INS_ALIAS_BLTCTRL, "bltctrl" },
{ PPC_INS_ALIAS_BLTm, "blt-" },
{ PPC_INS_ALIAS_BLTAm, "blta-" },
{ PPC_INS_ALIAS_BLTLRm, "bltlr-" },
{ PPC_INS_ALIAS_BLTCTRm, "bltctr-" },
{ PPC_INS_ALIAS_BLTLm, "bltl-" },
{ PPC_INS_ALIAS_BLTLAm, "bltla-" },
{ PPC_INS_ALIAS_BLTLRLm, "bltlrl-" },
{ PPC_INS_ALIAS_BLTCTRLm, "bltctrl-" },
{ PPC_INS_ALIAS_BLTp, "blt+" },
{ PPC_INS_ALIAS_BLTAp, "blta+" },
{ PPC_INS_ALIAS_BLTLRp, "bltlr+" },
{ PPC_INS_ALIAS_BLTCTRp, "bltctr+" },
{ PPC_INS_ALIAS_BLTLp, "bltl+" },
{ PPC_INS_ALIAS_BLTLAp, "bltla+" },
{ PPC_INS_ALIAS_BLTLRLp, "bltlrl+" },
{ PPC_INS_ALIAS_BLTCTRLp, "bltctrl+" },
{ PPC_INS_ALIAS_BLTm, "bltm" },
{ PPC_INS_ALIAS_BLTAm, "bltam" },
{ PPC_INS_ALIAS_BLTLRm, "bltlrm" },
{ PPC_INS_ALIAS_BLTCTRm, "bltctrm" },
{ PPC_INS_ALIAS_BLTLm, "bltlm" },
{ PPC_INS_ALIAS_BLTLAm, "bltlam" },
{ PPC_INS_ALIAS_BLTLRLm, "bltlrlm" },
{ PPC_INS_ALIAS_BLTCTRLm, "bltctrlm" },
{ PPC_INS_ALIAS_BLTp, "bltp" },
{ PPC_INS_ALIAS_BLTAp, "bltap" },
{ PPC_INS_ALIAS_BLTLRp, "bltlrp" },
{ PPC_INS_ALIAS_BLTCTRp, "bltctrp" },
{ PPC_INS_ALIAS_BLTLp, "bltlp" },
{ PPC_INS_ALIAS_BLTLAp, "bltlap" },
{ PPC_INS_ALIAS_BLTLRLp, "bltlrlp" },
{ PPC_INS_ALIAS_BLTCTRLp, "bltctrlp" },
{ PPC_INS_ALIAS_BGT, "bgt" },
{ PPC_INS_ALIAS_BGTA, "bgta" },
{ PPC_INS_ALIAS_BGTLR, "bgtlr" },
@ -343,22 +352,22 @@
{ PPC_INS_ALIAS_BGTLA, "bgtla" },
{ PPC_INS_ALIAS_BGTLRL, "bgtlrl" },
{ PPC_INS_ALIAS_BGTCTRL, "bgtctrl" },
{ PPC_INS_ALIAS_BGTm, "bgt-" },
{ PPC_INS_ALIAS_BGTAm, "bgta-" },
{ PPC_INS_ALIAS_BGTLRm, "bgtlr-" },
{ PPC_INS_ALIAS_BGTCTRm, "bgtctr-" },
{ PPC_INS_ALIAS_BGTLm, "bgtl-" },
{ PPC_INS_ALIAS_BGTLAm, "bgtla-" },
{ PPC_INS_ALIAS_BGTLRLm, "bgtlrl-" },
{ PPC_INS_ALIAS_BGTCTRLm, "bgtctrl-" },
{ PPC_INS_ALIAS_BGTp, "bgt+" },
{ PPC_INS_ALIAS_BGTAp, "bgta+" },
{ PPC_INS_ALIAS_BGTLRp, "bgtlr+" },
{ PPC_INS_ALIAS_BGTCTRp, "bgtctr+" },
{ PPC_INS_ALIAS_BGTLp, "bgtl+" },
{ PPC_INS_ALIAS_BGTLAp, "bgtla+" },
{ PPC_INS_ALIAS_BGTLRLp, "bgtlrl+" },
{ PPC_INS_ALIAS_BGTCTRLp, "bgtctrl+" },
{ PPC_INS_ALIAS_BGTm, "bgtm" },
{ PPC_INS_ALIAS_BGTAm, "bgtam" },
{ PPC_INS_ALIAS_BGTLRm, "bgtlrm" },
{ PPC_INS_ALIAS_BGTCTRm, "bgtctrm" },
{ PPC_INS_ALIAS_BGTLm, "bgtlm" },
{ PPC_INS_ALIAS_BGTLAm, "bgtlam" },
{ PPC_INS_ALIAS_BGTLRLm, "bgtlrlm" },
{ PPC_INS_ALIAS_BGTCTRLm, "bgtctrlm" },
{ PPC_INS_ALIAS_BGTp, "bgtp" },
{ PPC_INS_ALIAS_BGTAp, "bgtap" },
{ PPC_INS_ALIAS_BGTLRp, "bgtlrp" },
{ PPC_INS_ALIAS_BGTCTRp, "bgtctrp" },
{ PPC_INS_ALIAS_BGTLp, "bgtlp" },
{ PPC_INS_ALIAS_BGTLAp, "bgtlap" },
{ PPC_INS_ALIAS_BGTLRLp, "bgtlrlp" },
{ PPC_INS_ALIAS_BGTCTRLp, "bgtctrlp" },
{ PPC_INS_ALIAS_BEQ, "beq" },
{ PPC_INS_ALIAS_BEQA, "beqa" },
{ PPC_INS_ALIAS_BEQLR, "beqlr" },
@ -367,22 +376,22 @@
{ PPC_INS_ALIAS_BEQLA, "beqla" },
{ PPC_INS_ALIAS_BEQLRL, "beqlrl" },
{ PPC_INS_ALIAS_BEQCTRL, "beqctrl" },
{ PPC_INS_ALIAS_BEQm, "beq-" },
{ PPC_INS_ALIAS_BEQAm, "beqa-" },
{ PPC_INS_ALIAS_BEQLRm, "beqlr-" },
{ PPC_INS_ALIAS_BEQCTRm, "beqctr-" },
{ PPC_INS_ALIAS_BEQLm, "beql-" },
{ PPC_INS_ALIAS_BEQLAm, "beqla-" },
{ PPC_INS_ALIAS_BEQLRLm, "beqlrl-" },
{ PPC_INS_ALIAS_BEQCTRLm, "beqctrl-" },
{ PPC_INS_ALIAS_BEQp, "beq+" },
{ PPC_INS_ALIAS_BEQAp, "beqa+" },
{ PPC_INS_ALIAS_BEQLRp, "beqlr+" },
{ PPC_INS_ALIAS_BEQCTRp, "beqctr+" },
{ PPC_INS_ALIAS_BEQLp, "beql+" },
{ PPC_INS_ALIAS_BEQLAp, "beqla+" },
{ PPC_INS_ALIAS_BEQLRLp, "beqlrl+" },
{ PPC_INS_ALIAS_BEQCTRLp, "beqctrl+" },
{ PPC_INS_ALIAS_BEQm, "beqm" },
{ PPC_INS_ALIAS_BEQAm, "beqam" },
{ PPC_INS_ALIAS_BEQLRm, "beqlrm" },
{ PPC_INS_ALIAS_BEQCTRm, "beqctrm" },
{ PPC_INS_ALIAS_BEQLm, "beqlm" },
{ PPC_INS_ALIAS_BEQLAm, "beqlam" },
{ PPC_INS_ALIAS_BEQLRLm, "beqlrlm" },
{ PPC_INS_ALIAS_BEQCTRLm, "beqctrlm" },
{ PPC_INS_ALIAS_BEQp, "beqp" },
{ PPC_INS_ALIAS_BEQAp, "beqap" },
{ PPC_INS_ALIAS_BEQLRp, "beqlrp" },
{ PPC_INS_ALIAS_BEQCTRp, "beqctrp" },
{ PPC_INS_ALIAS_BEQLp, "beqlp" },
{ PPC_INS_ALIAS_BEQLAp, "beqlap" },
{ PPC_INS_ALIAS_BEQLRLp, "beqlrlp" },
{ PPC_INS_ALIAS_BEQCTRLp, "beqctrlp" },
{ PPC_INS_ALIAS_BUN, "bun" },
{ PPC_INS_ALIAS_BUNA, "buna" },
{ PPC_INS_ALIAS_BUNLR, "bunlr" },
@ -391,22 +400,22 @@
{ PPC_INS_ALIAS_BUNLA, "bunla" },
{ PPC_INS_ALIAS_BUNLRL, "bunlrl" },
{ PPC_INS_ALIAS_BUNCTRL, "bunctrl" },
{ PPC_INS_ALIAS_BUNm, "bun-" },
{ PPC_INS_ALIAS_BUNAm, "buna-" },
{ PPC_INS_ALIAS_BUNLRm, "bunlr-" },
{ PPC_INS_ALIAS_BUNCTRm, "bunctr-" },
{ PPC_INS_ALIAS_BUNLm, "bunl-" },
{ PPC_INS_ALIAS_BUNLAm, "bunla-" },
{ PPC_INS_ALIAS_BUNLRLm, "bunlrl-" },
{ PPC_INS_ALIAS_BUNCTRLm, "bunctrl-" },
{ PPC_INS_ALIAS_BUNp, "bun+" },
{ PPC_INS_ALIAS_BUNAp, "buna+" },
{ PPC_INS_ALIAS_BUNLRp, "bunlr+" },
{ PPC_INS_ALIAS_BUNCTRp, "bunctr+" },
{ PPC_INS_ALIAS_BUNLp, "bunl+" },
{ PPC_INS_ALIAS_BUNLAp, "bunla+" },
{ PPC_INS_ALIAS_BUNLRLp, "bunlrl+" },
{ PPC_INS_ALIAS_BUNCTRLp, "bunctrl+" },
{ PPC_INS_ALIAS_BUNm, "bunm" },
{ PPC_INS_ALIAS_BUNAm, "bunam" },
{ PPC_INS_ALIAS_BUNLRm, "bunlrm" },
{ PPC_INS_ALIAS_BUNCTRm, "bunctrm" },
{ PPC_INS_ALIAS_BUNLm, "bunlm" },
{ PPC_INS_ALIAS_BUNLAm, "bunlam" },
{ PPC_INS_ALIAS_BUNLRLm, "bunlrlm" },
{ PPC_INS_ALIAS_BUNCTRLm, "bunctrlm" },
{ PPC_INS_ALIAS_BUNp, "bunp" },
{ PPC_INS_ALIAS_BUNAp, "bunap" },
{ PPC_INS_ALIAS_BUNLRp, "bunlrp" },
{ PPC_INS_ALIAS_BUNCTRp, "bunctrp" },
{ PPC_INS_ALIAS_BUNLp, "bunlp" },
{ PPC_INS_ALIAS_BUNLAp, "bunlap" },
{ PPC_INS_ALIAS_BUNLRLp, "bunlrlp" },
{ PPC_INS_ALIAS_BUNCTRLp, "bunctrlp" },
{ PPC_INS_ALIAS_BSO, "bso" },
{ PPC_INS_ALIAS_BSOA, "bsoa" },
{ PPC_INS_ALIAS_BSOLR, "bsolr" },
@ -415,22 +424,22 @@
{ PPC_INS_ALIAS_BSOLA, "bsola" },
{ PPC_INS_ALIAS_BSOLRL, "bsolrl" },
{ PPC_INS_ALIAS_BSOCTRL, "bsoctrl" },
{ PPC_INS_ALIAS_BSOm, "bso-" },
{ PPC_INS_ALIAS_BSOAm, "bsoa-" },
{ PPC_INS_ALIAS_BSOLRm, "bsolr-" },
{ PPC_INS_ALIAS_BSOCTRm, "bsoctr-" },
{ PPC_INS_ALIAS_BSOLm, "bsol-" },
{ PPC_INS_ALIAS_BSOLAm, "bsola-" },
{ PPC_INS_ALIAS_BSOLRLm, "bsolrl-" },
{ PPC_INS_ALIAS_BSOCTRLm, "bsoctrl-" },
{ PPC_INS_ALIAS_BSOp, "bso+" },
{ PPC_INS_ALIAS_BSOAp, "bsoa+" },
{ PPC_INS_ALIAS_BSOLRp, "bsolr+" },
{ PPC_INS_ALIAS_BSOCTRp, "bsoctr+" },
{ PPC_INS_ALIAS_BSOLp, "bsol+" },
{ PPC_INS_ALIAS_BSOLAp, "bsola+" },
{ PPC_INS_ALIAS_BSOLRLp, "bsolrl+" },
{ PPC_INS_ALIAS_BSOCTRLp, "bsoctrl+" },
{ PPC_INS_ALIAS_BSOm, "bsom" },
{ PPC_INS_ALIAS_BSOAm, "bsoam" },
{ PPC_INS_ALIAS_BSOLRm, "bsolrm" },
{ PPC_INS_ALIAS_BSOCTRm, "bsoctrm" },
{ PPC_INS_ALIAS_BSOLm, "bsolm" },
{ PPC_INS_ALIAS_BSOLAm, "bsolam" },
{ PPC_INS_ALIAS_BSOLRLm, "bsolrlm" },
{ PPC_INS_ALIAS_BSOCTRLm, "bsoctrlm" },
{ PPC_INS_ALIAS_BSOp, "bsop" },
{ PPC_INS_ALIAS_BSOAp, "bsoap" },
{ PPC_INS_ALIAS_BSOLRp, "bsolrp" },
{ PPC_INS_ALIAS_BSOCTRp, "bsoctrp" },
{ PPC_INS_ALIAS_BSOLp, "bsolp" },
{ PPC_INS_ALIAS_BSOLAp, "bsolap" },
{ PPC_INS_ALIAS_BSOLRLp, "bsolrlp" },
{ PPC_INS_ALIAS_BSOCTRLp, "bsoctrlp" },
{ PPC_INS_ALIAS_BGE, "bge" },
{ PPC_INS_ALIAS_BGEA, "bgea" },
{ PPC_INS_ALIAS_BGELR, "bgelr" },
@ -439,22 +448,22 @@
{ PPC_INS_ALIAS_BGELA, "bgela" },
{ PPC_INS_ALIAS_BGELRL, "bgelrl" },
{ PPC_INS_ALIAS_BGECTRL, "bgectrl" },
{ PPC_INS_ALIAS_BGEm, "bge-" },
{ PPC_INS_ALIAS_BGEAm, "bgea-" },
{ PPC_INS_ALIAS_BGELRm, "bgelr-" },
{ PPC_INS_ALIAS_BGECTRm, "bgectr-" },
{ PPC_INS_ALIAS_BGELm, "bgel-" },
{ PPC_INS_ALIAS_BGELAm, "bgela-" },
{ PPC_INS_ALIAS_BGELRLm, "bgelrl-" },
{ PPC_INS_ALIAS_BGECTRLm, "bgectrl-" },
{ PPC_INS_ALIAS_BGEp, "bge+" },
{ PPC_INS_ALIAS_BGEAp, "bgea+" },
{ PPC_INS_ALIAS_BGELRp, "bgelr+" },
{ PPC_INS_ALIAS_BGECTRp, "bgectr+" },
{ PPC_INS_ALIAS_BGELp, "bgel+" },
{ PPC_INS_ALIAS_BGELAp, "bgela+" },
{ PPC_INS_ALIAS_BGELRLp, "bgelrl+" },
{ PPC_INS_ALIAS_BGECTRLp, "bgectrl+" },
{ PPC_INS_ALIAS_BGEm, "bgem" },
{ PPC_INS_ALIAS_BGEAm, "bgeam" },
{ PPC_INS_ALIAS_BGELRm, "bgelrm" },
{ PPC_INS_ALIAS_BGECTRm, "bgectrm" },
{ PPC_INS_ALIAS_BGELm, "bgelm" },
{ PPC_INS_ALIAS_BGELAm, "bgelam" },
{ PPC_INS_ALIAS_BGELRLm, "bgelrlm" },
{ PPC_INS_ALIAS_BGECTRLm, "bgectrlm" },
{ PPC_INS_ALIAS_BGEp, "bgep" },
{ PPC_INS_ALIAS_BGEAp, "bgeap" },
{ PPC_INS_ALIAS_BGELRp, "bgelrp" },
{ PPC_INS_ALIAS_BGECTRp, "bgectrp" },
{ PPC_INS_ALIAS_BGELp, "bgelp" },
{ PPC_INS_ALIAS_BGELAp, "bgelap" },
{ PPC_INS_ALIAS_BGELRLp, "bgelrlp" },
{ PPC_INS_ALIAS_BGECTRLp, "bgectrlp" },
{ PPC_INS_ALIAS_BNL, "bnl" },
{ PPC_INS_ALIAS_BNLA, "bnla" },
{ PPC_INS_ALIAS_BNLLR, "bnllr" },
@ -463,22 +472,22 @@
{ PPC_INS_ALIAS_BNLLA, "bnlla" },
{ PPC_INS_ALIAS_BNLLRL, "bnllrl" },
{ PPC_INS_ALIAS_BNLCTRL, "bnlctrl" },
{ PPC_INS_ALIAS_BNLm, "bnl-" },
{ PPC_INS_ALIAS_BNLAm, "bnla-" },
{ PPC_INS_ALIAS_BNLLRm, "bnllr-" },
{ PPC_INS_ALIAS_BNLCTRm, "bnlctr-" },
{ PPC_INS_ALIAS_BNLLm, "bnll-" },
{ PPC_INS_ALIAS_BNLLAm, "bnlla-" },
{ PPC_INS_ALIAS_BNLLRLm, "bnllrl-" },
{ PPC_INS_ALIAS_BNLCTRLm, "bnlctrl-" },
{ PPC_INS_ALIAS_BNLp, "bnl+" },
{ PPC_INS_ALIAS_BNLAp, "bnla+" },
{ PPC_INS_ALIAS_BNLLRp, "bnllr+" },
{ PPC_INS_ALIAS_BNLCTRp, "bnlctr+" },
{ PPC_INS_ALIAS_BNLLp, "bnll+" },
{ PPC_INS_ALIAS_BNLLAp, "bnlla+" },
{ PPC_INS_ALIAS_BNLLRLp, "bnllrl+" },
{ PPC_INS_ALIAS_BNLCTRLp, "bnlctrl+" },
{ PPC_INS_ALIAS_BNLm, "bnlm" },
{ PPC_INS_ALIAS_BNLAm, "bnlam" },
{ PPC_INS_ALIAS_BNLLRm, "bnllrm" },
{ PPC_INS_ALIAS_BNLCTRm, "bnlctrm" },
{ PPC_INS_ALIAS_BNLLm, "bnllm" },
{ PPC_INS_ALIAS_BNLLAm, "bnllam" },
{ PPC_INS_ALIAS_BNLLRLm, "bnllrlm" },
{ PPC_INS_ALIAS_BNLCTRLm, "bnlctrlm" },
{ PPC_INS_ALIAS_BNLp, "bnlp" },
{ PPC_INS_ALIAS_BNLAp, "bnlap" },
{ PPC_INS_ALIAS_BNLLRp, "bnllrp" },
{ PPC_INS_ALIAS_BNLCTRp, "bnlctrp" },
{ PPC_INS_ALIAS_BNLLp, "bnllp" },
{ PPC_INS_ALIAS_BNLLAp, "bnllap" },
{ PPC_INS_ALIAS_BNLLRLp, "bnllrlp" },
{ PPC_INS_ALIAS_BNLCTRLp, "bnlctrlp" },
{ PPC_INS_ALIAS_BLE, "ble" },
{ PPC_INS_ALIAS_BLEA, "blea" },
{ PPC_INS_ALIAS_BLELR, "blelr" },
@ -487,22 +496,22 @@
{ PPC_INS_ALIAS_BLELA, "blela" },
{ PPC_INS_ALIAS_BLELRL, "blelrl" },
{ PPC_INS_ALIAS_BLECTRL, "blectrl" },
{ PPC_INS_ALIAS_BLEm, "ble-" },
{ PPC_INS_ALIAS_BLEAm, "blea-" },
{ PPC_INS_ALIAS_BLELRm, "blelr-" },
{ PPC_INS_ALIAS_BLECTRm, "blectr-" },
{ PPC_INS_ALIAS_BLELm, "blel-" },
{ PPC_INS_ALIAS_BLELAm, "blela-" },
{ PPC_INS_ALIAS_BLELRLm, "blelrl-" },
{ PPC_INS_ALIAS_BLECTRLm, "blectrl-" },
{ PPC_INS_ALIAS_BLEp, "ble+" },
{ PPC_INS_ALIAS_BLEAp, "blea+" },
{ PPC_INS_ALIAS_BLELRp, "blelr+" },
{ PPC_INS_ALIAS_BLECTRp, "blectr+" },
{ PPC_INS_ALIAS_BLELp, "blel+" },
{ PPC_INS_ALIAS_BLELAp, "blela+" },
{ PPC_INS_ALIAS_BLELRLp, "blelrl+" },
{ PPC_INS_ALIAS_BLECTRLp, "blectrl+" },
{ PPC_INS_ALIAS_BLEm, "blem" },
{ PPC_INS_ALIAS_BLEAm, "bleam" },
{ PPC_INS_ALIAS_BLELRm, "blelrm" },
{ PPC_INS_ALIAS_BLECTRm, "blectrm" },
{ PPC_INS_ALIAS_BLELm, "blelm" },
{ PPC_INS_ALIAS_BLELAm, "blelam" },
{ PPC_INS_ALIAS_BLELRLm, "blelrlm" },
{ PPC_INS_ALIAS_BLECTRLm, "blectrlm" },
{ PPC_INS_ALIAS_BLEp, "blep" },
{ PPC_INS_ALIAS_BLEAp, "bleap" },
{ PPC_INS_ALIAS_BLELRp, "blelrp" },
{ PPC_INS_ALIAS_BLECTRp, "blectrp" },
{ PPC_INS_ALIAS_BLELp, "blelp" },
{ PPC_INS_ALIAS_BLELAp, "blelap" },
{ PPC_INS_ALIAS_BLELRLp, "blelrlp" },
{ PPC_INS_ALIAS_BLECTRLp, "blectrlp" },
{ PPC_INS_ALIAS_BNG, "bng" },
{ PPC_INS_ALIAS_BNGA, "bnga" },
{ PPC_INS_ALIAS_BNGLR, "bnglr" },
@ -511,22 +520,22 @@
{ PPC_INS_ALIAS_BNGLA, "bngla" },
{ PPC_INS_ALIAS_BNGLRL, "bnglrl" },
{ PPC_INS_ALIAS_BNGCTRL, "bngctrl" },
{ PPC_INS_ALIAS_BNGm, "bng-" },
{ PPC_INS_ALIAS_BNGAm, "bnga-" },
{ PPC_INS_ALIAS_BNGLRm, "bnglr-" },
{ PPC_INS_ALIAS_BNGCTRm, "bngctr-" },
{ PPC_INS_ALIAS_BNGLm, "bngl-" },
{ PPC_INS_ALIAS_BNGLAm, "bngla-" },
{ PPC_INS_ALIAS_BNGLRLm, "bnglrl-" },
{ PPC_INS_ALIAS_BNGCTRLm, "bngctrl-" },
{ PPC_INS_ALIAS_BNGp, "bng+" },
{ PPC_INS_ALIAS_BNGAp, "bnga+" },
{ PPC_INS_ALIAS_BNGLRp, "bnglr+" },
{ PPC_INS_ALIAS_BNGCTRp, "bngctr+" },
{ PPC_INS_ALIAS_BNGLp, "bngl+" },
{ PPC_INS_ALIAS_BNGLAp, "bngla+" },
{ PPC_INS_ALIAS_BNGLRLp, "bnglrl+" },
{ PPC_INS_ALIAS_BNGCTRLp, "bngctrl+" },
{ PPC_INS_ALIAS_BNGm, "bngm" },
{ PPC_INS_ALIAS_BNGAm, "bngam" },
{ PPC_INS_ALIAS_BNGLRm, "bnglrm" },
{ PPC_INS_ALIAS_BNGCTRm, "bngctrm" },
{ PPC_INS_ALIAS_BNGLm, "bnglm" },
{ PPC_INS_ALIAS_BNGLAm, "bnglam" },
{ PPC_INS_ALIAS_BNGLRLm, "bnglrlm" },
{ PPC_INS_ALIAS_BNGCTRLm, "bngctrlm" },
{ PPC_INS_ALIAS_BNGp, "bngp" },
{ PPC_INS_ALIAS_BNGAp, "bngap" },
{ PPC_INS_ALIAS_BNGLRp, "bnglrp" },
{ PPC_INS_ALIAS_BNGCTRp, "bngctrp" },
{ PPC_INS_ALIAS_BNGLp, "bnglp" },
{ PPC_INS_ALIAS_BNGLAp, "bnglap" },
{ PPC_INS_ALIAS_BNGLRLp, "bnglrlp" },
{ PPC_INS_ALIAS_BNGCTRLp, "bngctrlp" },
{ PPC_INS_ALIAS_BNE, "bne" },
{ PPC_INS_ALIAS_BNEA, "bnea" },
{ PPC_INS_ALIAS_BNELR, "bnelr" },
@ -535,22 +544,22 @@
{ PPC_INS_ALIAS_BNELA, "bnela" },
{ PPC_INS_ALIAS_BNELRL, "bnelrl" },
{ PPC_INS_ALIAS_BNECTRL, "bnectrl" },
{ PPC_INS_ALIAS_BNEm, "bne-" },
{ PPC_INS_ALIAS_BNEAm, "bnea-" },
{ PPC_INS_ALIAS_BNELRm, "bnelr-" },
{ PPC_INS_ALIAS_BNECTRm, "bnectr-" },
{ PPC_INS_ALIAS_BNELm, "bnel-" },
{ PPC_INS_ALIAS_BNELAm, "bnela-" },
{ PPC_INS_ALIAS_BNELRLm, "bnelrl-" },
{ PPC_INS_ALIAS_BNECTRLm, "bnectrl-" },
{ PPC_INS_ALIAS_BNEp, "bne+" },
{ PPC_INS_ALIAS_BNEAp, "bnea+" },
{ PPC_INS_ALIAS_BNELRp, "bnelr+" },
{ PPC_INS_ALIAS_BNECTRp, "bnectr+" },
{ PPC_INS_ALIAS_BNELp, "bnel+" },
{ PPC_INS_ALIAS_BNELAp, "bnela+" },
{ PPC_INS_ALIAS_BNELRLp, "bnelrl+" },
{ PPC_INS_ALIAS_BNECTRLp, "bnectrl+" },
{ PPC_INS_ALIAS_BNEm, "bnem" },
{ PPC_INS_ALIAS_BNEAm, "bneam" },
{ PPC_INS_ALIAS_BNELRm, "bnelrm" },
{ PPC_INS_ALIAS_BNECTRm, "bnectrm" },
{ PPC_INS_ALIAS_BNELm, "bnelm" },
{ PPC_INS_ALIAS_BNELAm, "bnelam" },
{ PPC_INS_ALIAS_BNELRLm, "bnelrlm" },
{ PPC_INS_ALIAS_BNECTRLm, "bnectrlm" },
{ PPC_INS_ALIAS_BNEp, "bnep" },
{ PPC_INS_ALIAS_BNEAp, "bneap" },
{ PPC_INS_ALIAS_BNELRp, "bnelrp" },
{ PPC_INS_ALIAS_BNECTRp, "bnectrp" },
{ PPC_INS_ALIAS_BNELp, "bnelp" },
{ PPC_INS_ALIAS_BNELAp, "bnelap" },
{ PPC_INS_ALIAS_BNELRLp, "bnelrlp" },
{ PPC_INS_ALIAS_BNECTRLp, "bnectrlp" },
{ PPC_INS_ALIAS_BNU, "bnu" },
{ PPC_INS_ALIAS_BNUA, "bnua" },
{ PPC_INS_ALIAS_BNULR, "bnulr" },
@ -559,22 +568,22 @@
{ PPC_INS_ALIAS_BNULA, "bnula" },
{ PPC_INS_ALIAS_BNULRL, "bnulrl" },
{ PPC_INS_ALIAS_BNUCTRL, "bnuctrl" },
{ PPC_INS_ALIAS_BNUm, "bnu-" },
{ PPC_INS_ALIAS_BNUAm, "bnua-" },
{ PPC_INS_ALIAS_BNULRm, "bnulr-" },
{ PPC_INS_ALIAS_BNUCTRm, "bnuctr-" },
{ PPC_INS_ALIAS_BNULm, "bnul-" },
{ PPC_INS_ALIAS_BNULAm, "bnula-" },
{ PPC_INS_ALIAS_BNULRLm, "bnulrl-" },
{ PPC_INS_ALIAS_BNUCTRLm, "bnuctrl-" },
{ PPC_INS_ALIAS_BNUp, "bnu+" },
{ PPC_INS_ALIAS_BNUAp, "bnua+" },
{ PPC_INS_ALIAS_BNULRp, "bnulr+" },
{ PPC_INS_ALIAS_BNUCTRp, "bnuctr+" },
{ PPC_INS_ALIAS_BNULp, "bnul+" },
{ PPC_INS_ALIAS_BNULAp, "bnula+" },
{ PPC_INS_ALIAS_BNULRLp, "bnulrl+" },
{ PPC_INS_ALIAS_BNUCTRLp, "bnuctrl+" },
{ PPC_INS_ALIAS_BNUm, "bnum" },
{ PPC_INS_ALIAS_BNUAm, "bnuam" },
{ PPC_INS_ALIAS_BNULRm, "bnulrm" },
{ PPC_INS_ALIAS_BNUCTRm, "bnuctrm" },
{ PPC_INS_ALIAS_BNULm, "bnulm" },
{ PPC_INS_ALIAS_BNULAm, "bnulam" },
{ PPC_INS_ALIAS_BNULRLm, "bnulrlm" },
{ PPC_INS_ALIAS_BNUCTRLm, "bnuctrlm" },
{ PPC_INS_ALIAS_BNUp, "bnup" },
{ PPC_INS_ALIAS_BNUAp, "bnuap" },
{ PPC_INS_ALIAS_BNULRp, "bnulrp" },
{ PPC_INS_ALIAS_BNUCTRp, "bnuctrp" },
{ PPC_INS_ALIAS_BNULp, "bnulp" },
{ PPC_INS_ALIAS_BNULAp, "bnulap" },
{ PPC_INS_ALIAS_BNULRLp, "bnulrlp" },
{ PPC_INS_ALIAS_BNUCTRLp, "bnuctrlp" },
{ PPC_INS_ALIAS_BNS, "bns" },
{ PPC_INS_ALIAS_BNSA, "bnsa" },
{ PPC_INS_ALIAS_BNSLR, "bnslr" },
@ -583,22 +592,22 @@
{ PPC_INS_ALIAS_BNSLA, "bnsla" },
{ PPC_INS_ALIAS_BNSLRL, "bnslrl" },
{ PPC_INS_ALIAS_BNSCTRL, "bnsctrl" },
{ PPC_INS_ALIAS_BNSm, "bns-" },
{ PPC_INS_ALIAS_BNSAm, "bnsa-" },
{ PPC_INS_ALIAS_BNSLRm, "bnslr-" },
{ PPC_INS_ALIAS_BNSCTRm, "bnsctr-" },
{ PPC_INS_ALIAS_BNSLm, "bnsl-" },
{ PPC_INS_ALIAS_BNSLAm, "bnsla-" },
{ PPC_INS_ALIAS_BNSLRLm, "bnslrl-" },
{ PPC_INS_ALIAS_BNSCTRLm, "bnsctrl-" },
{ PPC_INS_ALIAS_BNSp, "bns+" },
{ PPC_INS_ALIAS_BNSAp, "bnsa+" },
{ PPC_INS_ALIAS_BNSLRp, "bnslr+" },
{ PPC_INS_ALIAS_BNSCTRp, "bnsctr+" },
{ PPC_INS_ALIAS_BNSLp, "bnsl+" },
{ PPC_INS_ALIAS_BNSLAp, "bnsla+" },
{ PPC_INS_ALIAS_BNSLRLp, "bnslrl+" },
{ PPC_INS_ALIAS_BNSCTRLp, "bnsctrl+" },
{ PPC_INS_ALIAS_BNSm, "bnsm" },
{ PPC_INS_ALIAS_BNSAm, "bnsam" },
{ PPC_INS_ALIAS_BNSLRm, "bnslrm" },
{ PPC_INS_ALIAS_BNSCTRm, "bnsctrm" },
{ PPC_INS_ALIAS_BNSLm, "bnslm" },
{ PPC_INS_ALIAS_BNSLAm, "bnslam" },
{ PPC_INS_ALIAS_BNSLRLm, "bnslrlm" },
{ PPC_INS_ALIAS_BNSCTRLm, "bnsctrlm" },
{ PPC_INS_ALIAS_BNSp, "bnsp" },
{ PPC_INS_ALIAS_BNSAp, "bnsap" },
{ PPC_INS_ALIAS_BNSLRp, "bnslrp" },
{ PPC_INS_ALIAS_BNSCTRp, "bnsctrp" },
{ PPC_INS_ALIAS_BNSLp, "bnslp" },
{ PPC_INS_ALIAS_BNSLAp, "bnslap" },
{ PPC_INS_ALIAS_BNSLRLp, "bnslrlp" },
{ PPC_INS_ALIAS_BNSCTRLp, "bnsctrlp" },
{ PPC_INS_ALIAS_CMPWI, "cmpwi" },
{ PPC_INS_ALIAS_CMPW, "cmpw" },
{ PPC_INS_ALIAS_CMPLWI, "cmplwi" },

57
arch/PowerPC/PPCGenCSFeatureName.inc
View file

@ -1,32 +1,43 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ PPC_FEATURE_IsNotISAFuture, "IsNotISAFuture" },
{ PPC_FEATURE_IsISA3_0, "IsISA3_0" },
{ PPC_FEATURE_In64BitMode, "In64BitMode" },
{ PPC_FEATURE_In32BitMode, "In32BitMode" },
{ PPC_FEATURE_PCRelativeMemops, "PCRelativeMemops" },
{ PPC_FEATURE_HasBPERMD, "HasBPERMD" },
{ PPC_FEATURE_HasSPE, "HasSPE" },
{ PPC_FEATURE_IsE500, "IsE500" },
{ PPC_FEATURE_IsPPC4xx, "IsPPC4xx" },
{ PPC_FEATURE_HasExtDiv, "HasExtDiv" },
{ PPC_FEATURE_IsISAFuture, "IsISAFuture" },
{ PPC_FEATURE_HasFPU, "HasFPU" },
{ PPC_FEATURE_HasICBT, "HasICBT" },
{ PPC_FEATURE_HasPartwordAtomics, "HasPartwordAtomics" },
{ PPC_FEATURE_IsISA2_06, "IsISA2_06" },
{ PPC_FEATURE_IsBookE, "IsBookE" },
{ PPC_FEATURE_HasPS, "HasPS" },
{ PPC_FEATURE_HasQPX, "HasQPX" },
{ PPC_FEATURE_IsPPC6xx, "IsPPC6xx" },
{ PPC_FEATURE_HASPS, "HasPS" },
{ PPC_FEATURE_IN32BITMODE, "In32BitMode" },
{ PPC_FEATURE_IN64BITMODE, "In64BitMode" },
{ PPC_FEATURE_ISBOOKE, "IsBookE" },
{ PPC_FEATURE_ISNOTBOOKE, "IsNotBookE" },
{ PPC_FEATURE_HASONLYMSYNC, "HasOnlyMSYNC" },
{ PPC_FEATURE_HASSYNC, "HasSYNC" },
{ PPC_FEATURE_ISPPC4XX, "IsPPC4xx" },
{ PPC_FEATURE_ISPPC6XX, "IsPPC6xx" },
{ PPC_FEATURE_ISE500, "IsE500" },
{ PPC_FEATURE_HASSPE, "HasSPE" },
{ PPC_FEATURE_HASICBT, "HasICBT" },
{ PPC_FEATURE_HASPARTWORDATOMICS, "HasPartwordAtomics" },
{ PPC_FEATURE_HASQUADWORDATOMICS, "HasQuadwordAtomics" },
{ PPC_FEATURE_NONANSFPMATH, "NoNaNsFPMath" },
{ PPC_FEATURE_NANSFPMATH, "NaNsFPMath" },
{ PPC_FEATURE_HASBPERMD, "HasBPERMD" },
{ PPC_FEATURE_HASEXTDIV, "HasExtDiv" },
{ PPC_FEATURE_ISISA2_06, "IsISA2_06" },
{ PPC_FEATURE_ISISA2_07, "IsISA2_07" },
{ PPC_FEATURE_ISISA3_0, "IsISA3_0" },
{ PPC_FEATURE_HASFPU, "HasFPU" },
{ PPC_FEATURE_PCRELATIVEMEMOPS, "PCRelativeMemops" },
{ PPC_FEATURE_ISNOTISA3_1, "IsNotISA3_1" },
{ PPC_FEATURE_MODERNAS, "ModernAs" },
{ PPC_FEATURE_ISAIX, "IsAIX" },
{ PPC_FEATURE_NOTAIX, "NotAIX" },
{ PPC_FEATURE_ISISAFUTURE, "IsISAFuture" },
{ PPC_FEATURE_ISNOTISAFUTURE, "IsNotISAFuture" },
{ PPC_FEATURE_HASQPX, "HasQPX" },

15823
arch/PowerPC/PPCGenCSMappingInsn.inc
View file

File diff suppressed because it is too large Load diff

71
arch/PowerPC/PPCGenCSMappingInsnName.inc
View file

@ -1,10 +1,10 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
@ -37,6 +37,7 @@
"insrdi", // PPC_INS_INSRDI
"insrwi", // PPC_INS_INSRWI
"la", // PPC_INS_LA
"psubi", // PPC_INS_PSUBI
"rlwimi", // PPC_INS_RLWIMI
"rlwinm", // PPC_INS_RLWINM
"rlwnm", // PPC_INS_RLWNM
@ -57,6 +58,7 @@
"adde", // PPC_INS_ADDE
"addeo", // PPC_INS_ADDEO
"addex", // PPC_INS_ADDEX
"addg6s", // PPC_INS_ADDG6S
"addi", // PPC_INS_ADDI
"addic", // PPC_INS_ADDIC
"addis", // PPC_INS_ADDIS
@ -98,6 +100,8 @@
"brh", // PPC_INS_BRH
"brinc", // PPC_INS_BRINC
"brw", // PPC_INS_BRW
"cbcdtd", // PPC_INS_CBCDTD
"cdtbcd", // PPC_INS_CDTBCD
"cfuged", // PPC_INS_CFUGED
"clrbhrb", // PPC_INS_CLRBHRB
"cmpb", // PPC_INS_CMPB
@ -128,6 +132,8 @@
"cror", // PPC_INS_CROR
"crorc", // PPC_INS_CRORC
"crxor", // PPC_INS_CRXOR
"dadd", // PPC_INS_DADD
"daddq", // PPC_INS_DADDQ
"darn", // PPC_INS_DARN
"dcba", // PPC_INS_DCBA
"dcbfep", // PPC_INS_DCBFEP
@ -141,6 +147,26 @@
"dcbzl", // PPC_INS_DCBZL
"dcbzlep", // PPC_INS_DCBZLEP
"dccci", // PPC_INS_DCCCI
"dcffix", // PPC_INS_DCFFIX
"dcffixq", // PPC_INS_DCFFIXQ
"dcffixqq", // PPC_INS_DCFFIXQQ
"dcmpo", // PPC_INS_DCMPO
"dcmpoq", // PPC_INS_DCMPOQ
"dcmpu", // PPC_INS_DCMPU
"dcmpuq", // PPC_INS_DCMPUQ
"dctdp", // PPC_INS_DCTDP
"dctfix", // PPC_INS_DCTFIX
"dctfixq", // PPC_INS_DCTFIXQ
"dctfixqq", // PPC_INS_DCTFIXQQ
"dctqpq", // PPC_INS_DCTQPQ
"ddedpd", // PPC_INS_DDEDPD
"ddedpdq", // PPC_INS_DDEDPDQ
"ddiv", // PPC_INS_DDIV
"ddivq", // PPC_INS_DDIVQ
"denbcd", // PPC_INS_DENBCD
"denbcdq", // PPC_INS_DENBCDQ
"diex", // PPC_INS_DIEX
"diexq", // PPC_INS_DIEXQ
"divd", // PPC_INS_DIVD
"divde", // PPC_INS_DIVDE
"divdeo", // PPC_INS_DIVDEO
@ -159,17 +185,49 @@
"divwuo", // PPC_INS_DIVWUO
"dmmr", // PPC_INS_DMMR
"dmsetdmrz", // PPC_INS_DMSETDMRZ
"dmul", // PPC_INS_DMUL
"dmulq", // PPC_INS_DMULQ
"dmxor", // PPC_INS_DMXOR
"dmxxextfdmr256", // PPC_INS_DMXXEXTFDMR256
"dmxxextfdmr512", // PPC_INS_DMXXEXTFDMR512
"dmxxinstfdmr256", // PPC_INS_DMXXINSTFDMR256
"dmxxinstfdmr512", // PPC_INS_DMXXINSTFDMR512
"dqua", // PPC_INS_DQUA
"dquai", // PPC_INS_DQUAI
"dquaiq", // PPC_INS_DQUAIQ
"dquaq", // PPC_INS_DQUAQ
"drdpq", // PPC_INS_DRDPQ
"drintn", // PPC_INS_DRINTN
"drintnq", // PPC_INS_DRINTNQ
"drintx", // PPC_INS_DRINTX
"drintxq", // PPC_INS_DRINTXQ
"drrnd", // PPC_INS_DRRND
"drrndq", // PPC_INS_DRRNDQ
"drsp", // PPC_INS_DRSP
"dscli", // PPC_INS_DSCLI
"dscliq", // PPC_INS_DSCLIQ
"dscri", // PPC_INS_DSCRI
"dscriq", // PPC_INS_DSCRIQ
"dss", // PPC_INS_DSS
"dssall", // PPC_INS_DSSALL
"dst", // PPC_INS_DST
"dstst", // PPC_INS_DSTST
"dststt", // PPC_INS_DSTSTT
"dstt", // PPC_INS_DSTT
"dsub", // PPC_INS_DSUB
"dsubq", // PPC_INS_DSUBQ
"dtstdc", // PPC_INS_DTSTDC
"dtstdcq", // PPC_INS_DTSTDCQ
"dtstdg", // PPC_INS_DTSTDG
"dtstdgq", // PPC_INS_DTSTDGQ
"dtstex", // PPC_INS_DTSTEX
"dtstexq", // PPC_INS_DTSTEXQ
"dtstsf", // PPC_INS_DTSTSF
"dtstsfi", // PPC_INS_DTSTSFI
"dtstsfiq", // PPC_INS_DTSTSFIQ
"dtstsfq", // PPC_INS_DTSTSFQ
"dxex", // PPC_INS_DXEX
"dxexq", // PPC_INS_DXEXQ
"efdabs", // PPC_INS_EFDABS
"efdadd", // PPC_INS_EFDADD
"efdcfs", // PPC_INS_EFDCFS
@ -522,6 +580,8 @@
"lhzu", // PPC_INS_LHZU
"lhzux", // PPC_INS_LHZUX
"lhzx", // PPC_INS_LHZX
"li", // PPC_INS_LI
"lis", // PPC_INS_LIS
"lmw", // PPC_INS_LMW
"lq", // PPC_INS_LQ
"lqarx", // PPC_INS_LQARX
@ -658,6 +718,7 @@
"paddi", // PPC_INS_PADDI
"pdepd", // PPC_INS_PDEPD
"pextd", // PPC_INS_PEXTD
"pla", // PPC_INS_PLA
"plbz", // PPC_INS_PLBZ
"pld", // PPC_INS_PLD
"plfd", // PPC_INS_PLFD
@ -882,6 +943,7 @@
"rldicr", // PPC_INS_RLDICR
"rldimi", // PPC_INS_RLDIMI
"sc", // PPC_INS_SC
"scv", // PPC_INS_SCV
"setb", // PPC_INS_SETB
"setbc", // PPC_INS_SETBC
"setbcr", // PPC_INS_SETBCR
@ -1006,6 +1068,7 @@
"tlbia", // PPC_INS_TLBIA
"tlbie", // PPC_INS_TLBIE
"tlbiel", // PPC_INS_TLBIEL
"tlbilx", // PPC_INS_TLBILX
"tlbivax", // PPC_INS_TLBIVAX
"tlbld", // PPC_INS_TLBLD
"tlbli", // PPC_INS_TLBLI

17619
arch/PowerPC/PPCGenCSMappingInsnOp.inc
View file

File diff suppressed because it is too large Load diff

39
arch/PowerPC/PPCGenCSOpGroup.inc
View file

@ -1,6 +1,6 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
@ -17,26 +17,25 @@
PPC_OP_GROUP_U6ImmOperand = 3,
PPC_OP_GROUP_U5ImmOperand = 4,
PPC_OP_GROUP_MemRegImm = 5,
PPC_OP_GROUP_S16ImmOperand = 6,
PPC_OP_GROUP_U2ImmOperand = 7,
PPC_OP_GROUP_U16ImmOperand = 8,
PPC_OP_GROUP_BranchOperand = 9,
PPC_OP_GROUP_AbsBranchOperand = 10,
PPC_OP_GROUP_PredicateOperand = 11,
PPC_OP_GROUP_U1ImmOperand = 12,
PPC_OP_GROUP_TLSCall = 13,
PPC_OP_GROUP_U3ImmOperand = 14,
PPC_OP_GROUP_S5ImmOperand = 15,
PPC_OP_GROUP_MemRegImmHash = 16,
PPC_OP_GROUP_U4ImmOperand = 17,
PPC_OP_GROUP_U10ImmOperand = 18,
PPC_OP_GROUP_crbitm = 19,
PPC_OP_GROUP_S34ImmOperand = 20,
PPC_OP_GROUP_S34ImmOperand = 6,
PPC_OP_GROUP_S16ImmOperand = 7,
PPC_OP_GROUP_U2ImmOperand = 8,
PPC_OP_GROUP_U16ImmOperand = 9,
PPC_OP_GROUP_BranchOperand = 10,
PPC_OP_GROUP_AbsBranchOperand = 11,
PPC_OP_GROUP_PredicateOperand = 12,
PPC_OP_GROUP_U1ImmOperand = 13,
PPC_OP_GROUP_TLSCall = 14,
PPC_OP_GROUP_U3ImmOperand = 15,
PPC_OP_GROUP_S5ImmOperand = 16,
PPC_OP_GROUP_MemRegImmHash = 17,
PPC_OP_GROUP_U4ImmOperand = 18,
PPC_OP_GROUP_U10ImmOperand = 19,
PPC_OP_GROUP_crbitm = 20,
PPC_OP_GROUP_ImmZeroOperand = 21,
PPC_OP_GROUP_MemRegImm34 = 22,
PPC_OP_GROUP_MemRegImm34PCRel = 23,
PPC_OP_GROUP_U8ImmOperand = 24,
PPC_OP_GROUP_MemRegImmPS = 25,
PPC_OP_GROUP_U12ImmOperand = 26,
PPC_OP_GROUP_U7ImmOperand = 27,
PPC_OP_GROUP_ATBitsAsHint = 28,
PPC_OP_GROUP_U12ImmOperand = 25,
PPC_OP_GROUP_U7ImmOperand = 26,
PPC_OP_GROUP_ATBitsAsHint = 27,

13000
arch/PowerPC/PPCGenDisassemblerTables.inc
View file

File diff suppressed because it is too large Load diff

13401
arch/PowerPC/PPCGenInstrInfo.inc
View file

File diff suppressed because it is too large Load diff

2842
arch/PowerPC/PPCGenRegisterInfo.inc
View file

File diff suppressed because it is too large Load diff

173
arch/PowerPC/PPCGenSubtargetInfo.inc
View file

@ -1,10 +1,10 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
@ -45,88 +45,89 @@ enum {
PPC_DirectivePwrFuture = 27,
PPC_Feature64Bit = 28,
PPC_Feature64BitRegs = 29,
PPC_FeatureAddLogicalFusion = 30,
PPC_FeatureAddiLoadFusion = 31,
PPC_FeatureAddisLoadFusion = 32,
PPC_FeatureAltivec = 33,
PPC_FeatureArithAddFusion = 34,
PPC_FeatureBPERMD = 35,
PPC_FeatureBack2BackFusion = 36,
PPC_FeatureBookE = 37,
PPC_FeatureCMPB = 38,
PPC_FeatureCRBits = 39,
PPC_FeatureCompareFusion = 40,
PPC_FeatureDirectMove = 41,
PPC_FeatureE500 = 42,
PPC_FeatureEFPU2 = 43,
PPC_FeatureExtDiv = 44,
PPC_FeatureFCPSGN = 45,
PPC_FeatureFPCVT = 46,
PPC_FeatureFPRND = 47,
PPC_FeatureFPU = 48,
PPC_FeatureFRE = 49,
PPC_FeatureFRES = 50,
PPC_FeatureFRSQRTE = 51,
PPC_FeatureFRSQRTES = 52,
PPC_FeatureFSqrt = 53,
PPC_FeatureFastMFLR = 54,
PPC_FeatureFloat128 = 55,
PPC_FeatureFusion = 56,
PPC_FeatureHTM = 57,
PPC_FeatureHardFloat = 58,
PPC_FeatureICBT = 59,
PPC_FeatureISA2_06 = 60,
PPC_FeatureISA2_07 = 61,
PPC_FeatureISA3_0 = 62,
PPC_FeatureISA3_1 = 63,
PPC_FeatureISAFuture = 64,
PPC_FeatureISEL = 65,
PPC_FeatureInvariantFunctionDescriptors = 66,
PPC_FeatureLDBRX = 67,
PPC_FeatureLFIWAX = 68,
PPC_FeatureLogicalAddFusion = 69,
PPC_FeatureLogicalFusion = 70,
PPC_FeatureLongCall = 71,
PPC_FeatureMFOCRF = 72,
PPC_FeatureMFTB = 73,
PPC_FeatureMMA = 74,
PPC_FeatureMSYNC = 75,
PPC_FeatureModernAIXAs = 76,
PPC_FeatureP8Altivec = 77,
PPC_FeatureP8Crypto = 78,
PPC_FeatureP8Vector = 79,
PPC_FeatureP9Altivec = 80,
PPC_FeatureP9Vector = 81,
PPC_FeatureP10Vector = 82,
PPC_FeaturePCRelativeMemops = 83,
PPC_FeaturePOPCNTD = 84,
PPC_FeaturePPC4xx = 85,
PPC_FeaturePPC6xx = 86,
PPC_FeaturePPCPostRASched = 87,
PPC_FeaturePPCPreRASched = 88,
PPC_FeaturePS = 89,
PPC_FeaturePairedVectorMemops = 90,
PPC_FeaturePartwordAtomic = 91,
PPC_FeaturePredictableSelectIsExpensive = 92,
PPC_FeaturePrefixInstrs = 93,
PPC_FeaturePrivileged = 94,
PPC_FeatureQPX = 95,
PPC_FeatureQuadwordAtomic = 96,
PPC_FeatureROPProtect = 97,
PPC_FeatureRecipPrec = 98,
PPC_FeatureSPE = 99,
PPC_FeatureSTFIWX = 100,
PPC_FeatureSecurePlt = 101,
PPC_FeatureSha3Fusion = 102,
PPC_FeatureSlowPOPCNTD = 103,
PPC_FeatureStoreFusion = 104,
PPC_FeatureTwoConstNR = 105,
PPC_FeatureUnalignedFloats = 106,
PPC_FeatureVSX = 107,
PPC_FeatureVectorsUseTwoUnits = 108,
PPC_FeatureWideImmFusion = 109,
PPC_FeatureZeroMoveFusion = 110,
PPC_NumSubtargetFeatures = 111
PPC_FeatureAIXLocalExecTLS = 30,
PPC_FeatureAddLogicalFusion = 31,
PPC_FeatureAddiLoadFusion = 32,
PPC_FeatureAddisLoadFusion = 33,
PPC_FeatureAltivec = 34,
PPC_FeatureArithAddFusion = 35,
PPC_FeatureBPERMD = 36,
PPC_FeatureBack2BackFusion = 37,
PPC_FeatureBookE = 38,
PPC_FeatureCMPB = 39,
PPC_FeatureCRBits = 40,
PPC_FeatureCompareFusion = 41,
PPC_FeatureDirectMove = 42,
PPC_FeatureE500 = 43,
PPC_FeatureEFPU2 = 44,
PPC_FeatureExtDiv = 45,
PPC_FeatureFCPSGN = 46,
PPC_FeatureFPCVT = 47,
PPC_FeatureFPRND = 48,
PPC_FeatureFPU = 49,
PPC_FeatureFRE = 50,
PPC_FeatureFRES = 51,
PPC_FeatureFRSQRTE = 52,
PPC_FeatureFRSQRTES = 53,
PPC_FeatureFSqrt = 54,
PPC_FeatureFastMFLR = 55,
PPC_FeatureFloat128 = 56,
PPC_FeatureFusion = 57,
PPC_FeatureHTM = 58,
PPC_FeatureHardFloat = 59,
PPC_FeatureICBT = 60,
PPC_FeatureISA2_06 = 61,
PPC_FeatureISA2_07 = 62,
PPC_FeatureISA3_0 = 63,
PPC_FeatureISA3_1 = 64,
PPC_FeatureISAFuture = 65,
PPC_FeatureISEL = 66,
PPC_FeatureInvariantFunctionDescriptors = 67,
PPC_FeatureLDBRX = 68,
PPC_FeatureLFIWAX = 69,
PPC_FeatureLogicalAddFusion = 70,
PPC_FeatureLogicalFusion = 71,
PPC_FeatureLongCall = 72,
PPC_FeatureMFOCRF = 73,
PPC_FeatureMFTB = 74,
PPC_FeatureMMA = 75,
PPC_FeatureMSYNC = 76,
PPC_FeatureModernAIXAs = 77,
PPC_FeatureP8Altivec = 78,
PPC_FeatureP8Crypto = 79,
PPC_FeatureP8Vector = 80,
PPC_FeatureP9Altivec = 81,
PPC_FeatureP9Vector = 82,
PPC_FeatureP10Vector = 83,
PPC_FeaturePCRelativeMemops = 84,
PPC_FeaturePOPCNTD = 85,
PPC_FeaturePPC4xx = 86,
PPC_FeaturePPC6xx = 87,
PPC_FeaturePPCPostRASched = 88,
PPC_FeaturePPCPreRASched = 89,
PPC_FeaturePS = 90,
PPC_FeaturePairedVectorMemops = 91,
PPC_FeaturePartwordAtomic = 92,
PPC_FeaturePredictableSelectIsExpensive = 93,
PPC_FeaturePrefixInstrs = 94,
PPC_FeaturePrivileged = 95,
PPC_FeatureQPX = 96,
PPC_FeatureQuadwordAtomic = 97,
PPC_FeatureROPProtect = 98,
PPC_FeatureRecipPrec = 99,
PPC_FeatureSPE = 100,
PPC_FeatureSTFIWX = 101,
PPC_FeatureSecurePlt = 102,
PPC_FeatureSha3Fusion = 103,
PPC_FeatureSlowPOPCNTD = 104,
PPC_FeatureStoreFusion = 105,
PPC_FeatureTwoConstNR = 106,
PPC_FeatureUnalignedFloats = 107,
PPC_FeatureVSX = 108,
PPC_FeatureVectorsUseTwoUnits = 109,
PPC_FeatureWideImmFusion = 110,
PPC_FeatureZeroMoveFusion = 111,
PPC_NumSubtargetFeatures = 112
};
#endif // GET_SUBTARGETINFO_ENUM

1026
arch/PowerPC/PPCInstPrinter.c
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File diff suppressed because it is too large Load diff

79
arch/PowerPC/PPCInstPrinter.h
View file

@ -1,79 +0,0 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax -*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an PPC MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifndef CS_PPC_INSTPRINTER_H
#define CS_PPC_INSTPRINTER_H
#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "../../LEB128.h"
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "PPCMCTargetDesc.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
bool showRegistersWithPercentPrefix(const MCInst *MI, const char *RegName);
bool showRegistersWithPrefix(const MCInst *MI);
// Autogenerated by tblgen.
void printATBitsAsHint(MCInst *MI, unsigned OpNo, SStream *O);
void printU1ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU3ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU7ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU8ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU10ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printS12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printS34ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printImmZeroOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo,
SStream *O);
void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O);
void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O);
void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O);
void printMemRegImmPS(MCInst *MI, unsigned OpNo, SStream *O);
void printMemRegImmHash(MCInst *MI, unsigned OpNo, SStream *O);
void printMemRegImm34PCRel(MCInst *MI, unsigned OpNo, SStream *O);
void printMemRegImm34(MCInst *MI, unsigned OpNo, SStream *O);
void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O);
;
// end namespace llvm
#endif // CS_PPC_INSTPRINTER_H

2
arch/PowerPC/PPCInstrInfo.h
View file

@ -6,8 +6,6 @@
#include "PPCMCTargetDesc.h"
extern const MCInstrDesc PPCInsts[];
static bool isVFRegister(unsigned Reg)
{
return Reg >= PPC_VF0 && Reg <= PPC_VF31;

79
arch/PowerPC/PPCMCTargetDesc.h
View file

@ -1,3 +1,5 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
@ -120,68 +122,55 @@ static inline bool isRunOfOnes64(uint64_t Val, unsigned *MB, unsigned *ME)
#define GET_SUBTARGETINFO_ENUM
#include "PPCGenSubtargetInfo.inc"
#define PPC_REGS0_7(X) \
{ \
X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
}
#define PPC_REGS0_7(X) { X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 }
#define PPC_REGS0_31(X) \
{ \
X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
}
{ X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, \
X##8, X##9, X##10, X##11, X##12, X##13, X##14, X##15, \
X##16, X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 }
#define PPC_REGS_EVEN0_30(X) \
{ X##0, X##2, X##4, X##6, X##8, X##10, X##12, X##14, \
X##16, X##18, X##20, X##22, X##24, X##26, X##28, X##30 }
#define PPC_REGS0_63(X) \
{ \
X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
X##24, X##25, X##26, X##27, X##28, X##29, X##30, \
X##31, X##32, X##33, X##34, X##35, X##36, X##37, \
X##38, X##39, X##40, X##41, X##42, X##43, X##44, \
X##45, X##46, X##47, X##48, X##49, X##50, X##51, \
X##52, X##53, X##54, X##55, X##56, X##57, X##58, \
X##59, X##60, X##61, X##62, X##63 \
X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, \
X##8, X##9, X##10, X##11, X##12, X##13, X##14, X##15, \
X##16, X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31, \
X##32, X##33, X##34, X##35, X##36, X##37, X##38, X##39, \
X##40, X##41, X##42, X##43, X##44, X##45, X##46, X##47, \
X##48, X##49, X##50, X##51, X##52, X##53, X##54, X##55, \
X##56, X##57, X##58, X##59, X##60, X##61, X##62, X##63 \
}
#define PPC_REGS_NO0_31(Z, X) \
{ \
Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
}
{ Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, \
X##8, X##9, X##10, X##11, X##12, X##13, X##14, X##15, \
X##16, X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 }
#define PPC_REGS_LO_HI(LO, HI) \
{ \
LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, \
LO##9, LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, \
LO##16, LO##17, LO##18, LO##19, LO##20, LO##21, \
LO##22, LO##23, LO##24, LO##25, LO##26, LO##27, \
LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, \
HI##10, HI##11, HI##12, HI##13, HI##14, HI##15, \
HI##16, HI##17, HI##18, HI##19, HI##20, HI##21, \
HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
HI##28, HI##29, HI##30, HI##31 \
}
{ LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, \
LO##8, LO##9, LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, \
LO##16, LO##17, LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, \
LO##24, LO##25, LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, \
HI##0, HI##1, HI##2, HI##3, HI##4, HI##5, HI##6, HI##7, \
HI##8, HI##9, HI##10, HI##11, HI##12, HI##13, HI##14, HI##15, \
HI##16, HI##17, HI##18, HI##19, HI##20, HI##21, HI##22, HI##23, \
HI##24, HI##25, HI##26, HI##27, HI##28, HI##29, HI##30, HI##31 }
#define PPC_REGS0_7(X) \
{ \
X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
}
#define PPC_REGS0_7(X) { X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 }
#define PPC_REGS0_3(X) \
{ \
X##0, X##1, X##2, X##3 \
}
#define PPC_REGS0_3(X) { X##0, X##1, X##2, X##3 }
#define DEFINE_PPC_REGCLASSES \
static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC_R); \
static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC_X); \
static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC_F); \
static const MCPhysReg FpRegs[16] = PPC_REGS_EVEN0_30(PPC_Fpair); \
static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC_VSRp); \
static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC_S); \
static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC_VF); \

184
arch/PowerPC/PPCMapping.c
View file

@ -1,7 +1,7 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#include "capstone/ppc.h"
#include "capstone/capstone.h"
#ifdef CAPSTONE_HAS_POWERPC
#include <stdio.h> // debug
@ -16,6 +16,99 @@
#include "PPCMapping.h"
#include "PPCMCTargetDesc.h"
static int P7InheritableFeatures[] = {
PPC_DirectivePwr7, PPC_FeatureAltivec,
PPC_FeatureVSX, PPC_FeatureMFOCRF,
PPC_FeatureFCPSGN, PPC_FeatureFSqrt,
PPC_FeatureFRE, PPC_FeatureFRES,
PPC_FeatureFRSQRTE, PPC_FeatureFRSQRTES,
PPC_FeatureRecipPrec, PPC_FeatureSTFIWX,
PPC_FeatureLFIWAX, PPC_FeatureFPRND,
PPC_FeatureFPCVT, PPC_FeatureISEL,
PPC_FeaturePOPCNTD, PPC_FeatureCMPB,
PPC_FeatureLDBRX, PPC_Feature64Bit,
PPC_FeatureBPERMD, PPC_FeatureExtDiv,
PPC_FeatureMFTB, PPC_DeprecatedDST,
PPC_FeatureTwoConstNR, PPC_FeatureUnalignedFloats,
PPC_FeatureISA2_06, INT_MAX
};
static int *P7Features[] = { P7InheritableFeatures };
// Power8
static int P8AdditionalFeatures[] = { PPC_DirectivePwr8,
PPC_FeatureP8Altivec,
PPC_FeatureP8Vector,
PPC_FeatureP8Crypto,
PPC_FeatureHTM,
PPC_FeatureDirectMove,
PPC_FeatureICBT,
PPC_FeaturePartwordAtomic,
PPC_FeatureQuadwordAtomic,
PPC_FeaturePredictableSelectIsExpensive,
PPC_FeatureISA2_07,
PPC_FeatureCRBits,
INT_MAX };
static int P8SpecificFeatures[] = { PPC_FeatureAddiLoadFusion,
PPC_FeatureAddisLoadFusion, INT_MAX };
static int *P8Features[] = { P7InheritableFeatures, P8AdditionalFeatures,
P8SpecificFeatures };
static int P9AdditionalFeatures[] = { PPC_DirectivePwr9,
PPC_FeatureP9Altivec,
PPC_FeatureP9Vector,
PPC_FeaturePPCPreRASched,
PPC_FeaturePPCPostRASched,
PPC_FeatureISA3_0,
PPC_FeaturePredictableSelectIsExpensive,
INT_MAX };
static int P9SpecificFeatures[] = { PPC_FeatureVectorsUseTwoUnits, INT_MAX };
static int *P9Features[] = { P7InheritableFeatures, P8AdditionalFeatures,
P9AdditionalFeatures, P9SpecificFeatures };
static int P10AdditionalFeatures[] = { PPC_FeatureStoreFusion,
PPC_FeatureAddLogicalFusion,
PPC_FeatureLogicalAddFusion,
PPC_FeatureLogicalFusion,
PPC_FeatureArithAddFusion,
PPC_FeatureSha3Fusion,
PPC_DirectivePwr10,
PPC_FeatureISA3_1,
PPC_FeaturePrefixInstrs,
PPC_FeaturePCRelativeMemops,
PPC_FeatureP10Vector,
PPC_FeatureMMA,
PPC_FeaturePairedVectorMemops,
PPC_FeatureFastMFLR,
INT_MAX };
static int *P10Features[] = { P7InheritableFeatures, P8AdditionalFeatures,
P9AdditionalFeatures, P10AdditionalFeatures };
static int FutureAdditionalFeatures[] = { PPC_FeatureISAFuture, INT_MAX };
static int *FutureFeatures[] = { P7InheritableFeatures, P8AdditionalFeatures,
P9AdditionalFeatures, P10AdditionalFeatures,
FutureAdditionalFeatures };
static inline bool is_feature_of(int feature, int **feature_set, int set_size)
{
for (size_t i = 0; i < set_size; ++i) {
size_t j = 0;
while (feature_set[i][j] != INT_MAX) {
if (feature == feature_set[i][j]) {
return true;
}
++j;
}
}
return false;
}
#define GET_REGINFO_MC_DESC
#include "PPCGenRegisterInfo.inc"
@ -82,7 +175,9 @@ static const name_map group_name_maps[] = {
{ PPC_GRP_INVALID, NULL },
{ PPC_GRP_JUMP, "jump" },
{ PPC_GRP_CALL, "call" },
{ PPC_GRP_RET, "ret" },
{ PPC_GRP_INT, "int" },
{ PPC_GRP_IRET, "iret" },
{ PPC_GRP_PRIVILEGE, "privilege" },
{ PPC_GRP_BRANCH_RELATIVE, "branch_relative" },
@ -244,23 +339,41 @@ bool PPC_getInstruction(csh handle, const uint8_t *bytes, size_t bytes_len,
bool PPC_getFeatureBits(unsigned int mode, unsigned int feature)
{
if ((feature == PPC_FeatureQPX) && (mode & CS_MODE_QPX) == 0) {
return false;
} else if ((feature == PPC_FeatureSPE) && (mode & CS_MODE_SPE) == 0) {
return false;
} else if ((feature == PPC_FeatureBookE) &&
(mode & CS_MODE_BOOKE) == 0) {
return false;
} else if ((feature == PPC_FeaturePS) && (mode & CS_MODE_PS) == 0) {
return false;
if (feature == PPC_FeatureQPX) {
return (mode & CS_MODE_QPX) != 0;
} else if (feature == PPC_FeatureSPE) {
return (mode & CS_MODE_SPE) != 0;
} else if (feature == PPC_FeatureBookE) {
return (mode & CS_MODE_BOOKE) != 0;
} else if (feature == PPC_FeaturePS) {
return (mode & CS_MODE_PS) != 0;
} else if (feature == PPC_FeatureModernAIXAs) {
return (mode & CS_MODE_MODERN_AIX_AS) != 0;
} else if (feature == PPC_AIXOS) {
return (mode & CS_MODE_AIX_OS) != 0 || (mode & CS_MODE_MODERN_AIX_AS) != 0;
} else if (feature == PPC_FeatureMSYNC) {
return (mode & CS_MODE_MSYNC) != 0;
}
if ((mode & (CS_MODE_PWR7 | CS_MODE_PWR8 | CS_MODE_PWR9 | CS_MODE_PWR10 | CS_MODE_PPC_ISA_FUTURE)) == 0) {
// By default support everything
return true;
}
// No AIX support for now.
if (feature == PPC_FeatureModernAIXAs || feature == PPC_AIXOS)
return false;
// TODO Make it optional
if (feature == PPC_FeatureMSYNC)
return false;
if (is_feature_of(feature, P7Features, ARR_SIZE(P7Features))) {
return (mode & (CS_MODE_PWR7 | CS_MODE_PWR8 | CS_MODE_PWR9 | CS_MODE_PWR10 | CS_MODE_PPC_ISA_FUTURE));
}
if (is_feature_of(feature, P8Features, ARR_SIZE(P8Features))) {
return (mode & (CS_MODE_PWR8 | CS_MODE_PWR9 | CS_MODE_PWR10 | CS_MODE_PPC_ISA_FUTURE));
}
if (is_feature_of(feature, P9Features, ARR_SIZE(P9Features))) {
return (mode & (CS_MODE_PWR9 | CS_MODE_PWR10 | CS_MODE_PPC_ISA_FUTURE));
}
if (is_feature_of(feature, P10Features, ARR_SIZE(P10Features))) {
return (mode & (CS_MODE_PWR10 | CS_MODE_PPC_ISA_FUTURE));
}
if (is_feature_of(feature, FutureFeatures, ARR_SIZE(FutureFeatures))) {
return (mode & CS_MODE_PPC_ISA_FUTURE);
}
// By default support everything
return true;
@ -317,7 +430,7 @@ static void add_cs_detail_general(MCInst *MI, ppc_op_group op_group,
}
CS_ASSERT_RET((op_type & CS_OP_MEM) ==
0); // doing_mem should have been true.
0); // doing_mem should have been true.
if (op_type == CS_OP_REG)
PPC_set_detail_op_reg(MI, OpNum,
@ -400,10 +513,9 @@ static void add_cs_detail_general(MCInst *MI, ppc_op_group op_group,
// Handled in printOperand()
return;
unsigned Val = MCInst_getOpVal(MI, OpNum) << 2;
int32_t Imm = SignExtend32(Val, 32);
PPC_check_safe_inc(MI);
PPC_get_detail_op(MI, 0)->type = PPC_OP_IMM;
PPC_get_detail_op(MI, 0)->imm = Imm;
PPC_get_detail_op(MI, 0)->imm = Val;
PPC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
PPC_inc_op_count(MI);
break;
@ -462,10 +574,8 @@ static void add_cs_detail_general(MCInst *MI, ppc_op_group op_group,
}
}
/// Fills cs_detail with the data of the operand.
/// Calls to this function should not be added by hand! Please checkout the
/// patch `AddCSDetail` of the CppTranslator.
void PPC_add_cs_detail(MCInst *MI, ppc_op_group op_group, va_list args)
void PPC_add_cs_detail_1(MCInst *MI, ppc_op_group op_group, unsigned OpNum,
const char *Modifier)
{
if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
return;
@ -475,8 +585,6 @@ void PPC_add_cs_detail(MCInst *MI, ppc_op_group op_group, va_list args)
printf("Operand group %d not handled!\n", op_group);
return;
case PPC_OP_GROUP_PredicateOperand: {
unsigned OpNum = va_arg(args, unsigned);
const char *Modifier = va_arg(args, const char *);
if ((strcmp(Modifier, "cc") == 0) ||
(strcmp(Modifier, "pm") == 0)) {
unsigned Val = MCInst_getOpVal(MI, OpNum);
@ -494,6 +602,21 @@ void PPC_add_cs_detail(MCInst *MI, ppc_op_group op_group, va_list args)
}
return;
}
}
}
/// Fills cs_detail with the data of the operand.
/// Calls to this function should not be added by hand! Please checkout the
/// patch `AddCSDetail` of the CppTranslator.
void PPC_add_cs_detail_0(MCInst *MI, ppc_op_group op_group, unsigned OpNo)
{
if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
return;
switch (op_group) {
default:
printf("Operand group %d not handled!\n", op_group);
return;
case PPC_OP_GROUP_S12ImmOperand:
case PPC_OP_GROUP_Operand:
case PPC_OP_GROUP_MemRegReg:
@ -521,8 +644,7 @@ void PPC_add_cs_detail(MCInst *MI, ppc_op_group op_group, va_list args)
case PPC_OP_GROUP_U12ImmOperand:
case PPC_OP_GROUP_U7ImmOperand:
case PPC_OP_GROUP_ATBitsAsHint: {
unsigned OpNum = va_arg(args, unsigned);
add_cs_detail_general(MI, op_group, OpNum);
add_cs_detail_general(MI, op_group, OpNo);
return;
}
}
@ -543,12 +665,14 @@ void PPC_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val,
case CS_OP_REG:
if (is_off_reg) {
PPC_get_detail_op(MI, 0)->mem.offset = Val;
if (PPC_get_detail_op(MI, 0)->mem.base != PPC_REG_INVALID)
if (PPC_get_detail_op(MI, 0)->mem.base !=
PPC_REG_INVALID)
set_mem_access(MI, false);
} else {
} else {
PPC_get_detail_op(MI, 0)->mem.base = Val;
if (MCInst_opIsTying(MI, OpNum))
map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum));
map_add_implicit_write(
MI, MCInst_getOpVal(MI, OpNum));
}
break;
case CS_OP_IMM:

13
arch/PowerPC/PPCMapping.h
View file

@ -46,17 +46,8 @@ ppc_reg PPC_map_register(unsigned int r);
bool PPC_getFeatureBits(unsigned int mode, unsigned int feature);
void PPC_add_cs_detail(MCInst *MI, ppc_op_group op_group, va_list args);
static inline void add_cs_detail(MCInst *MI, ppc_op_group op_group, ...)
{
if (!MI->flat_insn->detail)
return;
va_list args;
va_start(args, op_group);
PPC_add_cs_detail(MI, op_group, args);
va_end(args);
}
void PPC_add_cs_detail_0(MCInst *MI, ppc_op_group op_group, unsigned OpNo);
void PPC_add_cs_detail_1(MCInst *MI, ppc_op_group op_group, unsigned OpNo, const char *Modifier);
void PPC_set_detail_op_reg(MCInst *MI, unsigned OpNum, ppc_reg Reg);
void PPC_set_detail_op_imm(MCInst *MI, unsigned OpNum, int64_t Imm);

8
arch/PowerPC/PPCModule.c
View file

@ -5,7 +5,6 @@
#include "../../utils.h"
#include "../../MCRegisterInfo.h"
#include "PPCInstPrinter.h"
#include "PPCMapping.h"
#include "PPCModule.h"
@ -35,7 +34,14 @@ cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value)
handle->syntax = (int)value;
if (type == CS_OPT_MODE) {
if (value == CS_MODE_LITTLE_ENDIAN) {
handle->mode = handle->mode & ~CS_MODE_BIG_ENDIAN;
return CS_ERR_OK;
}
handle->mode |= (cs_mode)value;
if (value & CS_MODE_MSYNC) {
handle->mode |= (cs_mode)CS_MODE_BOOKE;
}
}
return CS_ERR_OK;

5
arch/PowerPC/PPCRegisterInfo.h
View file

@ -15,8 +15,11 @@ static const char *PPCRegisterInfo_stripRegisterPrefix(const char *RegName)
if (RegName[1] == 'c' && RegName[2] == 'c')
return RegName + 3;
break;
case 'r':
case 'f':
if (RegName[1] == 'p')
return RegName + 2;
// fallthrough
case 'r':
case 'v':
if (RegName[1] == 's') {
if (RegName[2] == 'p')

8
bindings/python/capstone/__init__.py
View file

@ -290,6 +290,14 @@ CS_MODE_QPX = (1 << 4) # Quad Processing eXtensions mode (PPC)
CS_MODE_SPE = (1 << 5) # Signal Processing Engine mode (PPC)
CS_MODE_BOOKE = (1 << 6) # Book-E mode (PPC)
CS_MODE_PS = (1 << 7) # Paired-singles mode (PPC)
CS_MODE_AIX_OS = (1 << 8) # PowerPC AIX-OS
CS_MODE_PWR7 = (1 << 9) # Power 7
CS_MODE_PWR8 = (1 << 10) # Power 8
CS_MODE_PWR9 = (1 << 11) # Power 9
CS_MODE_PWR10 = (1 << 12) # Power 10
CS_MODE_PPC_ISA_FUTURE = (1 << 13) # Power ISA Future
CS_MODE_MODERN_AIX_AS = (1 << 14) # PowerPC AIX-OS with modern assembly
CS_MODE_MSYNC = (1 << 15) # PowerPC Has only the msync instruction instead of sync. Implies BOOKE
CS_MODE_M68K_000 = (1 << 1) # M68K 68000 mode
CS_MODE_M68K_010 = (1 << 2) # M68K 68010 mode
CS_MODE_M68K_020 = (1 << 3) # M68K 68020 mode

5809
bindings/python/capstone/ppc_const.py
View file

File diff suppressed because it is too large Load diff

4
cs.c
View file

@ -138,7 +138,9 @@ typedef struct cs_arch_config {
PPC_global_init, \
PPC_option, \
~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_BIG_ENDIAN \
| CS_MODE_QPX | CS_MODE_PS | CS_MODE_BOOKE), \
| CS_MODE_QPX | CS_MODE_PS | CS_MODE_BOOKE | CS_MODE_SPE \
| CS_MODE_AIX_OS | CS_MODE_PWR7 | CS_MODE_PWR8 | CS_MODE_PWR9 \
| CS_MODE_PWR10 | CS_MODE_PPC_ISA_FUTURE | CS_MODE_MSYNC | CS_MODE_MODERN_AIX_AS), \
}
#define CS_ARCH_CONFIG_SPARC \
{ \

30
cstool/cstool.c
View file

@ -47,6 +47,20 @@ static struct {
CS_ARCH_MIPS, CS_ARCH_MAX }, 0, CS_MODE_MIPS_NOFLOAT },
{ "+ptr64", "Enables 64-bit pointers support", {
CS_ARCH_MIPS, CS_ARCH_MAX }, 0, CS_MODE_MIPS_PTR64 },
{ "+aix", "Enables AIX OS assembly", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_AIX_OS },
{ "+booke", "Enables BOOKE extension", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_BOOKE },
{ "+maix", "Enables Modern AIX assembly", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_MODERN_AIX_AS },
{ "+msync", "Has only the msync instruction instead of sync. Implies BookE.", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_MSYNC },
{ "+qpx", "Enables QPX extension", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_QPX },
{ "+ps", "Enables PS extension", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_PS },
{ "+spe", "Enables SPE extension", {
CS_ARCH_PPC, CS_ARCH_MAX }, 0, CS_MODE_SPE },
{ NULL }
};
@ -134,14 +148,18 @@ static struct {
{ "ppc32", "PowerPC 32-bit, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_LITTLE_ENDIAN },
{ "ppc32be", "PowerPC 32-bit, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN },
{ "ppc32qpx", "PowerPC 32-bit, qpx, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN },
{ "ppc32beqpx", "PowerPC 32-bit, qpx, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN },
{ "ppc32ps", "PowerPC 32-bit, ps, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_LITTLE_ENDIAN },
{ "ppc32beps", "PowerPC 32-bit, ps, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_BIG_ENDIAN },
{ "ppc64", "PowerPC 64-bit, little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_LITTLE_ENDIAN },
{ "ppc64be", "PowerPC 64-bit, big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN },
{ "ppc64qpx", "PowerPC 64-bit, qpx, little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN },
{ "ppc64beqpx", "PowerPC 64-bit, qpx, big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN },
{ "ppc64pwr7", "PowerPC 64-bit, Power7 (ISA v2.06), little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR7 | CS_MODE_LITTLE_ENDIAN },
{ "ppc64bepwr7", "PowerPC 64-bit, Power7 (ISA v2.06), big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR7 | CS_MODE_BIG_ENDIAN },
{ "ppc64pwr8", "PowerPC 64-bit, Power8 (ISA v2.07), little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR8 | CS_MODE_LITTLE_ENDIAN },
{ "ppc64bepwr8", "PowerPC 64-bit, Power8 (ISA v2.07), big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR8 | CS_MODE_BIG_ENDIAN },
{ "ppc64pwr9", "PowerPC 64-bit, Power9 (ISA v3.0), little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR9 | CS_MODE_LITTLE_ENDIAN },
{ "ppc64bepwr9", "PowerPC 64-bit, Power9 (ISA v3.0), big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR9 | CS_MODE_BIG_ENDIAN },
{ "ppc64pwr10", "PowerPC 64-bit, Power10 (ISA v3.1), little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR10 | CS_MODE_LITTLE_ENDIAN },
{ "ppc64bepwr10", "PowerPC 64-bit, Power10 (ISA v3.1), big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PWR10 | CS_MODE_BIG_ENDIAN },
{ "ppc64FutureISA", "PowerPC 64-bit, Future ISA, little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PPC_ISA_FUTURE | CS_MODE_LITTLE_ENDIAN },
{ "ppc64beFutureISA", "PowerPC 64-bit, Future ISA, big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_PPC_ISA_FUTURE | CS_MODE_BIG_ENDIAN },
{ "sparc", "Sparc, big endian", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN },
{ "sparcv9", "Sparc v9, big endian", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN | CS_MODE_V9 },

8
include/capstone/capstone.h
View file

@ -132,6 +132,14 @@ typedef enum cs_mode {
CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC)
CS_MODE_BOOKE = 1 << 6, ///< Book-E mode (PPC)
CS_MODE_PS = 1 << 7, ///< Paired-singles mode (PPC)
CS_MODE_AIX_OS = 1 << 8, ///< PowerPC AIX-OS
CS_MODE_PWR7 = 1 << 9, ///< Power 7
CS_MODE_PWR8 = 1 << 10, ///< Power 8
CS_MODE_PWR9 = 1 << 11, ///< Power 9
CS_MODE_PWR10 = 1 << 12, ///< Power 10
CS_MODE_PPC_ISA_FUTURE = 1 << 13, ///< Power ISA Future
CS_MODE_MODERN_AIX_AS = 1 << 14, ///< PowerPC AIX-OS with modern assembly
CS_MODE_MSYNC = 1 << 15, ///< PowerPC Has only the msync instruction instead of sync. Implies BOOKE
CS_MODE_M68K_000 = 1 << 1, ///< M68K 68000 mode
CS_MODE_M68K_010 = 1 << 2, ///< M68K 68010 mode
CS_MODE_M68K_020 = 1 << 3, ///< M68K 68020 mode

1008
include/capstone/ppc.h
View file

File diff suppressed because it is too large Load diff

3
suite/auto-sync/src/autosync/ASUpdater.py
View file

@ -51,6 +51,7 @@ class ASUpdater:
wait_for_user: bool = True,
) -> None:
self.arch = arch
self.arch_dir_name = TARGET_TO_DIR_NAME[self.arch]
self.write = write
self.no_clean_build = no_clean
self.inc_list = inc_list
@ -218,7 +219,7 @@ class ASUpdater:
# MC tests
i = 0
mc_dir = get_path("{MC_DIR}").joinpath(self.arch)
mc_dir = get_path("{MC_DIR}").joinpath(self.arch_dir_name)
log.info(f"Copy MC test files to {mc_dir}")
for file in get_path("{MCUPDATER_OUT_DIR}").iterdir():
self.copy_files(file, mc_dir)

34
suite/auto-sync/src/autosync/MCUpdater.py
View file

@ -11,7 +11,7 @@ import subprocess as sp
from pathlib import Path
from autosync.Targets import TARGETS_LLVM_NAMING
from autosync.Targets import TARGETS_LLVM_NAMING, TARGET_TO_DIR_NAME
from autosync.Helper import convert_loglevel, get_path
@ -212,7 +212,8 @@ class TestFile:
def get_multi_mode_filename(self) -> Path:
filename = self.file_path.stem
parent = self.file_path.parent
detailed_name = f"{filename}_{'_'.join(self.opts)}.txt"
prefix_less_opts = [re.sub(r"CS_(OPT|MODE)_", "", o).lower() for o in self.opts]
detailed_name = f"{filename}_{'_'.join(prefix_less_opts)}.txt"
detailed_name = re.sub(r"[+-]", "_", detailed_name)
out_path = parent.joinpath(detailed_name)
return Path(out_path)
@ -256,6 +257,7 @@ class MCUpdater:
):
self.symbolic_links = list()
self.arch = arch
self.arch_dir_name = TARGET_TO_DIR_NAME[self.arch]
self.test_dir_link_prefix = f"test_dir_{arch}_"
self.mc_dir = mc_dir
self.excluded = excluded if excluded else list()
@ -276,6 +278,11 @@ class MCUpdater:
if self.arch in self.conf["mandatory_options"]
else list()
)
self.default_endianess: str = (
self.conf["default_endianess"][self.arch]
if self.arch in self.conf["default_endianess"]
else ""
)
self.remove_options: str = (
self.conf["remove_options"][self.arch]
if self.arch in self.conf["remove_options"]
@ -339,10 +346,10 @@ class MCUpdater:
write_mode = "w+"
filename.parent.mkdir(parents=True, exist_ok=True)
if self.multi_mode and filename.exists():
raise ValueError(
f"The following file exists already: {filename}\n"
"This is not allowed in multi-mode."
log.warning(
f"The following file exists already: {filename}. This is might indicate a blind spot in testing."
)
overwritten += 1
elif not self.multi_mode and filename.exists():
log.debug(f"Overwrite: {filename}")
overwritten += 1
@ -350,6 +357,7 @@ class MCUpdater:
f.write(test.get_cs_testfile_content(only_test=(write_mode == "a")))
log.debug(f"Write {filename}")
files_written.add(filename)
print()
log.info(
f"Got {len(self.test_files)} test files.\n"
f"\t\tProcessed {file_cnt} files with {test_cnt} test cases.\n"
@ -363,6 +371,7 @@ class MCUpdater:
f"You have to use multi-mode to write them into distinct files.\n"
f"The current setting will only keep the last one written.\n"
f"See also: https://github.com/capstone-engine/capstone/issues/1992"
"If you already used multi-mode, there possibly is a blind spot for testing."
)
def build_test_options(self, options):
@ -372,9 +381,20 @@ class MCUpdater:
if opt in self.remove_options:
continue
elif opt in self.replace_option_map:
new_options.append(self.replace_option_map[opt])
new_options.extend(self.replace_option_map[opt])
else:
new_options.append(opt)
if (
not any(
[
True
for x in new_options
if x in ["CS_MODE_BIG_ENDIAN", "CS_MODE_LITTLE_ENDIAN"]
]
)
and self.default_endianess
):
new_options.append(self.default_endianess)
return new_options
def build_test_files(self, mc_cmds: list[LLVM_MC_Command]) -> list[TestFile]:
@ -479,7 +499,7 @@ class MCUpdater:
def gen_all(self):
log.info("Check prerequisites")
disas_tests = self.mc_dir.joinpath(f"Disassembler/{self.arch}")
disas_tests = self.mc_dir.joinpath(f"Disassembler/{self.arch_dir_name}")
test_paths = [disas_tests]
# Xtensa only defines assembly tests.
if self.arch == "Xtensa":

2
suite/auto-sync/src/autosync/Targets.py
View file

@ -38,6 +38,7 @@ TARGET_TO_IN_CODE_NAME = {
"Mips": "Mips",
"Xtensa": "Xtensa",
"TriCore": "TriCore",
"ARCH": "ARCH", # For testing
}
# Maps the name from ARCH_LLVM_NAMING to the directory name in LLVM
@ -51,4 +52,5 @@ TARGET_TO_DIR_NAME = {
"Mips": "Mips",
"Xtensa": "Xtensa",
"TriCore": "TriCore",
"ARCH": "ARCH", # For testing
}

16
suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/mode_mapping/test_systemz_mapping.txt.yaml
View file

@ -3,7 +3,7 @@ test_cases:
input:
bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0xae ]
arch: "CS_ARCH_SYSTEMZ"
options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13" ]
options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
@ -13,7 +13,7 @@ test_cases:
input:
bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0xae ]
arch: "CS_ARCH_SYSTEMZ"
options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13" ]
options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
@ -23,7 +23,7 @@ test_cases:
input:
bytes: [ 0xed, 0x00, 0x00, 0x00, 0x0f, 0xae ]
arch: "CS_ARCH_SYSTEMZ"
options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13" ]
options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
@ -33,7 +33,7 @@ test_cases:
input:
bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0xae ]
arch: "CS_ARCH_SYSTEMZ"
options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13" ]
options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_Z13", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
@ -43,7 +43,7 @@ test_cases:
input:
bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0xae ]
arch: "CS_ARCH_SYSTEMZ"
options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_ARCH11" ]
options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_ARCH11", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
@ -53,7 +53,7 @@ test_cases:
input:
bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0xae ]
arch: "CS_ARCH_SYSTEMZ"
options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_ARCH11" ]
options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_ARCH11", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
@ -63,7 +63,7 @@ test_cases:
input:
bytes: [ 0xed, 0x00, 0x00, 0x00, 0x0f, 0xae ]
arch: "CS_ARCH_SYSTEMZ"
options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_ARCH11" ]
options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_ARCH11", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
@ -73,7 +73,7 @@ test_cases:
input:
bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0xae ]
arch: "CS_ARCH_SYSTEMZ"
options: [ "CS_MODE_BIG_ENDIAN", "s390x-linux-gnu", "CS_MODE_SYSTEMZ_ARCH11" ]
options: [ "s390x-linux-gnu", "CS_MODE_SYSTEMZ_ARCH11", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-

3
suite/auto-sync/src/autosync/cpptranslator/arch_config.json
View file

@ -84,9 +84,6 @@
},{
"in": "{LLVM_ROOT}/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp",
"out": "PPCInstPrinter.c"
},{
"in": "{LLVM_ROOT}/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h",
"out": "PPCInstPrinter.h"
},{
"in": "{LLVM_ROOT}/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h",
"out": "PPCMCTargetDesc.h"

131
suite/auto-sync/src/autosync/mcupdater.json
View file

@ -11,17 +11,15 @@
},
"mandatory_options":
{
"SystemZ":
[
"CS_MODE_BIG_ENDIAN"
],
"Mips":
[
"CS_OPT_SYNTAX_NOREGNAME"
],
"PPC":
[
"CS_OPT_ONLY_OFFSET_BRANCH"
"CS_OPT_ONLY_OFFSET_BRANCH",
"CS_OPT_SYNTAX_NOREGNAME"
],
"ARM":
[
@ -32,6 +30,11 @@
"CS_OPT_ONLY_OFFSET_BRANCH"
]
},
"default_endianess":
{
"SystemZ": "CS_MODE_BIG_ENDIAN",
"PPC": "CS_MODE_BIG_ENDIAN"
},
"remove_options":
{
"Mips":
@ -49,63 +52,83 @@
"fp64",
"+virt",
"mt"
],
"PPC": [
"powerpc64-unknown-linux-gnu"
]
},
"replace_option_map":
{
"Mips":
{
"mips-unknown-linux": "CS_MODE_BIG_ENDIAN",
"mips-unknown-linux-gnu": "CS_MODE_BIG_ENDIAN",
"mips32-unknown-linux": "CS_MODE_BIG_ENDIAN",
"mips64-unknown-linux": "CS_MODE_BIG_ENDIAN",
"mips64-unknown-linux-gnu": "CS_MODE_BIG_ENDIAN",
"mips64el-unknown-linux": "CS_MODE_LITTLE_ENDIAN",
"mips64el-unknown-linux-gnu": "CS_MODE_LITTLE_ENDIAN",
"mipsel": "CS_MODE_LITTLE_ENDIAN",
"mipsel-unknown-linux": "CS_MODE_LITTLE_ENDIAN",
"mipsel-unknown-linux-gnu": "CS_MODE_LITTLE_ENDIAN",
"mips16": "CS_MODE_MIPS16",
"mips32": "CS_MODE_MIPS32",
"mips64": "CS_MODE_MIPS64",
"micromips": "CS_MODE_MICRO",
"mips1": "CS_MODE_MIPS1",
"mips2": "CS_MODE_MIPS2",
"mips32r2": "CS_MODE_MIPS32R2",
"mips32r3": "CS_MODE_MIPS32R3",
"mips32r5": "CS_MODE_MIPS32R5",
"mips32r6": "CS_MODE_MIPS32R6",
"mips3": "CS_MODE_MIPS3",
"mips4": "CS_MODE_MIPS4",
"mips5": "CS_MODE_MIPS5",
"mips64r2": "CS_MODE_MIPS64R2",
"mips64r3": "CS_MODE_MIPS64R3",
"mips64r5": "CS_MODE_MIPS64R5",
"mips64r6": "CS_MODE_MIPS64R6",
"octeon": "CS_MODE_OCTEON",
"octeon+": "CS_MODE_OCTEONP",
"nanomips": "CS_MODE_NANOMIPS",
"nms1": "CS_MODE_NMS1",
"i7200": "CS_MODE_I7200",
"mips_nofloat": "CS_MODE_MIPS_NOFLOAT",
"mips_ptr64": "CS_MODE_MIPS_PTR64"
"mips-unknown-linux": ["CS_MODE_BIG_ENDIAN"],
"mips-unknown-linux-gnu": ["CS_MODE_BIG_ENDIAN"],
"mips32-unknown-linux": ["CS_MODE_BIG_ENDIAN"],
"mips64-unknown-linux": ["CS_MODE_BIG_ENDIAN"],
"mips64-unknown-linux-gnu": ["CS_MODE_BIG_ENDIAN"],
"mips64el-unknown-linux": ["CS_MODE_LITTLE_ENDIAN"],
"mips64el-unknown-linux-gnu": ["CS_MODE_LITTLE_ENDIAN"],
"mipsel": ["CS_MODE_LITTLE_ENDIAN"],
"mipsel-unknown-linux": ["CS_MODE_LITTLE_ENDIAN"],
"mipsel-unknown-linux-gnu": ["CS_MODE_LITTLE_ENDIAN"],
"mips16": ["CS_MODE_MIPS16"],
"mips32": ["CS_MODE_MIPS32"],
"mips64": ["CS_MODE_MIPS64"],
"micromips": ["CS_MODE_MICRO"],
"mips1": ["CS_MODE_MIPS1"],
"mips2": ["CS_MODE_MIPS2"],
"mips32r2": ["CS_MODE_MIPS32R2"],
"mips32r3": ["CS_MODE_MIPS32R3"],
"mips32r5": ["CS_MODE_MIPS32R5"],
"mips32r6": ["CS_MODE_MIPS32R6"],
"mips3": ["CS_MODE_MIPS3"],
"mips4": ["CS_MODE_MIPS4"],
"mips5": ["CS_MODE_MIPS5"],
"mips64r2": ["CS_MODE_MIPS64R2"],
"mips64r3": ["CS_MODE_MIPS64R3"],
"mips64r5": ["CS_MODE_MIPS64R5"],
"mips64r6": ["CS_MODE_MIPS64R6"],
"octeon": ["CS_MODE_OCTEON"],
"octeon+": ["CS_MODE_OCTEONP"],
"nanomips": ["CS_MODE_NANOMIPS"],
"nms1": ["CS_MODE_NMS1"],
"i7200": ["CS_MODE_I7200"],
"mips_nofloat": ["CS_MODE_MIPS_NOFLOAT"],
"mips_ptr64": ["CS_MODE_MIPS_PTR64"]
},
"SystemZ": {
"arch8": "CS_MODE_SYSTEMZ_ARCH8",
"arch9": "CS_MODE_SYSTEMZ_ARCH9",
"arch10": "CS_MODE_SYSTEMZ_ARCH10",
"arch11": "CS_MODE_SYSTEMZ_ARCH11",
"arch12": "CS_MODE_SYSTEMZ_ARCH12",
"arch13": "CS_MODE_SYSTEMZ_ARCH13",
"arch14": "CS_MODE_SYSTEMZ_ARCH14",
"z10": "CS_MODE_SYSTEMZ_Z10",
"z196": "CS_MODE_SYSTEMZ_Z196",
"zec12": "CS_MODE_SYSTEMZ_ZEC12",
"z13": "CS_MODE_SYSTEMZ_Z13",
"z14": "CS_MODE_SYSTEMZ_Z14",
"z15": "CS_MODE_SYSTEMZ_Z15",
"z16": "CS_MODE_SYSTEMZ_Z16",
"generic": "CS_MODE_SYSTEMZ_GENERIC"
"arch8": ["CS_MODE_SYSTEMZ_ARCH8"],
"arch9": ["CS_MODE_SYSTEMZ_ARCH9"],
"arch10": ["CS_MODE_SYSTEMZ_ARCH10"],
"arch11": ["CS_MODE_SYSTEMZ_ARCH11"],
"arch12": ["CS_MODE_SYSTEMZ_ARCH12"],
"arch13": ["CS_MODE_SYSTEMZ_ARCH13"],
"arch14": ["CS_MODE_SYSTEMZ_ARCH14"],
"z10": ["CS_MODE_SYSTEMZ_Z10"],
"z196": ["CS_MODE_SYSTEMZ_Z196"],
"zec12": ["CS_MODE_SYSTEMZ_ZEC12"],
"z13": ["CS_MODE_SYSTEMZ_Z13"],
"z14": ["CS_MODE_SYSTEMZ_Z14"],
"z15": ["CS_MODE_SYSTEMZ_Z15"],
"z16": ["CS_MODE_SYSTEMZ_Z16"],
"generic": ["CS_MODE_SYSTEMZ_GENERIC"]
},
"PPC": {
"powerpc64-unknown-unknown": ["CS_MODE_BIG_ENDIAN", "CS_MODE_64"],
"powerpc64-unknown-linux": ["CS_MODE_BIG_ENDIAN", "CS_MODE_64"],
"powerpc64-unknown-aix-gnu": ["CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS"],
"powerpc64le-unknown-unknown": ["CS_MODE_LITTLE_ENDIAN", "CS_MODE_64"],
"powerpc64-ibm-aix-xcoff": ["CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS"],
"powerpc-unknown-aix-gnu": ["CS_MODE_BIG_ENDIAN", "CS_MODE_32", "CS_MODE_AIX_OS"],
"pwr7": ["CS_MODE_PWR7"],
"pwr8": ["CS_MODE_PWR8"],
"pwr9": ["CS_MODE_PWR9"],
"pwr10": ["CS_MODE_PWR10"],
"pwr10": ["CS_MODE_PWR10"],
"future": ["CS_MODE_PPC_ISA_FUTURE"],
"modern-aix-as": ["CS_MODE_MODERN_AIX_AS"],
"spe": ["CS_MODE_SPE"],
"a2": ["CS_MODE_BOOKE"]
}
}
}

70
suite/cstest/include/test_mapping.h
View file

@ -67,6 +67,7 @@ static const cs_enum_id_map test_mode_map[] = {
{ .str = "CS_MODE_16", .val = CS_MODE_16 },
{ .str = "CS_MODE_32", .val = CS_MODE_32 },
{ .str = "CS_MODE_64", .val = CS_MODE_64 },
{ .str = "CS_MODE_AIX_OS", .val = CS_MODE_AIX_OS },
{ .str = "CS_MODE_ARM", .val = CS_MODE_ARM },
{ .str = "CS_MODE_BIG_ENDIAN", .val = CS_MODE_BIG_ENDIAN },
{ .str = "CS_MODE_BOOKE", .val = CS_MODE_BOOKE },
@ -117,6 +118,7 @@ static const cs_enum_id_map test_mode_map[] = {
{ .str = "CS_MODE_MIPS64R6", .val = CS_MODE_MIPS64R6 },
{ .str = "CS_MODE_MIPS_NOFLOAT", .val = CS_MODE_MIPS_NOFLOAT },
{ .str = "CS_MODE_MIPS_PTR64", .val = CS_MODE_MIPS_PTR64 },
{ .str = "CS_MODE_MODERN_AIX_AS", .val = CS_MODE_MODERN_AIX_AS },
{ .str = "CS_MODE_MOS65XX_6502", .val = CS_MODE_MOS65XX_6502 },
{ .str = "CS_MODE_MOS65XX_65816", .val = CS_MODE_MOS65XX_65816 },
{ .str = "CS_MODE_MOS65XX_65816_LONG_M",
@ -127,11 +129,17 @@ static const cs_enum_id_map test_mode_map[] = {
.val = CS_MODE_MOS65XX_65816_LONG_X },
{ .str = "CS_MODE_MOS65XX_65C02", .val = CS_MODE_MOS65XX_65C02 },
{ .str = "CS_MODE_MOS65XX_W65C02", .val = CS_MODE_MOS65XX_W65C02 },
{ .str = "CS_MODE_MSYNC", .val = CS_MODE_MSYNC },
{ .str = "CS_MODE_NANOMIPS", .val = CS_MODE_NANOMIPS },
{ .str = "CS_MODE_NMS1", .val = CS_MODE_NMS1 },
{ .str = "CS_MODE_OCTEON", .val = CS_MODE_OCTEON },
{ .str = "CS_MODE_OCTEONP", .val = CS_MODE_OCTEONP },
{ .str = "CS_MODE_PPC_ISA_FUTURE", .val = CS_MODE_PPC_ISA_FUTURE },
{ .str = "CS_MODE_PS", .val = CS_MODE_PS },
{ .str = "CS_MODE_PWR10", .val = CS_MODE_PWR10 },
{ .str = "CS_MODE_PWR7", .val = CS_MODE_PWR7 },
{ .str = "CS_MODE_PWR8", .val = CS_MODE_PWR8 },
{ .str = "CS_MODE_PWR9", .val = CS_MODE_PWR9 },
{ .str = "CS_MODE_QPX", .val = CS_MODE_QPX },
{ .str = "CS_MODE_RISCV32", .val = CS_MODE_RISCV32 },
{ .str = "CS_MODE_RISCV64", .val = CS_MODE_RISCV64 },
@ -880,16 +888,55 @@ static const cs_enum_id_map cs_enum_map[] = {
{ .str = "PPC_BR_NOT_TAKEN", .val = PPC_BR_NOT_TAKEN },
{ .str = "PPC_BR_RESERVED", .val = PPC_BR_RESERVED },
{ .str = "PPC_BR_TAKEN", .val = PPC_BR_TAKEN },
{ .str = "PPC_FEATURE_HASBPERMD", .val = PPC_FEATURE_HASBPERMD },
{ .str = "PPC_FEATURE_HASEXTDIV", .val = PPC_FEATURE_HASEXTDIV },
{ .str = "PPC_FEATURE_HASFPU", .val = PPC_FEATURE_HASFPU },
{ .str = "PPC_FEATURE_HASICBT", .val = PPC_FEATURE_HASICBT },
{ .str = "PPC_FEATURE_HASONLYMSYNC", .val = PPC_FEATURE_HASONLYMSYNC },
{ .str = "PPC_FEATURE_HASPARTWORDATOMICS",
.val = PPC_FEATURE_HASPARTWORDATOMICS },
{ .str = "PPC_FEATURE_HASPS", .val = PPC_FEATURE_HASPS },
{ .str = "PPC_FEATURE_HASQPX", .val = PPC_FEATURE_HASQPX },
{ .str = "PPC_FEATURE_HASQUADWORDATOMICS",
.val = PPC_FEATURE_HASQUADWORDATOMICS },
{ .str = "PPC_FEATURE_HASSPE", .val = PPC_FEATURE_HASSPE },
{ .str = "PPC_FEATURE_HASSYNC", .val = PPC_FEATURE_HASSYNC },
{ .str = "PPC_FEATURE_IN32BITMODE", .val = PPC_FEATURE_IN32BITMODE },
{ .str = "PPC_FEATURE_IN64BITMODE", .val = PPC_FEATURE_IN64BITMODE },
{ .str = "PPC_FEATURE_ISAIX", .val = PPC_FEATURE_ISAIX },
{ .str = "PPC_FEATURE_ISBOOKE", .val = PPC_FEATURE_ISBOOKE },
{ .str = "PPC_FEATURE_ISE500", .val = PPC_FEATURE_ISE500 },
{ .str = "PPC_FEATURE_ISISA2_06", .val = PPC_FEATURE_ISISA2_06 },
{ .str = "PPC_FEATURE_ISISA2_07", .val = PPC_FEATURE_ISISA2_07 },
{ .str = "PPC_FEATURE_ISISA3_0", .val = PPC_FEATURE_ISISA3_0 },
{ .str = "PPC_FEATURE_ISISAFUTURE", .val = PPC_FEATURE_ISISAFUTURE },
{ .str = "PPC_FEATURE_ISNOTBOOKE", .val = PPC_FEATURE_ISNOTBOOKE },
{ .str = "PPC_FEATURE_ISNOTISA3_1", .val = PPC_FEATURE_ISNOTISA3_1 },
{ .str = "PPC_FEATURE_ISNOTISAFUTURE",
.val = PPC_FEATURE_ISNOTISAFUTURE },
{ .str = "PPC_FEATURE_ISPPC4XX", .val = PPC_FEATURE_ISPPC4XX },
{ .str = "PPC_FEATURE_ISPPC6XX", .val = PPC_FEATURE_ISPPC6XX },
{ .str = "PPC_FEATURE_MODERNAS", .val = PPC_FEATURE_MODERNAS },
{ .str = "PPC_FEATURE_NANSFPMATH", .val = PPC_FEATURE_NANSFPMATH },
{ .str = "PPC_FEATURE_NONANSFPMATH", .val = PPC_FEATURE_NONANSFPMATH },
{ .str = "PPC_FEATURE_NOTAIX", .val = PPC_FEATURE_NOTAIX },
{ .str = "PPC_FEATURE_PCRELATIVEMEMOPS",
.val = PPC_FEATURE_PCRELATIVEMEMOPS },
{ .str = "PPC_GRP_BRANCH_RELATIVE", .val = PPC_GRP_BRANCH_RELATIVE },
{ .str = "PPC_GRP_CALL", .val = PPC_GRP_CALL },
{ .str = "PPC_GRP_INT", .val = PPC_GRP_INT },
{ .str = "PPC_GRP_IRET", .val = PPC_GRP_IRET },
{ .str = "PPC_GRP_JUMP", .val = PPC_GRP_JUMP },
{ .str = "PPC_GRP_PRIVILEGE", .val = PPC_GRP_PRIVILEGE },
{ .str = "PPC_GRP_RET", .val = PPC_GRP_RET },
{ .str = "PPC_INSN_FORM_AFORM_1", .val = PPC_INSN_FORM_AFORM_1 },
{ .str = "PPC_INSN_FORM_AFORM_4", .val = PPC_INSN_FORM_AFORM_4 },
{ .str = "PPC_INSN_FORM_BFORM", .val = PPC_INSN_FORM_BFORM },
{ .str = "PPC_INSN_FORM_BFORM_3", .val = PPC_INSN_FORM_BFORM_3 },
{ .str = "PPC_INSN_FORM_BFORM_3_AT", .val = PPC_INSN_FORM_BFORM_3_AT },
{ .str = "PPC_INSN_FORM_DCBZL_FORM", .val = PPC_INSN_FORM_DCBZL_FORM },
{ .str = "PPC_INSN_FORM_DCB_FORM", .val = PPC_INSN_FORM_DCB_FORM },
{ .str = "PPC_INSN_FORM_DCB_FORM_HINT",
.val = PPC_INSN_FORM_DCB_FORM_HINT },
{ .str = "PPC_INSN_FORM_DFORM_1", .val = PPC_INSN_FORM_DFORM_1 },
{ .str = "PPC_INSN_FORM_DFORM_2_R0", .val = PPC_INSN_FORM_DFORM_2_R0 },
{ .str = "PPC_INSN_FORM_DFORM_4", .val = PPC_INSN_FORM_DFORM_4 },
{ .str = "PPC_INSN_FORM_DFORM_5", .val = PPC_INSN_FORM_DFORM_5 },
@ -913,6 +960,7 @@ static const cs_enum_id_map cs_enum_map[] = {
{ .str = "PPC_INSN_FORM_MDFORM_1", .val = PPC_INSN_FORM_MDFORM_1 },
{ .str = "PPC_INSN_FORM_MDSFORM_1", .val = PPC_INSN_FORM_MDSFORM_1 },
{ .str = "PPC_INSN_FORM_MFORM_1", .val = PPC_INSN_FORM_MFORM_1 },
{ .str = "PPC_INSN_FORM_MFORM_2", .val = PPC_INSN_FORM_MFORM_2 },
{ .str = "PPC_INSN_FORM_PSFORM_C", .val = PPC_INSN_FORM_PSFORM_C },
{ .str = "PPC_INSN_FORM_PSFORM_QD", .val = PPC_INSN_FORM_PSFORM_QD },
{ .str = "PPC_INSN_FORM_PSFORM_QI", .val = PPC_INSN_FORM_PSFORM_QI },
@ -965,14 +1013,24 @@ static const cs_enum_id_map cs_enum_map[] = {
.val = PPC_INSN_FORM_XFORM_BASE_R3XO },
{ .str = "PPC_INSN_FORM_XFORM_BASE_R3XO_SWAPPED",
.val = PPC_INSN_FORM_XFORM_BASE_R3XO_SWAPPED },
{ .str = "PPC_INSN_FORM_XFORM_BF3_UIM6_FRB5",
.val = PPC_INSN_FORM_XFORM_BF3_UIM6_FRB5 },
{ .str = "PPC_INSN_FORM_XFORM_HTM0", .val = PPC_INSN_FORM_XFORM_HTM0 },
{ .str = "PPC_INSN_FORM_XFORM_HTM1", .val = PPC_INSN_FORM_XFORM_HTM1 },
{ .str = "PPC_INSN_FORM_XFORM_HTM2", .val = PPC_INSN_FORM_XFORM_HTM2 },
{ .str = "PPC_INSN_FORM_XFORM_HTM3", .val = PPC_INSN_FORM_XFORM_HTM3 },
{ .str = "PPC_INSN_FORM_XFORM_ICBT", .val = PPC_INSN_FORM_XFORM_ICBT },
{ .str = "PPC_INSN_FORM_XFORM_IMM2_IMM2",
.val = PPC_INSN_FORM_XFORM_IMM2_IMM2 },
{ .str = "PPC_INSN_FORM_XFORM_IMM3_IMM2",
.val = PPC_INSN_FORM_XFORM_IMM3_IMM2 },
{ .str = "PPC_INSN_FORM_XFORM_MBAR", .val = PPC_INSN_FORM_XFORM_MBAR },
{ .str = "PPC_INSN_FORM_XFORM_MTMSR",
.val = PPC_INSN_FORM_XFORM_MTMSR },
{ .str = "PPC_INSN_FORM_XFORM_S1_FRTB5",
.val = PPC_INSN_FORM_XFORM_S1_FRTB5 },
{ .str = "PPC_INSN_FORM_XFORM_SP2_FRTB5",
.val = PPC_INSN_FORM_XFORM_SP2_FRTB5 },
{ .str = "PPC_INSN_FORM_XFORM_SR", .val = PPC_INSN_FORM_XFORM_SR },
{ .str = "PPC_INSN_FORM_XFORM_SRIN", .val = PPC_INSN_FORM_XFORM_SRIN },
{ .str = "PPC_INSN_FORM_XFORM_TLBWS",
@ -1031,9 +1089,17 @@ static const cs_enum_id_map cs_enum_map[] = {
{ .str = "PPC_INSN_FORM_X_BF3_RS5_RS5",
.val = PPC_INSN_FORM_X_BF3_RS5_RS5 },
{ .str = "PPC_INSN_FORM_X_RD6_IMM8", .val = PPC_INSN_FORM_X_RD6_IMM8 },
{ .str = "PPC_INSN_FORM_Z22FORM_BF3_FRA5_DCM6",
.val = PPC_INSN_FORM_Z22FORM_BF3_FRA5_DCM6 },
{ .str = "PPC_INSN_FORM_Z22FORM_FRTA5_SH6",
.val = PPC_INSN_FORM_Z22FORM_FRTA5_SH6 },
{ .str = "PPC_INSN_FORM_Z23FORM_1", .val = PPC_INSN_FORM_Z23FORM_1 },
{ .str = "PPC_INSN_FORM_Z23FORM_3", .val = PPC_INSN_FORM_Z23FORM_3 },
{ .str = "PPC_INSN_FORM_Z23FORM_8", .val = PPC_INSN_FORM_Z23FORM_8 },
{ .str = "PPC_INSN_FORM_Z23FORM_FRTAB5_RMC2",
.val = PPC_INSN_FORM_Z23FORM_FRTAB5_RMC2 },
{ .str = "PPC_INSN_FORM_Z23FORM_FRTB5_R1_RMC2",
.val = PPC_INSN_FORM_Z23FORM_FRTB5_R1_RMC2 },
{ .str = "PPC_INSN_FORM_Z23FORM_RTAB5_CY2",
.val = PPC_INSN_FORM_Z23FORM_RTAB5_CY2 },
{ .str = "PPC_OP_IMM", .val = PPC_OP_IMM },

40
tests/MC/PowerPC/dcbt_only_offset_branch_syntax_noregname_big_endian_64_a2.txt.yaml Normal file
View file

@ -0,0 +1,40 @@
test_cases:
-
input:
bytes: [ 0x7c, 0x02, 0x1a, 0x2c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "dcbt 2, 3"
-
input:
bytes: [ 0x7c, 0x02, 0x19, 0xec ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "dcbtst 2, 3"
-
input:
bytes: [ 0x7d, 0x42, 0x1a, 0x2c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "dcbt 10, 2, 3"
-
input:
bytes: [ 0x7d, 0x42, 0x19, 0xec ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "dcbtst 10, 2, 3"

40
tests/MC/PowerPC/dcbt_only_offset_branch_syntax_noregname_big_endian_64_booke.txt.yaml Normal file
View file

@ -0,0 +1,40 @@
test_cases:
-
input:
bytes: [ 0x7c, 0x02, 0x1a, 0x2c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "dcbt 2, 3"
-
input:
bytes: [ 0x7c, 0x02, 0x19, 0xec ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "dcbtst 2, 3"
-
input:
bytes: [ 0x7d, 0x42, 0x1a, 0x2c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "dcbt 10, 2, 3"
-
input:
bytes: [ 0x7d, 0x42, 0x19, 0xec ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "dcbtst 10, 2, 3"

40
tests/MC/PowerPC/dcbt_only_offset_branch_syntax_noregname_big_endian_64_pwr7.txt.yaml Normal file
View file

@ -0,0 +1,40 @@
test_cases:
-
input:
bytes: [ 0x7c, 0x02, 0x1a, 0x2c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbt 2, 3"
-
input:
bytes: [ 0x7c, 0x02, 0x19, 0xec ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbtst 2, 3"
-
input:
bytes: [ 0x7d, 0x42, 0x1a, 0x2c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbt 2, 3, 10"
-
input:
bytes: [ 0x7d, 0x42, 0x19, 0xec ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbtst 2, 3, 10"

150
tests/MC/PowerPC/ppc32_extpid_e500_only_offset_branch_syntax_noregname_powerpc_unknown_unknown_big_endian.txt.yaml Normal file
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@ -0,0 +1,150 @@
test_cases:
-
input:
bytes: [ 0x7c, 0x22, 0x18, 0xbe ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lbepx 1, 2, 3"
-
input:
bytes: [ 0x7c, 0x85, 0x34, 0xbe ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lfdepx 4, 5, 6"
-
input:
bytes: [ 0x7c, 0xe8, 0x4a, 0x3e ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lhepx 7, 8, 9"
-
input:
bytes: [ 0x7d, 0x4b, 0x60, 0x3e ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lwepx 10, 11, 12"
-
input:
bytes: [ 0x7d, 0xae, 0x79, 0xbe ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stbepx 13, 14, 15"
-
input:
bytes: [ 0x7e, 0x11, 0x95, 0xbe ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stfdepx 16, 17, 18"
-
input:
bytes: [ 0x7e, 0x74, 0xab, 0x3e ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "sthepx 19, 20, 21"
-
input:
bytes: [ 0x7e, 0xd7, 0xc1, 0x3e ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stwepx 22, 23, 24"
-
input:
bytes: [ 0x7c, 0x19, 0xd0, 0xfe ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dcbfep 25, 26"
-
input:
bytes: [ 0x7c, 0x1b, 0xe0, 0x7e ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dcbstep 27, 28"
-
input:
bytes: [ 0x7f, 0xbe, 0xfa, 0x7e ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dcbtep 29, 30, 31"
-
input:
bytes: [ 0x7c, 0x01, 0x11, 0xfe ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dcbtstep 0, 1, 2"
-
input:
bytes: [ 0x7c, 0x03, 0x27, 0xfe ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dcbzep 3, 4"
-
input:
bytes: [ 0x7c, 0x25, 0x37, 0xfe ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dcbzlep 5, 6"
-
input:
bytes: [ 0x7c, 0x07, 0x47, 0xbe ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-unknown", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "icbiep 7, 8"

36
tests/MC/PowerPC/ppc64-encoding-bookII.s.yaml → tests/MC/PowerPC/ppc64-encoding-bookii.s.yaml
View file

@ -3,7 +3,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x02, 0x1f, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -12,7 +12,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x02, 0x1a, 0x2c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -21,7 +21,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x02, 0x19, 0xec ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -30,7 +30,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x02, 0x1f, 0xec ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -39,7 +39,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x02, 0x18, 0x6c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -48,7 +48,7 @@ test_cases:
input:
bytes: [ 0x4c, 0x00, 0x01, 0x2c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -57,7 +57,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x43, 0x21, 0x2d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -66,7 +66,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x43, 0x21, 0xad ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -75,7 +75,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x00, 0x06, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -84,7 +84,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x02, 0x18, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -93,7 +93,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x43, 0x20, 0x28 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -102,7 +102,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x43, 0x20, 0xa8 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -111,7 +111,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x00, 0x04, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -120,7 +120,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x20, 0x04, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -129,7 +129,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x40, 0x04, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -138,7 +138,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x5b, 0x1a, 0xe6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -147,7 +147,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x4c, 0x42, 0xe6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-
@ -156,7 +156,7 @@ test_cases:
input:
bytes: [ 0x7c, 0x4d, 0x42, 0xe6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_PWR7", "CS_MODE_64" ]
expected:
insns:
-

0
tests/MC/PowerPC/ppc64-encoding-bookIII.s.yaml → tests/MC/PowerPC/ppc64-encoding-bookiii.s.yaml
View file

338
tests/MC/PowerPC/ppc64-encoding-vmx.s.yaml
View file

File diff suppressed because it is too large Load diff

100
tests/MC/PowerPC/ppc64_encoding_4xx_only_offset_branch_syntax_noregname_big_endian_64_pwr7.txt.yaml Normal file
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@ -0,0 +1,100 @@
test_cases:
-
input:
bytes: [ 0x7c, 0x72, 0x2a, 0x86 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mfdcr 3, 178"
-
input:
bytes: [ 0x7c, 0x72, 0x2b, 0x86 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtdcr 178, 3"
-
input:
bytes: [ 0x7c, 0x43, 0x07, 0x64 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "tlbrehi 2, 3"
-
input:
bytes: [ 0x7c, 0x43, 0x0f, 0x64 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "tlbrelo 2, 3"
-
input:
bytes: [ 0x7c, 0x43, 0x07, 0xa4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "tlbwehi 2, 3"
-
input:
bytes: [ 0x7c, 0x43, 0x0f, 0xa4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "tlbwelo 2, 3"
-
input:
bytes: [ 0x7c, 0x43, 0x0f, 0x24 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "tlbsx 2, 3, 1"
-
input:
bytes: [ 0x7c, 0x43, 0x0f, 0x25 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "tlbsx. 2, 3, 1"
-
input:
bytes: [ 0x7c, 0x05, 0x33, 0x8c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dccci 5, 6"
-
input:
bytes: [ 0x7c, 0x05, 0x37, 0x8c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "iccci 5, 6"

20
tests/MC/PowerPC/ppc64_encoding_6xx_only_offset_branch_syntax_noregname_big_endian_64_pwr7.txt.yaml Normal file
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@ -0,0 +1,20 @@
test_cases:
-
input:
bytes: [ 0x7c, 0x00, 0x27, 0xa4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "tlbld 4"
-
input:
bytes: [ 0x7c, 0x00, 0x27, 0xe4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "tlbli 4"

430
tests/MC/PowerPC/ppc64_encoding_bookii_only_offset_branch_syntax_noregname_big_endian_64_pwr7.txt.yaml Normal file
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@ -0,0 +1,430 @@
test_cases:
-
input:
bytes: [ 0x7c, 0x02, 0x1f, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "icbi 2, 3"
-
input:
bytes: [ 0x7c, 0x05, 0xf8, 0x2c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "icbt 0, 5, 31"
-
input:
bytes: [ 0x7c, 0x02, 0x1a, 0x2c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbt 2, 3"
-
input:
bytes: [ 0x7c, 0x02, 0x19, 0xec ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbtst 2, 3"
-
input:
bytes: [ 0x7d, 0x42, 0x1a, 0x2c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbt 2, 3, 10"
-
input:
bytes: [ 0x7d, 0x42, 0x19, 0xec ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbtst 2, 3, 10"
-
input:
bytes: [ 0x7c, 0x02, 0x1f, 0xec ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbz 2, 3"
-
input:
bytes: [ 0x7c, 0x02, 0x18, 0x6c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbst 2, 3"
-
input:
bytes: [ 0x4c, 0x00, 0x01, 0x2c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "isync"
-
input:
bytes: [ 0x7c, 0x43, 0x21, 0x2d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "stwcx. 2, 3, 4"
-
input:
bytes: [ 0x7c, 0x43, 0x21, 0xad ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "stdcx. 2, 3, 4"
-
input:
bytes: [ 0x7c, 0x43, 0x21, 0x6d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "stqcx. 2, 3, 4"
-
input:
bytes: [ 0x7f, 0x9e, 0xf9, 0x6d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "stqcx. 28, 30, 31"
-
input:
bytes: [ 0x7c, 0x43, 0xe5, 0x8c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "stwat 2, 3, 28"
-
input:
bytes: [ 0x7c, 0x43, 0xe5, 0xcc ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "stdat 2, 3, 28"
-
input:
bytes: [ 0x7c, 0x40, 0x04, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ptesync"
-
input:
bytes: [ 0x7c, 0x00, 0x06, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "eieio"
-
input:
bytes: [ 0x7c, 0x40, 0x00, 0x3c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "waitimpl"
-
input:
bytes: [ 0x7c, 0x20, 0x06, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "mbar 1"
-
input:
bytes: [ 0x7c, 0x02, 0x18, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbf 2, 3"
-
input:
bytes: [ 0x7c, 0x22, 0x18, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbfl 2, 3"
-
input:
bytes: [ 0x7c, 0x62, 0x18, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcbflp 2, 3"
-
input:
bytes: [ 0x7c, 0x43, 0x20, 0x68 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "lbarx 2, 3, 4"
-
input:
bytes: [ 0x7c, 0x43, 0x20, 0xe8 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "lharx 2, 3, 4"
-
input:
bytes: [ 0x7c, 0x43, 0x20, 0x28 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lwarx 2, 3, 4"
-
input:
bytes: [ 0x7c, 0x43, 0x20, 0xa8 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ldarx 2, 3, 4"
-
input:
bytes: [ 0x7c, 0x43, 0x22, 0x28 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lqarx 2, 3, 4"
-
input:
bytes: [ 0x7f, 0x9e, 0xfa, 0x28 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lqarx 28, 30, 31"
-
input:
bytes: [ 0x7c, 0x43, 0x20, 0x69 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "lbarx 2, 3, 4, 1"
-
input:
bytes: [ 0x7c, 0x43, 0x20, 0xe9 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "lharx 2, 3, 4, 1"
-
input:
bytes: [ 0x7c, 0x43, 0x20, 0x29 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lwarx 2, 3, 4, 1"
-
input:
bytes: [ 0x7c, 0x43, 0x20, 0xa9 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ldarx 2, 3, 4, 1"
-
input:
bytes: [ 0x7c, 0x43, 0x22, 0x29 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lqarx 2, 3, 4, 1"
-
input:
bytes: [ 0x7f, 0x9e, 0xfa, 0x29 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lqarx 28, 30, 31, 1"
-
input:
bytes: [ 0x7c, 0x43, 0xe4, 0x8c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lwat 2, 3, 28"
-
input:
bytes: [ 0x7c, 0x43, 0xe4, 0xcc ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ldat 2, 3, 28"
-
input:
bytes: [ 0x7c, 0x00, 0x04, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "sync"
-
input:
bytes: [ 0x7c, 0x20, 0x04, 0xac ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lwsync"
-
input:
bytes: [ 0x7c, 0x00, 0x00, 0x3c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "wait"
-
input:
bytes: [ 0x7c, 0x20, 0x00, 0x3c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "waitrsv"
-
input:
bytes: [ 0x7c, 0x5b, 0x1a, 0xe6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mftb 2, 123"
-
input:
bytes: [ 0x7c, 0x4c, 0x42, 0xe6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mftb 2, 268"
-
input:
bytes: [ 0x7c, 0x4d, 0x42, 0xe6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mftbu 2"

460
tests/MC/PowerPC/ppc64_encoding_bookiii_only_offset_branch_syntax_noregname_big_endian_64_pwr7.txt.yaml Normal file
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@ -0,0 +1,460 @@
test_cases:
-
input:
bytes: [ 0x4c, 0x00, 0x02, 0x24 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "hrfid"
-
input:
bytes: [ 0x4c, 0x00, 0x03, 0x64 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "nap"
-
input:
bytes: [ 0x7c, 0x80, 0x01, 0x24 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtmsr 4"
-
input:
bytes: [ 0x7c, 0x81, 0x01, 0x24 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtmsr 4, 1"
-
input:
bytes: [ 0x7c, 0x80, 0x00, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mfmsr 4"
-
input:
bytes: [ 0x7c, 0x80, 0x01, 0x64 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtmsrd 4"
-
input:
bytes: [ 0x7c, 0x81, 0x01, 0x64 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtmsrd 4, 1"
-
input:
bytes: [ 0x7c, 0x90, 0x42, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mfspr 4, 272"
-
input:
bytes: [ 0x7c, 0x91, 0x42, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mfspr 4, 273"
-
input:
bytes: [ 0x7c, 0x92, 0x42, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mfspr 4, 274"
-
input:
bytes: [ 0x7c, 0x93, 0x42, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mfspr 4, 275"
-
input:
bytes: [ 0x7c, 0x90, 0x43, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtspr 272, 4"
-
input:
bytes: [ 0x7c, 0x91, 0x43, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtspr 273, 4"
-
input:
bytes: [ 0x7c, 0x92, 0x43, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtspr 274, 4"
-
input:
bytes: [ 0x7c, 0x93, 0x43, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtspr 275, 4"
-
input:
bytes: [ 0x7c, 0x98, 0x43, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtasr 4"
-
input:
bytes: [ 0x7c, 0x96, 0x02, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mfdec 4"
-
input:
bytes: [ 0x7c, 0x96, 0x03, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtdec 4"
-
input:
bytes: [ 0x7c, 0x9f, 0x42, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mfpvr 4"
-
input:
bytes: [ 0x7c, 0x99, 0x02, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mfsdr1 4"
-
input:
bytes: [ 0x7c, 0x99, 0x03, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtsdr1 4"
-
input:
bytes: [ 0x7c, 0x9a, 0x02, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mfsrr0 4"
-
input:
bytes: [ 0x7c, 0x9a, 0x03, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtsrr0 4"
-
input:
bytes: [ 0x7c, 0x9b, 0x02, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mfsrr1 4"
-
input:
bytes: [ 0x7c, 0x9b, 0x03, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtsrr1 4"
-
input:
bytes: [ 0x7c, 0x00, 0x23, 0x64 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "slbie 4"
-
input:
bytes: [ 0x7c, 0x80, 0x2b, 0x24 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "slbmte 4, 5"
-
input:
bytes: [ 0x7c, 0x80, 0x2f, 0x26 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "slbmfee 4, 5"
-
input:
bytes: [ 0x7c, 0x40, 0x1e, 0xa6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "slbmfev 2, 3"
-
input:
bytes: [ 0x7c, 0x00, 0x03, 0xe4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "slbia"
-
input:
bytes: [ 0x7c, 0x00, 0x04, 0x6c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "tlbsync"
-
input:
bytes: [ 0x7c, 0x00, 0x22, 0x24 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "tlbiel 4"
-
input:
bytes: [ 0x7c, 0x00, 0x22, 0x64 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "tlbie 4"
-
input:
bytes: [ 0x4c, 0x00, 0x00, 0x64 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "rfi"
-
input:
bytes: [ 0x4c, 0x00, 0x00, 0x66 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "rfci"
-
input:
bytes: [ 0x7d, 0x80, 0x01, 0x06 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "wrtee 12"
-
input:
bytes: [ 0x7c, 0x00, 0x01, 0x46 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "wrteei 0"
-
input:
bytes: [ 0x7c, 0x00, 0x81, 0x46 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "wrteei 1"
-
input:
bytes: [ 0x7c, 0x00, 0x07, 0x64 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "tlbre"
-
input:
bytes: [ 0x7c, 0x00, 0x07, 0xa4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "tlbwe"
-
input:
bytes: [ 0x7c, 0x0b, 0x66, 0x24 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "tlbivax 11, 12"
-
input:
bytes: [ 0x7c, 0x0b, 0x67, 0x24 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7", "CS_MODE_BOOKE" ]
expected:
insns:
-
asm_text: "tlbsx 11, 12"
-
input:
bytes: [ 0x7c, 0xb0, 0x62, 0x9c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mfpmr 5, 400"
-
input:
bytes: [ 0x7c, 0xd0, 0x63, 0x9c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "mtpmr 400, 6"
-
input:
bytes: [ 0x7c, 0x00, 0x41, 0xcc ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "icblc 0, 0, 8"
-
input:
bytes: [ 0x7c, 0x00, 0x4b, 0xcc ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "icbtls 0, 0, 9"

920
tests/MC/PowerPC/ppc64_encoding_dfp_only_offset_branch_syntax_noregname_big_endian_64_pwr7.txt.yaml Normal file
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@ -0,0 +1,920 @@
test_cases:
-
input:
bytes: [ 0xec, 0x43, 0x20, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dadd 2, 3, 4"
-
input:
bytes: [ 0xec, 0x43, 0x20, 0x05 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dadd. 2, 3, 4"
-
input:
bytes: [ 0xfc, 0x46, 0x20, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "daddq 2, 6, 4"
-
input:
bytes: [ 0xfc, 0x46, 0x20, 0x05 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "daddq. 2, 6, 4"
-
input:
bytes: [ 0xec, 0x43, 0x24, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dsub 2, 3, 4"
-
input:
bytes: [ 0xec, 0x43, 0x24, 0x05 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dsub. 2, 3, 4"
-
input:
bytes: [ 0xfc, 0x46, 0x24, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dsubq 2, 6, 4"
-
input:
bytes: [ 0xfc, 0x46, 0x24, 0x05 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dsubq. 2, 6, 4"
-
input:
bytes: [ 0xec, 0x43, 0x20, 0x44 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dmul 2, 3, 4"
-
input:
bytes: [ 0xec, 0x43, 0x20, 0x45 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dmul. 2, 3, 4"
-
input:
bytes: [ 0xfc, 0x46, 0x20, 0x44 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dmulq 2, 6, 4"
-
input:
bytes: [ 0xfc, 0x46, 0x20, 0x45 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dmulq. 2, 6, 4"
-
input:
bytes: [ 0xec, 0x43, 0x24, 0x44 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ddiv 2, 3, 4"
-
input:
bytes: [ 0xec, 0x43, 0x24, 0x45 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ddiv. 2, 3, 4"
-
input:
bytes: [ 0xfc, 0x46, 0x24, 0x44 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ddivq 2, 6, 4"
-
input:
bytes: [ 0xfc, 0x46, 0x24, 0x45 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ddivq. 2, 6, 4"
-
input:
bytes: [ 0xed, 0x06, 0x25, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcmpu 2, 6, 4"
-
input:
bytes: [ 0xfd, 0x06, 0x25, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcmpuq 2, 6, 4"
-
input:
bytes: [ 0xed, 0x06, 0x21, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcmpo 2, 6, 4"
-
input:
bytes: [ 0xfd, 0x06, 0x21, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcmpoq 2, 6, 4"
-
input:
bytes: [ 0xed, 0x0f, 0x26, 0x86 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dquai 15, 8, 4, 3"
-
input:
bytes: [ 0xed, 0x0f, 0x26, 0x87 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dquai. 15, 8, 4, 3"
-
input:
bytes: [ 0xfd, 0x0f, 0x26, 0x86 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dquaiq 15, 8, 4, 3"
-
input:
bytes: [ 0xfd, 0x0f, 0x26, 0x87 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dquaiq. 15, 8, 4, 3"
-
input:
bytes: [ 0xec, 0xef, 0x24, 0x06 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dqua 7, 15, 4, 2"
-
input:
bytes: [ 0xec, 0xef, 0x24, 0x07 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dqua. 7, 15, 4, 2"
-
input:
bytes: [ 0xfc, 0xce, 0x24, 0x06 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dquaq 6, 14, 4, 2"
-
input:
bytes: [ 0xfc, 0xce, 0x24, 0x07 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dquaq. 6, 14, 4, 2"
-
input:
bytes: [ 0xed, 0x0c, 0x34, 0x46 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drrnd 8, 12, 6, 2"
-
input:
bytes: [ 0xed, 0x0c, 0x34, 0x47 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drrnd. 8, 12, 6, 2"
-
input:
bytes: [ 0xfd, 0x0c, 0x34, 0x46 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drrndq 8, 12, 6, 2"
-
input:
bytes: [ 0xfd, 0x0c, 0x34, 0x47 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drrndq. 8, 12, 6, 2"
-
input:
bytes: [ 0xed, 0x01, 0x56, 0xc6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drintx 1, 8, 10, 3"
-
input:
bytes: [ 0xed, 0x00, 0x56, 0xc7 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drintx. 0, 8, 10, 3"
-
input:
bytes: [ 0xfd, 0x00, 0x56, 0xc6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drintxq 0, 8, 10, 3"
-
input:
bytes: [ 0xfd, 0x01, 0x56, 0xc7 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drintxq. 1, 8, 10, 3"
-
input:
bytes: [ 0xed, 0x40, 0x35, 0xc6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drintn 0, 10, 6, 2"
-
input:
bytes: [ 0xed, 0x41, 0x35, 0xc7 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drintn. 1, 10, 6, 2"
-
input:
bytes: [ 0xfd, 0x41, 0x35, 0xc6 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drintnq 1, 10, 6, 2"
-
input:
bytes: [ 0xfd, 0x40, 0x35, 0xc7 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drintnq. 0, 10, 6, 2"
-
input:
bytes: [ 0xed, 0x00, 0x12, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dctdp 8, 2"
-
input:
bytes: [ 0xed, 0x00, 0x12, 0x05 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dctdp. 8, 2"
-
input:
bytes: [ 0xfd, 0x00, 0x12, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dctqpq 8, 2"
-
input:
bytes: [ 0xfd, 0x00, 0x12, 0x05 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dctqpq. 8, 2"
-
input:
bytes: [ 0xee, 0x80, 0x46, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drsp 20, 8"
-
input:
bytes: [ 0xee, 0x80, 0x46, 0x05 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drsp. 20, 8"
-
input:
bytes: [ 0xfe, 0x80, 0x46, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drdpq 20, 8"
-
input:
bytes: [ 0xfe, 0x80, 0x46, 0x05 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "drdpq. 20, 8"
-
input:
bytes: [ 0xed, 0x80, 0x3e, 0x44 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcffix 12, 7"
-
input:
bytes: [ 0xed, 0x80, 0x3e, 0x45 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcffix. 12, 7"
-
input:
bytes: [ 0xfd, 0x80, 0x46, 0x44 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcffixq 12, 8"
-
input:
bytes: [ 0xfd, 0x80, 0x46, 0x45 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcffixq. 12, 8"
-
input:
bytes: [ 0xfe, 0x40, 0xa7, 0xc4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dcffixqq 18, 20"
-
input:
bytes: [ 0xed, 0x00, 0x22, 0x44 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dctfix 8, 4"
-
input:
bytes: [ 0xed, 0x00, 0x22, 0x45 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dctfix. 8, 4"
-
input:
bytes: [ 0xfd, 0x00, 0x22, 0x44 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dctfixq 8, 4"
-
input:
bytes: [ 0xfd, 0x00, 0x22, 0x45 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dctfixq. 8, 4"
-
input:
bytes: [ 0xfd, 0x01, 0x57, 0xc4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dctfixqq 8, 10"
-
input:
bytes: [ 0xed, 0x00, 0x52, 0x84 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ddedpd 0, 8, 10"
-
input:
bytes: [ 0xed, 0x00, 0x52, 0x85 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ddedpd. 0, 8, 10"
-
input:
bytes: [ 0xfd, 0x08, 0x52, 0x84 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ddedpdq 1, 8, 10"
-
input:
bytes: [ 0xfd, 0x08, 0x52, 0x85 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ddedpdq. 1, 8, 10"
-
input:
bytes: [ 0xed, 0x90, 0x86, 0x84 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "denbcd 1, 12, 16"
-
input:
bytes: [ 0xed, 0x80, 0x86, 0x85 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "denbcd. 0, 12, 16"
-
input:
bytes: [ 0xfd, 0x90, 0x86, 0x84 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "denbcdq 1, 12, 16"
-
input:
bytes: [ 0xfd, 0x80, 0x86, 0x85 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "denbcdq. 0, 12, 16"
-
input:
bytes: [ 0xed, 0x00, 0xa2, 0xc4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dxex 8, 20"
-
input:
bytes: [ 0xed, 0x00, 0xa2, 0xc5 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dxex. 8, 20"
-
input:
bytes: [ 0xfd, 0x00, 0xa2, 0xc4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dxexq 8, 20"
-
input:
bytes: [ 0xfd, 0x00, 0xa2, 0xc5 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dxexq. 8, 20"
-
input:
bytes: [ 0xed, 0x0c, 0x96, 0xc4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "diex 8, 12, 18"
-
input:
bytes: [ 0xed, 0x0c, 0x96, 0xc5 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "diex. 8, 12, 18"
-
input:
bytes: [ 0xfd, 0x0c, 0x96, 0xc5 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "diexq. 8, 12, 18"
-
input:
bytes: [ 0xfd, 0x0c, 0x96, 0xc4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "diexq 8, 12, 18"
-
input:
bytes: [ 0xee, 0xc4, 0xfc, 0x84 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dscli 22, 4, 63"
-
input:
bytes: [ 0xee, 0xc4, 0xfc, 0x85 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dscli. 22, 4, 63"
-
input:
bytes: [ 0xfe, 0xc4, 0xfc, 0x84 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dscliq 22, 4, 63"
-
input:
bytes: [ 0xfe, 0xc4, 0xfc, 0x85 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dscliq. 22, 4, 63"
-
input:
bytes: [ 0xee, 0x0a, 0xc8, 0xc4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dscri 16, 10, 50"
-
input:
bytes: [ 0xee, 0x0a, 0xc8, 0xc5 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dscri. 16, 10, 50"
-
input:
bytes: [ 0xfe, 0x0a, 0xc8, 0xc4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dscriq 16, 10, 50"
-
input:
bytes: [ 0xfe, 0x0a, 0xc8, 0xc5 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dscriq. 16, 10, 50"
-
input:
bytes: [ 0xed, 0x06, 0x11, 0x84 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dtstdc 2, 6, 4"
-
input:
bytes: [ 0xfd, 0x06, 0x11, 0x84 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dtstdcq 2, 6, 4"
-
input:
bytes: [ 0xed, 0x06, 0x11, 0xc4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dtstdg 2, 6, 4"
-
input:
bytes: [ 0xfd, 0x06, 0x11, 0xc4 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dtstdgq 2, 6, 4"
-
input:
bytes: [ 0xed, 0x06, 0x21, 0x44 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dtstex 2, 6, 4"
-
input:
bytes: [ 0xfd, 0x06, 0x21, 0x44 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dtstexq 2, 6, 4"
-
input:
bytes: [ 0xed, 0x06, 0x25, 0x44 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dtstsf 2, 6, 4"
-
input:
bytes: [ 0xfd, 0x06, 0x25, 0x44 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dtstsfq 2, 6, 4"
-
input:
bytes: [ 0xed, 0x06, 0x25, 0x46 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dtstsfi 2, 6, 4"
-
input:
bytes: [ 0xfd, 0x06, 0x25, 0x46 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "dtstsfiq 2, 6, 4"

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test_cases:
-
input:
bytes: [ 0x38, 0x22, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "addi 1, 2, -1"
-
input:
bytes: [ 0x88, 0x22, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lbz 1, -1(2)"
-
input:
bytes: [ 0xc8, 0x22, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lfd 1, -1(2)"
-
input:
bytes: [ 0xa8, 0x22, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lha 1, -1(2)"
-
input:
bytes: [ 0xa0, 0x22, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lhz 1, -1(2)"
-
input:
bytes: [ 0x80, 0x22, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lwz 1, -1(2)"
-
input:
bytes: [ 0x98, 0x22, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stb 1, -1(2)"
-
input:
bytes: [ 0xd8, 0x22, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stfd 1, -1(2)"
-
input:
bytes: [ 0xd0, 0x22, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stfs 1, -1(2)"
-
input:
bytes: [ 0xb0, 0x22, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "sth 1, -1(2)"
-
input:
bytes: [ 0x90, 0x22, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stw 1, -1(2)"
-
input:
bytes: [ 0xe0, 0x23, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lq 1, 0(3)"
-
input:
bytes: [ 0xa4, 0x23, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lhzu 1, 0(3)"
-
input:
bytes: [ 0xa8, 0x23, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lha 1, 0(3)"
-
input:
bytes: [ 0xac, 0x23, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lhau 1, 0(3)"
-
input:
bytes: [ 0xcb, 0xe3, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lfd 31, -1(3)"
-
input:
bytes: [ 0xb8, 0x23, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lmw 1, 0(3)"
-
input:
bytes: [ 0xbc, 0x23, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stmw 1, 0(3)"
-
input:
bytes: [ 0xdb, 0xe3, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PWR10", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stfd 31, -1(3)"

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tests/MC/PowerPC/ppc64_encoding_only_offset_branch_syntax_noregname_big_endian_64_pwr7.txt.yaml Normal file
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test_cases:
-
input:
bytes: [ 0x7c, 0x20, 0x05, 0x1d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "tbegin. 1"
-
input:
bytes: [ 0x7c, 0x00, 0x05, 0x1d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "tbegin. 0"
-
input:
bytes: [ 0x7c, 0x00, 0x05, 0x5d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "tend."
-
input:
bytes: [ 0x7e, 0x00, 0x05, 0x5d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "tendall."
-
input:
bytes: [ 0x7c, 0x03, 0x07, 0x1d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "tabort. 3"
-
input:
bytes: [ 0x7d, 0x20, 0x06, 0x5d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "tabortdc. 9, 0, 0"
-
input:
bytes: [ 0x7c, 0x20, 0x1e, 0xdd ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "tabortdci. 1, 0, 3"
-
input:
bytes: [ 0x7c, 0x04, 0x1e, 0x1d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "tabortwc. 0, 4, 3"
-
input:
bytes: [ 0x7c, 0x04, 0x16, 0x9d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "tabortwci. 0, 4, 2"
-
input:
bytes: [ 0x7c, 0x20, 0x05, 0xdd ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "tresume."
-
input:
bytes: [ 0x7c, 0x00, 0x05, 0xdd ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "tsuspend."
-
input:
bytes: [ 0x7c, 0x00, 0x05, 0x9c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "tcheck 0"
-
input:
bytes: [ 0x7c, 0x03, 0x07, 0x5d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "treclaim. 3"
-
input:
bytes: [ 0x7c, 0x00, 0x07, 0xdd ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "trechkpt."

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test_cases:
-
input:
bytes: [ 0x10, 0x43, 0x25, 0xce ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "vpksdss 2, 3, 4"
-
input:
bytes: [ 0x10, 0x43, 0x25, 0x4e ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "vpksdus 2, 3, 4"
-
input:
bytes: [ 0x10, 0x43, 0x24, 0xce ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "vpkudus 2, 3, 4"
-
input:
bytes: [ 0x10, 0x43, 0x24, 0x4e ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "vpkudum 2, 3, 4"
-
input:
bytes: [ 0x10, 0x40, 0x1e, 0x4e ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "vupkhsw 2, 3"
-
input:
bytes: [ 0x10, 0x40, 0x1e, 0xce ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR8" ]
expected:
insns:
-
asm_text: "vupklsw 2, 3"

10
tests/MC/PowerPC/ppc64_encoding_p9vector_only_offset_branch_syntax_noregname_little_endian_64_pwr9.txt.yaml Normal file
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test_cases:
-
input:
bytes: [ 0x66, 0x1b, 0xc0, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PWR9" ]
expected:
insns:
-
asm_text: "mtvsrdd 6, 0, 3"

2950
tests/MC/PowerPC/ppc64_encoding_vmx_only_offset_branch_syntax_noregname_big_endian_64_pwr7.txt.yaml Normal file
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test_cases:
-
input:
bytes: [ 0x7c, 0x22, 0x1a, 0x14 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "add 1, 2, 3"
-
input:
bytes: [ 0x7c, 0x00, 0x02, 0x14 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "add 0, 0, 0"
-
input:
bytes: [ 0x7f, 0xff, 0xfa, 0x14 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "add 31, 31, 31"
-
input:
bytes: [ 0x38, 0x20, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "li 1, 0"
-
input:
bytes: [ 0x38, 0x22, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "addi 1, 2, 0"
-
input:
bytes: [ 0x38, 0x20, 0x80, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "li 1, -32768"
-
input:
bytes: [ 0x38, 0x20, 0x7f, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "li 1, 32767"
-
input:
bytes: [ 0x60, 0x41, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ori 1, 2, 0"
-
input:
bytes: [ 0x60, 0x41, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ori 1, 2, 65535"
-
input:
bytes: [ 0x3c, 0x20, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lis 1, 0"
-
input:
bytes: [ 0x3c, 0x20, 0xff, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lis 1, -1"
-
input:
bytes: [ 0x80, 0x20, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lwz 1, 0(0)"
-
input:
bytes: [ 0x80, 0x3f, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lwz 1, 0(31)"
-
input:
bytes: [ 0x80, 0x22, 0x80, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lwz 1, -32768(2)"
-
input:
bytes: [ 0x80, 0x22, 0x7f, 0xff ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "lwz 1, 32767(2)"
-
input:
bytes: [ 0xe8, 0x20, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ld 1, 0(0)"
-
input:
bytes: [ 0xe8, 0x3f, 0x00, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ld 1, 0(31)"
-
input:
bytes: [ 0xe8, 0x22, 0x80, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ld 1, -32768(2)"
-
input:
bytes: [ 0xe8, 0x22, 0x7f, 0xfc ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ld 1, 32764(2)"
-
input:
bytes: [ 0xe8, 0x22, 0x00, 0x04 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ld 1, 4(2)"
-
input:
bytes: [ 0xe8, 0x22, 0xff, 0xfc ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ld 1, -4(2)"
-
input:
bytes: [ 0x48, 0x00, 0x04, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "b .+1024"
-
input:
bytes: [ 0x48, 0x00, 0x04, 0x02 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "ba 0x400"
-
input:
bytes: [ 0x41, 0x82, 0x04, 0x00 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "bt 2, .+1024"
-
input:
bytes: [ 0x41, 0x82, 0x04, 0x02 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_PWR7" ]
expected:
insns:
-
asm_text: "bta 2, 0x400"

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tests/MC/PowerPC/ppc64le_encoding_isafuture_only_offset_branch_syntax_noregname_little_endian_64_ppc_isa_future.txt.yaml Normal file
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test_cases:
-
input:
bytes: [ 0x12, 0x17, 0x82, 0xf0 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxextfdmr512 1, 2, 34, 0"
-
input:
bytes: [ 0x12, 0x17, 0x83, 0xf0 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxextfdmr512 1, 2, 34, 1"
-
input:
bytes: [ 0x90, 0x47, 0x80, 0xf1 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxextfdmr256 3, 8, 0"
-
input:
bytes: [ 0x90, 0x4f, 0x81, 0xf1 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxextfdmr256 3, 8, 3"
-
input:
bytes: [ 0x52, 0x17, 0x82, 0xf0 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr512 1, 2, 34, 0"
-
input:
bytes: [ 0x52, 0x17, 0x83, 0xf0 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr512 1, 2, 34, 1"
-
input:
bytes: [ 0x94, 0x47, 0x80, 0xf1 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr256 3, 8, 0"
-
input:
bytes: [ 0x94, 0x4f, 0x81, 0xf1 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr256 3, 8, 3"
-
input:
bytes: [ 0x62, 0x01, 0x82, 0x7d ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmsetdmrz 3"
-
input:
bytes: [ 0x62, 0xa1, 0x06, 0x7e ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmmr 4, 5"
-
input:
bytes: [ 0x62, 0xe1, 0x07, 0x7f ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxor 6, 7"
-
input:
bytes: [ 0x90, 0x28, 0x64, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "subfus 3, 0, 4, 5"
-
input:
bytes: [ 0x90, 0x2c, 0x64, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "subfus 3, 1, 4, 5"
-
input:
bytes: [ 0x91, 0x28, 0x64, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "subfus. 3, 0, 4, 5"
-
input:
bytes: [ 0x91, 0x2c, 0x64, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "subfus. 3, 1, 4, 5"
-
input:
bytes: [ 0x1a, 0x14, 0x21, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "lxvrl 1, 1, 2"
-
input:
bytes: [ 0x5a, 0x24, 0x03, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "lxvrll 0, 3, 4"
-
input:
bytes: [ 0x1a, 0x0d, 0x40, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "stxvrl 2, 0, 1"
-
input:
bytes: [ 0x5a, 0x2d, 0x61, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "stxvrll 3, 1, 5"
-
input:
bytes: [ 0x9a, 0x2c, 0xc1, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "lxvprl 6, 1, 5"
-
input:
bytes: [ 0xda, 0x0c, 0xc2, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "lxvprll 6, 2, 1"
-
input:
bytes: [ 0x9a, 0x15, 0x01, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "stxvprl 0, 1, 2"
-
input:
bytes: [ 0xda, 0x0d, 0xc0, 0x7c ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_LITTLE_ENDIAN", "CS_MODE_64", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "stxvprll 6, 0, 1"

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tests/MC/PowerPC/ppc_encoding_isafuture_only_offset_branch_syntax_noregname_big_endian_64_aix_os_ppc_isa_future.txt.yaml Normal file
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test_cases:
-
input:
bytes: [ 0xf0, 0x82, 0x17, 0x12 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxextfdmr512 1, 2, 34, 0"
-
input:
bytes: [ 0xf0, 0x83, 0x17, 0x12 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxextfdmr512 1, 2, 34, 1"
-
input:
bytes: [ 0xf1, 0x80, 0x47, 0x90 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxextfdmr256 3, 8, 0"
-
input:
bytes: [ 0xf1, 0x81, 0x4f, 0x90 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxextfdmr256 3, 8, 3"
-
input:
bytes: [ 0xf0, 0x82, 0x17, 0x52 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr512 1, 2, 34, 0"
-
input:
bytes: [ 0xf0, 0x83, 0x17, 0x52 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr512 1, 2, 34, 1"
-
input:
bytes: [ 0xf1, 0x80, 0x47, 0x94 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr256 3, 8, 0"
-
input:
bytes: [ 0xf1, 0x81, 0x4f, 0x94 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr256 3, 8, 3"
-
input:
bytes: [ 0x7d, 0x82, 0x01, 0x62 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmsetdmrz 3"
-
input:
bytes: [ 0x7e, 0x06, 0xa1, 0x62 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmmr 4, 5"
-
input:
bytes: [ 0x7f, 0x07, 0xe1, 0x62 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "dmxor 6, 7"
-
input:
bytes: [ 0x7c, 0x64, 0x28, 0x90 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "subfus 3, 0, 4, 5"
-
input:
bytes: [ 0x7c, 0x64, 0x2c, 0x90 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "subfus 3, 1, 4, 5"
-
input:
bytes: [ 0x7c, 0x64, 0x28, 0x91 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "subfus. 3, 0, 4, 5"
-
input:
bytes: [ 0x7c, 0x64, 0x2c, 0x91 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "subfus. 3, 1, 4, 5"
-
input:
bytes: [ 0x7c, 0x21, 0x14, 0x1a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "lxvrl 1, 1, 2"
-
input:
bytes: [ 0x7c, 0x03, 0x24, 0x5a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "lxvrll 0, 3, 4"
-
input:
bytes: [ 0x7c, 0x40, 0x0d, 0x1a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "stxvrl 2, 0, 1"
-
input:
bytes: [ 0x7c, 0x61, 0x2d, 0x5a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "stxvrll 3, 1, 5"
-
input:
bytes: [ 0x7c, 0xc1, 0x2c, 0x9a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "lxvprl 6, 1, 5"
-
input:
bytes: [ 0x7c, 0xc2, 0x0c, 0xda ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "lxvprll 6, 2, 1"
-
input:
bytes: [ 0x7c, 0x01, 0x15, 0x9a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "stxvprl 0, 1, 2"
-
input:
bytes: [ 0x7c, 0xc0, 0x0d, 0xda ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_64", "CS_MODE_AIX_OS", "CS_MODE_PPC_ISA_FUTURE" ]
expected:
insns:
-
asm_text: "stxvprll 6, 0, 1"

230
tests/MC/PowerPC/ppc_encoding_isafuture_only_offset_branch_syntax_noregname_powerpc_unknown_aix_gnu_ppc_isa_future_big_endian.txt.yaml Normal file
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test_cases:
-
input:
bytes: [ 0xf0, 0x82, 0x17, 0x12 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxextfdmr512 1, 2, 34, 0"
-
input:
bytes: [ 0xf0, 0x83, 0x17, 0x12 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxextfdmr512 1, 2, 34, 1"
-
input:
bytes: [ 0xf1, 0x80, 0x47, 0x90 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxextfdmr256 3, 8, 0"
-
input:
bytes: [ 0xf1, 0x81, 0x4f, 0x90 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxextfdmr256 3, 8, 3"
-
input:
bytes: [ 0xf0, 0x82, 0x17, 0x52 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr512 1, 2, 34, 0"
-
input:
bytes: [ 0xf0, 0x83, 0x17, 0x52 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr512 1, 2, 34, 1"
-
input:
bytes: [ 0xf1, 0x80, 0x47, 0x94 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr256 3, 8, 0"
-
input:
bytes: [ 0xf1, 0x81, 0x4f, 0x94 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr256 3, 8, 3"
-
input:
bytes: [ 0x7d, 0x82, 0x01, 0x62 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmsetdmrz 3"
-
input:
bytes: [ 0x7e, 0x06, 0xa1, 0x62 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmmr 4, 5"
-
input:
bytes: [ 0x7f, 0x07, 0xe1, 0x62 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxor 6, 7"
-
input:
bytes: [ 0x7c, 0x64, 0x28, 0x90 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "subfus 3, 0, 4, 5"
-
input:
bytes: [ 0x7c, 0x64, 0x2c, 0x90 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "subfus 3, 1, 4, 5"
-
input:
bytes: [ 0x7c, 0x64, 0x28, 0x91 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "subfus. 3, 0, 4, 5"
-
input:
bytes: [ 0x7c, 0x64, 0x2c, 0x91 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "subfus. 3, 1, 4, 5"
-
input:
bytes: [ 0x7c, 0x21, 0x14, 0x1a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lxvrl 1, 1, 2"
-
input:
bytes: [ 0x7c, 0x03, 0x24, 0x5a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lxvrll 0, 3, 4"
-
input:
bytes: [ 0x7c, 0x40, 0x0d, 0x1a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stxvrl 2, 0, 1"
-
input:
bytes: [ 0x7c, 0x61, 0x2d, 0x5a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stxvrll 3, 1, 5"
-
input:
bytes: [ 0x7c, 0xc1, 0x2c, 0x9a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lxvprl 6, 1, 5"
-
input:
bytes: [ 0x7c, 0xc2, 0x0c, 0xda ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lxvprll 6, 2, 1"
-
input:
bytes: [ 0x7c, 0x01, 0x15, 0x9a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stxvprl 0, 1, 2"
-
input:
bytes: [ 0x7c, 0xc0, 0x0d, 0xda ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "powerpc-unknown-aix-gnu", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stxvprll 6, 0, 1"

230
tests/MC/PowerPC/ppc_encoding_isafuture_only_offset_branch_syntax_noregname_ppc_isa_future_big_endian.txt.yaml Normal file
View file

@ -0,0 +1,230 @@
test_cases:
-
input:
bytes: [ 0xf0, 0x82, 0x17, 0x12 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxextfdmr512 1, 2, 34, 0"
-
input:
bytes: [ 0xf0, 0x83, 0x17, 0x12 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxextfdmr512 1, 2, 34, 1"
-
input:
bytes: [ 0xf1, 0x80, 0x47, 0x90 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxextfdmr256 3, 8, 0"
-
input:
bytes: [ 0xf1, 0x81, 0x4f, 0x90 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxextfdmr256 3, 8, 3"
-
input:
bytes: [ 0xf0, 0x82, 0x17, 0x52 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr512 1, 2, 34, 0"
-
input:
bytes: [ 0xf0, 0x83, 0x17, 0x52 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr512 1, 2, 34, 1"
-
input:
bytes: [ 0xf1, 0x80, 0x47, 0x94 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr256 3, 8, 0"
-
input:
bytes: [ 0xf1, 0x81, 0x4f, 0x94 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxxinstfdmr256 3, 8, 3"
-
input:
bytes: [ 0x7d, 0x82, 0x01, 0x62 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmsetdmrz 3"
-
input:
bytes: [ 0x7e, 0x06, 0xa1, 0x62 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmmr 4, 5"
-
input:
bytes: [ 0x7f, 0x07, 0xe1, 0x62 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "dmxor 6, 7"
-
input:
bytes: [ 0x7c, 0x64, 0x28, 0x90 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "subfus 3, 0, 4, 5"
-
input:
bytes: [ 0x7c, 0x64, 0x2c, 0x90 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "subfus 3, 1, 4, 5"
-
input:
bytes: [ 0x7c, 0x64, 0x28, 0x91 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "subfus. 3, 0, 4, 5"
-
input:
bytes: [ 0x7c, 0x64, 0x2c, 0x91 ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "subfus. 3, 1, 4, 5"
-
input:
bytes: [ 0x7c, 0x21, 0x14, 0x1a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lxvrl 1, 1, 2"
-
input:
bytes: [ 0x7c, 0x03, 0x24, 0x5a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lxvrll 0, 3, 4"
-
input:
bytes: [ 0x7c, 0x40, 0x0d, 0x1a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stxvrl 2, 0, 1"
-
input:
bytes: [ 0x7c, 0x61, 0x2d, 0x5a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stxvrll 3, 1, 5"
-
input:
bytes: [ 0x7c, 0xc1, 0x2c, 0x9a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lxvprl 6, 1, 5"
-
input:
bytes: [ 0x7c, 0xc2, 0x0c, 0xda ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "lxvprll 6, 2, 1"
-
input:
bytes: [ 0x7c, 0x01, 0x15, 0x9a ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stxvprl 0, 1, 2"
-
input:
bytes: [ 0x7c, 0xc0, 0x0d, 0xda ]
arch: "CS_ARCH_PPC"
options: [ "CS_OPT_ONLY_OFFSET_BRANCH", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_PPC_ISA_FUTURE", "CS_MODE_BIG_ENDIAN" ]
expected:
insns:
-
asm_text: "stxvprll 6, 0, 1"

2880
tests/MC/PowerPC/vsx_only_offset_branch_syntax_noregname_pwr7_big_endian.txt.yaml Normal file
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File diff suppressed because it is too large Load diff

4
tests/details/ppc.yaml
View file

@ -31,7 +31,7 @@ test_cases:
bo_set: true
pred_ctr: PPC_PRED_NZ
-
asm_text: "bdztla 4*cr5+eq, 0xff14"
asm_text: "bdztla 4*cr5+eq, 0xffffff14"
details:
ppc:
operands:
@ -41,7 +41,7 @@ test_cases:
access: CS_AC_READ
-
type: PPC_OP_IMM
imm: 0xff14
imm: 0xffffff14
access: CS_AC_READ
bc:
bi: 22

2
utils.c
View file

@ -244,7 +244,7 @@ char *byte_seq_to_str(uint8_t *bytes, size_t len)
char *s = calloc(sizeof(char), 32);
for (size_t i = 0; i < len; ++i) {
cs_snprintf(single_byte, sizeof(single_byte), "0x%02" PRIx8 "%s",
bytes[i], i == len - 1 ? "" : ",");
bytes[i], i == len - 1 ? "" : ", ");
s = str_append(s, single_byte);
if (!s) {
return NULL;