mirror of
https://github.com/capstone-engine/capstone
synced 2026-08-11 16:26:07 -04:00
93a104c009
* Update PPC module to LLVM 18.
**New**
(According to LLVM changelog)
- Added DFP instruction.
- Added the SCV instruction.
**Changes**
- Memory decoder were simplified by decoding disponent and base reg separately.
- `DFORM` -> `DFORM_BASE`
- Use inverted `MCInstDesc` table.
- Replace the many declared printer in PPCInstPrinter with `static inlines`.
- Renamed groups to upper case.
- Switched to `ARCH_add_cs_detail_X()` function names.
- Remove `PPCInstPrinter.h` because it is no longer used.
* Fix: Use correct directory name.
* Fix segfaults and add asserts for these NULL cases.
* Allow to map a single LLVM option to multiple CS options
* Add default endian option to the MCUpdater
* Fix setter for Little endian
* Add SPE option to cstool
* Fix QPX instructions.
Due to 4b43ef3e5c
the names of the operands were matched.
Because FRT dosn't exist in the XForm_1 class,
the generated tables didn't decoded them.
* Fix: AbsAddr should be printed as unsigned.
* Fix S12 immediate printing for PC memory operands
* Fix MCUpdater tests
* Update PPCRegisterInfo_stripRegisterPrefix
* Add support for selection of Power versions
* Run clang-format
* Fix feature check
* Allow to overwrite in multi-mode
* Add some more flags
* Fix order and map name
* Add new test files.
* Fix checks for features.
Only enables PowerX feature checks of a Power architecture is enabled
and the feature is in the list of it.
* Print byte sequence with space between comma.
This helps with copy and search of the byte string in the test files.
* Fix tests broken due to feature toggles
* Shorten generated names.
* Update bindings
65 lines
2 KiB
C
65 lines
2 KiB
C
/* Capstone Disassembly Engine */
|
|
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
|
|
|
#ifndef CS_PPC_MAP_H
|
|
#define CS_PPC_MAP_H
|
|
|
|
#include "../../cs_priv.h"
|
|
#include "../../MCDisassembler.h"
|
|
#include "capstone/capstone.h"
|
|
|
|
typedef enum {
|
|
#include "PPCGenCSOpGroup.inc"
|
|
} ppc_op_group;
|
|
|
|
void PPC_init_mri(MCRegisterInfo *MRI);
|
|
|
|
void PPC_init_cs_detail(MCInst *MI);
|
|
|
|
// return name of register in friendly string
|
|
const char *PPC_reg_name(csh handle, unsigned int reg);
|
|
|
|
void PPC_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
|
|
bool PPC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
|
|
MCInst *instr, uint16_t *size, uint64_t address,
|
|
void *info);
|
|
|
|
// given internal insn id, return public instruction info
|
|
void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
|
|
|
|
const char *PPC_insn_name(csh handle, unsigned int id);
|
|
const char *PPC_group_name(csh handle, unsigned int id);
|
|
|
|
typedef struct {
|
|
unsigned int id; // instruction id
|
|
const char *mnem;
|
|
} ppc_alias_id;
|
|
|
|
void PPC_set_mem_access(MCInst *MI, bool status);
|
|
static inline void set_mem_access(MCInst *MI, bool status)
|
|
{
|
|
PPC_set_mem_access(MI, status);
|
|
}
|
|
|
|
// map internal raw register to 'public' register
|
|
ppc_reg PPC_map_register(unsigned int r);
|
|
|
|
bool PPC_getFeatureBits(unsigned int mode, unsigned int feature);
|
|
|
|
void PPC_add_cs_detail_0(MCInst *MI, ppc_op_group op_group, unsigned OpNo);
|
|
void PPC_add_cs_detail_1(MCInst *MI, ppc_op_group op_group, unsigned OpNo, const char *Modifier);
|
|
|
|
void PPC_set_detail_op_reg(MCInst *MI, unsigned OpNum, ppc_reg Reg);
|
|
void PPC_set_detail_op_imm(MCInst *MI, unsigned OpNum, int64_t Imm);
|
|
void PPC_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val,
|
|
bool is_off_reg);
|
|
|
|
void PPC_insert_detail_op_imm_at(MCInst *MI, unsigned index, int64_t Val,
|
|
cs_ac_type access);
|
|
|
|
void PPC_setup_op(cs_ppc_op *op);
|
|
|
|
void PPC_check_updates_cr0(MCInst *MI);
|
|
void PPC_set_instr_map_data(MCInst *MI, const uint8_t *Bytes, size_t BytesLen);
|
|
|
|
#endif
|