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RISCV: the Ventana vendor is missing in the API (#2917)

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* RISCV: the Ventana vendor was missing in the API

* Update docs
This commit is contained in:
Petar Andrić 2026-05-13 18:33:27 +02:00 • committed by GitHub
parent a2b119e20a
commit d650f67eb2
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GPG key ID: B5690EEEBB952194
9 changed files with 26 additions and 8 deletions
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3
arch/RISCV/RISCVDisassemblerExtension.c
View file

@ -69,6 +69,9 @@ bool RISCV_getFeatureBits(unsigned int mode, unsigned int feature)
case RISCV_FeatureVendorXTHeadVdot:
return mode & CS_MODE_RISCV_THEAD;
case RISCV_FeatureVendorXVentanaCondOps:
return mode & CS_MODE_RISCV_VENTANA;
case RISCV_FeatureStdExtZba:
return mode & CS_MODE_RISCV_ZBA;
case RISCV_FeatureStdExtZbb:

4
bindings/python/capstone/__init__.py
View file

@ -146,6 +146,8 @@ __all__ = [
"CS_MODE_RISCV_XSFVFWMACCQQQ",
"CS_MODE_RISCV_XSFVQMACCDOD",
"CS_MODE_RISCV_XSFVQMACCQOQ",
"CS_MODE_RISCV_VENTANA",
"CS_MODE_RISCV_XVENTANACONDOPS",
"CS_MODE_RISCV_BITMANIP",
"CS_MODE_RISCV_ZBA",
"CS_MODE_RISCV_ZBB",
@ -449,6 +451,8 @@ CS_MODE_RISCV_ZBKB = 1 << 17
CS_MODE_RISCV_ZBKC = 1 << 18
CS_MODE_RISCV_ZBKX = 1 << 19
CS_MODE_RISCV_ZBS = 1 << 20
CS_MODE_RISCV_VENTANA = 1 << 21
CS_MODE_RISCV_XVENTANACONDOPS = CS_MODE_RISCV_VENTANA
CS_MODE_MOS65XX_6502 = 1 << 1 # MOS65XXX MOS 6502
CS_MODE_MOS65XX_65C02 = 1 << 2 # MOS65XXX WDC 65c02
CS_MODE_MOS65XX_W65C02 = 1 << 3 # MOS65XXX WDC W65c02

7
cs.c
View file

@ -223,9 +223,10 @@ typedef struct cs_arch_config {
CS_MODE_RISCV_ZCMP_ZCMT_ZCE | CS_MODE_RISCV_ZICFISS | \
CS_MODE_RISCV_E | CS_MODE_RISCV_A | CS_MODE_RISCV_COREV | \
CS_MODE_RISCV_SIFIVE | CS_MODE_RISCV_THEAD | \
CS_MODE_RISCV_ZBA | CS_MODE_RISCV_ZBB | CS_MODE_RISCV_ZBC | \
CS_MODE_RISCV_ZBKB | CS_MODE_RISCV_ZBKC | \
CS_MODE_RISCV_ZBKX | CS_MODE_RISCV_ZBS), \
CS_MODE_RISCV_VENTANA | CS_MODE_RISCV_ZBA | \
CS_MODE_RISCV_ZBB | CS_MODE_RISCV_ZBC | CS_MODE_RISCV_ZBKB | \
CS_MODE_RISCV_ZBKC | CS_MODE_RISCV_ZBKX | \
CS_MODE_RISCV_ZBS), \
}
#define CS_ARCH_CONFIG_SH \
{ \

5
cstool/cstool.c
View file

@ -228,6 +228,11 @@ static struct {
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_SIFIVE },
{ "+ventana",
"Enables the RISCV ventana extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_VENTANA },
{ "+bitmanip",
"Enables the RISCV bit manipulation extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },

1
docs/cs_v6_release_guide.md
View file

@ -233,6 +233,7 @@ Nonetheless, we hope this additional information is useful to you.
* `CS_MODE_RISCV_ZBKC = 1 << 18`
* `CS_MODE_RISCV_ZBKX = 1 << 19`
* `CS_MODE_RISCV_ZBS = 1 << 20`
* `CS_MODE_RISCV_VENTANA = 1 << 21`
- Added two syntax options for alias control:
* `CS_OPT_SYNTAX_NO_ALIAS_TEXT`: RISC-V assigns readable aliases to special cases of more flexible instructions, for example: `ret` is a `jalr`, a more general instruction that takes an arbitrary register as jump destination and a link register. `ret` is the special case where those 2 arguments are restricted to `ra` and `x0` respectively.

1
include/capstone/capstone.h
View file

@ -231,6 +231,7 @@ typedef enum cs_mode {
CS_MODE_RISCV_ZBKC = 1 << 18,
CS_MODE_RISCV_ZBKX = 1 << 19,
CS_MODE_RISCV_ZBS = 1 << 20,
CS_MODE_RISCV_VENTANA = 1 << 21,
CS_MODE_MOS65XX_6502 = 1 << 1, ///< MOS65XXX MOS 6502
CS_MODE_MOS65XX_65C02 = 1 << 2, ///< MOS65XXX WDC 65c02
CS_MODE_MOS65XX_W65C02 = 1 << 3, ///< MOS65XXX WDC W65c02

3
suite/auto-sync/src/autosync/mcupdater.json
View file

@ -223,8 +223,9 @@
"xtheadcmo": ["CS_MODE_RISCV_XTHEADCMO"],
"xtheadcondmov": ["CS_MODE_RISCV_XTHEADCONDMOV"],
"xtheadsync": ["CS_MODE_RISCV_XTHEADSYNC"],
"xtheadvdot": ["CS_MODE_RISCV_XTHEADVDOT"]
"xtheadvdot": ["CS_MODE_RISCV_XTHEADVDOT"],
"xventanacondops": ["CS_MODE_RISCV_XVENTANACONDOPS"]
}
}
}

2
suite/cstest/include/test_mapping.h
View file

@ -182,6 +182,8 @@ static const cs_enum_id_map test_mode_map[] = {
{ .str = "CS_MODE_RISCV_XTHEADMEMPAIR", .val = CS_MODE_RISCV_THEAD },
{ .str = "CS_MODE_RISCV_XTHEADSYNC", .val = CS_MODE_RISCV_THEAD },
{ .str = "CS_MODE_RISCV_XTHEADVDOT", .val = CS_MODE_RISCV_THEAD },
{ .str = "CS_MODE_RISCV_XVENTANACONDOPS",
.val = CS_MODE_RISCV_VENTANA },
{ .str = "CS_MODE_RISCV_ZBA", .val = CS_MODE_RISCV_ZBA },
{ .str = "CS_MODE_RISCV_ZBB", .val = CS_MODE_RISCV_ZBB },
{ .str = "CS_MODE_RISCV_ZBC", .val = CS_MODE_RISCV_ZBC },

8
tests/MC/RISCV/XVentanaCondOps_valid_riscv64_xventanacondops_syntax_no_alias_text.txt.yaml
View file

@ -3,7 +3,7 @@ test_cases:
input:
bytes: [ 0x7b, 0x60, 0x00, 0x00 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "xventanacondops", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ]
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_XVENTANACONDOPS", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ]
expected:
insns:
-
@ -13,7 +13,7 @@ test_cases:
input:
bytes: [ 0x7b, 0x70, 0x00, 0x00 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "xventanacondops", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ]
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_XVENTANACONDOPS", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ]
expected:
insns:
-
@ -23,7 +23,7 @@ test_cases:
input:
bytes: [ 0xfb, 0x60, 0x31, 0x00 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "xventanacondops", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ]
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_XVENTANACONDOPS", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ]
expected:
insns:
-
@ -33,7 +33,7 @@ test_cases:
input:
bytes: [ 0xfb, 0x70, 0x31, 0x00 ]
arch: "CS_ARCH_RISCV"
options: [ "CS_MODE_RISCV64", "xventanacondops", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ]
options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_XVENTANACONDOPS", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ]
expected:
insns:
-