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1013 commits

Author SHA1 Message Date
Nguyen Anh Quynh
1be1374278 x86: cleanup isPrefixAtLocation() 2017-05-16 17:41:31 +07:00
Nguyen Anh Quynh
ca57b2a62d Merge branch 'next' into test2 2017-05-16 17:40:44 +07:00
Nguyen Anh Quynh
d4345d955b x86: attempt to fix uninitialized memory, probably by introduction of UD0 2017-05-09 20:22:48 +08:00
Nguyen Anh Quynh
7ee4581160 x86: LDS is invalid in x64. see #904 2017-05-08 10:49:16 +08:00
Nguyen Anh Quynh
e9bd063104 x86: another attempt to fix prefix ordering issue 2017-05-07 23:38:08 +08:00
Nguyen Anh Quynh
2b84c0cf2c x86: handle f2/f3 prefix for 16bit. see issue #452 2017-05-07 14:30:06 +08:00
Nguyen Anh Quynh
64328e3f56 x86: add UD0 instruction 2017-05-07 11:17:23 +08:00
Nguyen Anh Quynh
d5f075a17a x86: LES is invalid in x64. see #904 2017-05-06 14:29:40 +08:00
Nguyen Anh Quynh
c0b9f86e43 x86: AT&T syntax bug with zero offset segment register. see #884 2017-05-06 10:37:44 +08:00
Nguyen Anh Quynh
ed1dab2516 arm: another fix for #913 2017-05-05 09:53:29 +08:00
Nguyen Anh Quynh
6cd1ab12a8 arm: POP {reg} read/write SP register. this fixes #913 2017-05-04 17:20:01 +08:00
Nguyen Anh Quynh
ec76b6fc08 x86: lock nop is a valid instruction. #915 2017-05-03 20:06:15 +08:00
noword
6fbb0ed935 fix compiling error in MS VS2015 (#869) 
for issue #868
 2017-04-26 05:52:28 +08:00
Simorfo
6beb6ad931 Bugfix : setting all fields to insns cache (#899) 
* Bugfix : setting all fields to insns cache

* Bugfix
Fixing root cause, not setting opcode to 0 in default case

* Not resetting opcode to 0 in this case as well

* Finalizing bugfix
 2017-04-21 21:21:20 +08:00
radare
cd7b282181 Fix undefined behaviour produced by disassembling 6662dcbc615a (#898) 2017-04-20 23:04:52 +08:00
radare
2c1c1b1af4 Fix assigned value with undefined (#893) 2017-04-18 06:45:03 +08:00
Nguyen Anh Quynh
ae34c9b58b Merge branch 'next2' into next 2017-04-17 21:27:26 +08:00
Nguyen Anh Quynh
47d0478dd9 Merge branch 'next' of https://github.com/fotisl/capstone into fotisl-next 2017-04-17 21:19:10 +08:00
Fotis Loukos
a6111dfd95 Fixed group name getting function 2017-04-17 11:57:16 +03:00
el2ro
d09f56545c fix merged conflicts 2017-04-15 10:39:06 +08:00
szt
5cdc9c3c14 replace if-s in AArch64_AM_decodeAdvSIMDModImmType10 with lookup table (#552) 
* replace if-s in AArch64_AM_decodeAdvSIMDModImmType10 with lookup table

Lookup table is much faster than bunch of if-s. If you don't like lookup tables, I have another proposal. See http://goo.gl/RjW1lr and compare generated machine code

* Smaller lookup table and shifting and bit mask used

* Update AArch64AddressingModes.h
 2017-04-15 10:36:43 +08:00
Nguyen Anh Quynh
4cebdb2c00 Merge branch 'next' of https://github.com/fotisl/capstone into fotisl-next 2017-04-15 09:53:05 +08:00
Fotis Loukos
03de8c6a5c Corrected a bug 
Corrected a bug that would cause capstone to crash under certain invalid
instructions.
 2017-04-14 22:39:40 +03:00
radare
f20a0a032b Fix UB when accessing un-initialized array (#890) 2017-04-14 23:21:56 +08:00
Fotis Loukos
bbc5fe3fe6 Fixed myinttypes.h 2017-04-14 17:40:53 +03:00
Fotis Loukos
0850d55211 Added support for the TMS320C64x architecture. 2017-04-14 17:00:40 +03:00
Nguyen Anh Quynh
a28ae7d488 x86: support BND prefix. issue #872 2017-03-17 23:44:34 +08:00
Nguyen Anh Quynh
5b84c69178 x86: consistent register names ST0-ST7 with the asm output 2017-02-22 15:54:37 +08:00
Nguyen Anh Quynh
a1422bd8f6 arm: add IMM operand for printPostIdxImm8s4Operand(). issue #861 2017-02-22 09:27:16 +08:00
Nguyen Anh Quynh
2fa3f02f2a ppc: print 0 offset for memory operand. see issue #856 2017-02-19 21:28:05 +08:00
Nguyen Anh Quynh
bd2077c2d6 switch endian mode with cs_option() for Arm/Arm64/Mips/Sparc. fix issue #849 2017-02-01 11:19:00 +08:00
Vincent Bénony
9271db7c7f Fixes truncated immediate value in operand details 
The instruction encoded « 00 00 19 B2 » was correctly disassembled « orr x0, x0, #0x8000000080 », but the reported immediate value, in the detail structure, was truncated to 0x80 due to the cast.
 2017-01-26 17:10:16 +01:00
Daniel Collin
18e8cee2db Fixed incorrect 8-bit displacement 
8-bit displacement was treated as unsigned while it should actually be signed.
 2017-01-23 20:11:53 +01:00
Nguyen Anh Quynh
fca6fe4837 arm: groups for Thumb SETEND instruction. ported from #843 2017-01-19 09:13:49 +08:00
Nguyen Anh Quynh
dd56985837 x86: Fix the operand encoding in the test instruction for reduce set, issue #702 2017-01-03 01:33:21 +08:00
Nguyen Anh Quynh
c00d644be0 Merge branch 'next' of https://github.com/aquynh/capstone into next 2017-01-03 01:06:06 +08:00
Nguyen Anh Quynh
7339846891 x86: Fix the operand encoding in the test instruction, issue #702 2017-01-03 01:05:52 +08:00
BartmanAbyss
35c96234cf (M68k) make displacements signed (#836) 
* (M68k) make displacements signed

* (M68k) revert group changes

* (m68k) signed displacement in python bindings
 2017-01-01 01:11:48 +08:00
Nguyen Anh Quynh
0237e4ca0c arm: fix operand access info for Bcc & BL. see issue #826 2016-12-13 18:20:01 +07:00
Nguyen Anh Quynh
1814c7ece4 arm: fix access info for RET. see issue #825 2016-12-13 18:02:51 +07:00
Nguyen Anh Quynh
df24131881 arm: fix decoding Thumb big-endian instructions. ported from PR #813 2016-11-14 21:37:23 +09:00
Nguyen Anh Quynh
61a503165c x86: fix instruction MOVAPS & MOVAPD. see issue #809 2016-11-11 11:27:34 +09:00
Nguyen Anh Quynh
b8bc95afdd x86: fix (AT&T) instruction SLDT for issue #807 2016-11-08 11:46:21 +08:00
Nguyen Anh Quynh
dcfd572710 x86: fix (AT&T) instruction lgs for issue #805 2016-11-08 11:39:10 +08:00
Nguyen Anh Quynh
1af41d2f92 x86: fix (AT&T) ROL instruction in issue #804 2016-11-08 11:28:09 +08:00
Nguyen Anh Quynh
3ca6b0df43 x86: fix movw instruction in #789 2016-11-08 10:56:18 +08:00
Nguyen Anh Quynh
ae360eaac3 x86: fix sysexit in #806 2016-11-08 10:29:07 +08:00
Samuel Chevet
c36a479b45 Add X86_REG_EFLAGS to X86_CLC, X86_CLD, X86_CMC (#801) 
* add X86_REG_EFLAGS for X86_STC

* remove wrong X86_GRP_PRIVILEGE for X86_STC ; add X86_REG_EFLAGS for X86_STD

* Add X86_REG_EFLAGS to X86_CLC, X86_CLD, X86_CMC

* add X86_REG_EFLAGS to X86_CLC, X86_CLD, X86_CMC for reduced instructions too
 2016-10-28 21:49:41 +08:00
Samuel Chevet
31378e5007 add X86_REG_EFLAGS for X86_STC (#797) 
* add X86_REG_EFLAGS for X86_STC

* remove wrong X86_GRP_PRIVILEGE for X86_STC ; add X86_REG_EFLAGS for X86_STD
 2016-10-28 03:23:50 +08:00
Andrew Dutcher
883c333f86 Fix two missing register operands in X86 AT&T syntax (#791) 
* Bug fix: missing register operand in AT&T emitter for `movb %ax, imm`

* Bug fix: missing register operand in AT&T emitter for `movb %al, imm`
 2016-10-14 13:26:27 +08:00