* Add Python bindings for WASM
* Update Python bindings for m68k
* Update Python bindings for mos65xx
* Update Python bindings for x86
* Add Python bindings for SH
* Update CS_* constants in Python bindings
* Update constants from ARM auto-sync patch
* Fixing TriCore disasm instructions (#2088)
* allow absolute CMAKE_INSTALL_*DIR (#2134)
This patch fixes Capstone 5 build on NixOS.
NixOS's build infrastructure sets CMAKE_INSTALL_{LIB,INCLUDE}DIR to
absolute paths. If you append it to ${prefix}, you get the wrong path.
NixOS automatically detects it and links this issue:
https://github.com/NixOS/nixpkgs/issues/144170
---------
Co-authored-by: Peace-Maker <peace-maker@wcfan.de>
Co-authored-by: Bastian Koppelmann <bkoppelmann@users.noreply.github.com>
Co-authored-by: chayleaf <chayleaf@protonmail.com>
* mos65xx: use imm field for immediate operand value
using the wrong field works on little-endian hosts, but on big-endian the wrong value would be read
* mos65xx: set operand mem field to address also in relative modes
previously the last operand would have an offset, which doesn't match the printed operand
* mos65xx: add bpl instruction to test
this demonstrates an address operand with relative addressing
* Fix Excessive and Missing Dependencies found by Vemake
* Remove extra spaces at the end of Makefile
* Remove used macro df
* Change "-rf" to "-f" in tests/Makefile
* Change "-rf" to "-f" in suite/fuzz/Makefile
* Remove 'r' from the removal command.
* Remove an extra blank line.
* updated 6502 support. some improvements to the base 6502 support but also adds support for 65c02, w65c02, and 65816.
* add CS_OPT_SYNTAX_MOTOROLA.
This will use "$" as a hex prefix instead of "0x"
* remove excess blank lines
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: 0db412ce3b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
* m68k: store correct m68k_reg value in op.reg_pair
Originally, value - M68K_REG_D0 was stored and the print logic added
M68K_REG_D0.
* m68k: fix license typo
* Basic changes of new arch - BPF
* Define some constants
* defined some API methods
* Able to print MISC instruction
* Follow Linux coding style
* Ability to show ALU insn names
* decode return
* Add suite/MC/BPF
* decode jump
* decode store
* decode load
* print instruction done
* try to implement BPF_reg_access
* Implements explicit accessed registers and fix some tiny bugs
* Fix unhandled ja case
* Added BPF_REG_OFF do fix wrong display in jump class
* Great I'm able to decode cBPF with eyes
* Fix: misunderstood the 16-byte instruction's imm
* Add ldxdw
* Add extended-all.cs
* Implements cstest/bpf_getdetail.c
* Fix memory leak
* Add BPF to fuzz
* Implemented regs_read and regs_write
* Fix missing write-access on ALU's dst
* Updated cstool/, test_basic.c, test_detail.c, and test_iter.c
* Updated docs
* Fix type of cs_bpf#operands
* Implements python bindings
* Fix some bugs found by self code review
* Remove dummy tests
* remove typeof
* Address comments
* Fix MSVC's warnings and add test_bpf.py to bindings/python/Makefile
* Fix: call is not offset
* Print EFLAGS and FPU_FLAGS correctly in test_x86
Since the eflags and fpu_flags are union the instruction group needs
to be checked for FPU to see if the flag is an FPU flag. cstool_x86
was already doing this but test_x86 was not. The result was the fadd
instruction from the x86 16bit test was showing in the test_x86
output as having eflags. Since fadd is an fpu instruction the FPU_FLAGS
should be shown instead.
* Remove extra newline in instruction output
All of the other test_<arch>.c functions print a single newline after
the dissassembly. x86 had two newlines. This makes test_x86
consistent with all the other test output.
The actual conditional PPC flag used is CAPSTONE_HAS_POWERPC. It
appears as if some of the test suite files was using the incorrect flag. Because
of this test_basic, test_detail and test_iter were all failing to output PPC
code in the default configuration.
