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مصطفي محمود كمال الدين 032f79993d
RISC-V: Add v5 compatibility behaviour for CS_MODE_RISCVC/RISCV_C (#2996) 
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
2026-07-18 16:58:01 +00:00
..
test_all.py RISC-V: add reg_access and test its usages in C and Python (#2895) 2026-04-17 17:40:16 +00:00
test_compatibility_layer.py RISC-V: Add v5 compatibility behaviour for CS_MODE_RISCVC/RISCV_C (#2996) 2026-07-18 16:58:01 +00:00
test_customized_mnem.py Python binding: (#2874) 2026-03-02 19:11:38 +00:00
test_iter.py Python binding: (#2874) 2026-03-02 19:11:38 +00:00
test_lite.py Python binding: (#2874) 2026-03-02 19:11:38 +00:00
test_riscv_reg_access.py RISC-V: add reg_access and test its usages in C and Python (#2895) 2026-04-17 17:40:16 +00:00
test_riscv_sysreg.py Fix sysreg registers in RISC-V and modify the header patcher to not crash if a header doesn't include all tags of a generated .inc file (#2894) 2026-04-15 09:25:46 +00:00
test_skipdata.py Python binding: (#2874) 2026-03-02 19:11:38 +00:00