* RISC-V: add reg_access and test its usages in C and Python
reg_access is a convenience wrapper over the `operands` array that filters the register operands (including those used as memory base address) and returns them sorted into read
and written registers. It wasn't implemented for RISC-V, this PR implements it.
The following decisions were made for RISC-V:
1- System registers (CSRs) are not registers
This follows existing Capstone convention, where almost every archiceture that have system registers except x86 treats them as a seperate address space.
From a purely practical POV, the reg_access function API returns registers as an array of integers, and the address space of normal registers intersects with that of system registers
so there is nothing in the return value to distinguish them.
2- PC is not an implicit register
Whenever an instruction reads PC (e.g. all call-ish instructions JAL[R]?) this is NOT counted as an implicit read of the PC.
The reason is that the PC is somewhat "second class" in RISC-V, it's an archiectural register but has no actual index and can never be directly written to by any instruction in any
standard extension no matter the privliege.
Meanwhile, all instruction that read the PC have names that make it obvious they read the PC so adding that information to the implicit reads array would be redundant.
* Add arm64.py and sysz_const.py compatibility layer to the Python bindings
When importing `capstone.arm64` before doing other capstone imports the ARM64 constants get monkey patched into the exports.
Same with `capstone.sysz_const` for the SYSZ constants.
* Add SPDX-License comments
* Access an instruction detail in compatibility test
* Fail python tests on error instead of just ERROR output
Include the test_iter.py in the test_all.py too.
* Improve python compatibility docs
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
* Test for ARM_CC_* constants presence
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Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
