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MRS Xt, NZCV reads (and MSR NZCV, Xt writes) the same flags every flag-setting instruction implicitly defines, but the generated implicit register lists cannot express it: MRS/MSR are single generic instructions whose system register is an immediate operand, so LLVM's static Uses/Defs do not depend on it. The semantic link is already half-modeled: AArch64_check_updates_flags() sets update_flags for MSR NZCV, yet neither direction surfaces in the detail register lists or cs_regs_access(). Add the aliased NZCV register to the implicit lists when MRS reads or MSR writes it. The 128-bit pair forms MRRS/MSRR are deliberately excluded: NZCV is not a valid 128-bit system register, so those encodings are UNDEFINED rather than flag accesses (an exhaustive 2^32-word cross-check against an external NZCV-liveness model caught exactly this over-match in an earlier revision of the patch). Add detail tests covering both directions, a TPIDR_EL0 control case, and exact-match register lists for MRRS/MSRR. |
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| .. | ||
| aarch64.yaml | ||
| alpha.yaml | ||
| arc.yaml | ||
| arm.yaml | ||
| bpf.yaml | ||
| cs_common_details.yaml | ||
| evm.yaml | ||
| hppa.yaml | ||
| loongarch.yaml | ||
| m68k.yaml | ||
| m680x.yaml | ||
| mips.yaml | ||
| mos65xx.yaml | ||
| ppc.yaml | ||
| README.md | ||
| riscv.yaml | ||
| sh.yaml | ||
| sparc.yaml | ||
| systemz.yaml | ||
| tms320c64x.yaml | ||
| tricore.yaml | ||
| wasm.yaml | ||
| x86.yaml | ||
| xcore.yaml | ||
| xtensa.yaml | ||
Test instruction details
This directory contains test cases for the cs_detail struct.
Test files are consumed by the cstest tool (see: suite/cstest).