mirror of
https://github.com/rizinorg/rizin
synced 2026-08-22 20:26:16 -04:00
Bump Capstone v6 to Alpha10 (#6644)
* Bump Capstone v6 to Alpha10 * Bump capstone-next to latest commit. * Remove Alpha check for upper case enums. * Add Xtensa ESP32s3 CPU. Moves the asm tests to a properly configured test file. * Document db/asm file naming * Fix leaks
This commit is contained in:
Rot127
GitHub
parent
136a337e1c
commit
e8818d1888
15 changed files with 119 additions and 79 deletions
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@ -8,6 +8,14 @@
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#include "asm_private.h"
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#include "analysis_private.h"
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#if CS_API_MAJOR >= 6 && CS_VERSION_PRE_RELEASE < CS_VERSION_ALPHA11
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// After Alpha10 the CS_MODE_XTENSA_ESP32S3 mode was added and some
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// instructions no longer decode without it.
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// For <= Alpha10 the instructions also decode with CS_MODE_XTENSA_ESP32S2.
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// Hence this redefinition.
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#define CS_MODE_XTENSA_ESP32S3 CS_MODE_XTENSA_ESP32S2
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#endif
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typedef struct {
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const char *cpu;
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cs_mode mode;
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@ -16,6 +24,7 @@ typedef struct {
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static const XtensaCPUMode xtensa_cpu_modes[] = {
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{ .cpu = "esp32", .mode = CS_MODE_XTENSA_ESP32 },
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{ .cpu = "esp32s2", .mode = CS_MODE_XTENSA_ESP32S2 },
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{ .cpu = "esp32s3", .mode = CS_MODE_XTENSA_ESP32S3 },
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{ .cpu = "esp8266", .mode = CS_MODE_XTENSA_ESP8266 },
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};
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@ -13,6 +13,31 @@
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#define RZ_ALPHA_INS(name) ALPHA_INS_##name
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// Stupid me forgot to request that all enums must be upper case
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// in the initial Capstone Alpha PR - Yes, I know.
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// This can be removed once Capstone v5 support is dropped.
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#if (CS_API_MAJOR >= 6) && (CS_VERSION_PRE_RELEASE >= CS_VERSION_ALPHA10)
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#define ALPHA_INS_CMPTEQsSU ALPHA_INS_CMPTEQSSU
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#define ALPHA_INS_CMPTLEsSU ALPHA_INS_CMPTLESSU
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#define ALPHA_INS_CMPTLTsSU ALPHA_INS_CMPTLTSSU
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#define ALPHA_INS_CMPTUNsSU ALPHA_INS_CMPTUNSSU
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#define ALPHA_INS_CVTQSsSUI ALPHA_INS_CVTQSSSUI
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#define ALPHA_INS_CVTQTsSUI ALPHA_INS_CVTQTSSUI
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#define ALPHA_INS_CVTSTsS ALPHA_INS_CVTSTSS
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#define ALPHA_INS_CVTTQsSVC ALPHA_INS_CVTTQSSVC
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#define ALPHA_INS_CVTTSsSUI ALPHA_INS_CVTTSSSUI
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#define ALPHA_INS_DIVSsSU ALPHA_INS_DIVSSSU
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#define ALPHA_INS_DIVTsSU ALPHA_INS_DIVTSSU
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#define ALPHA_INS_MULSsSU ALPHA_INS_MULSSSU
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#define ALPHA_INS_MULTsSU ALPHA_INS_MULTSSU
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#define ALPHA_INS_SQRTSsSU ALPHA_INS_SQRTSSSU
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#define ALPHA_INS_SQRTTsSU ALPHA_INS_SQRTTSSU
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#define ALPHA_INS_SUBSsSU ALPHA_INS_SUBSSSU
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#define ALPHA_INS_SUBTsSU ALPHA_INS_SUBTSSU
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#define ALPHA_INS_ADDSsSU ALPHA_INS_ADDSSSU
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#define ALPHA_INS_ADDTsSU ALPHA_INS_ADDTSSU
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#endif
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static char *get_reg_profile(RzAnalysis *_) {
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const char *p =
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"=PC r31\n"
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@ -276,8 +301,6 @@ static void alpha_op_set_type(RzAsmAlphaContext *ctx, RzAnalysisOp *op) {
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case RZ_ALPHA_INS(ADDL):
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case RZ_ALPHA_INS(ADDQ):
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case RZ_ALPHA_INS(ADDSsSU):
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case RZ_ALPHA_INS(ADDTsSU):
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case RZ_ALPHA_INS(AND):
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case RZ_ALPHA_INS(BIC):
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case RZ_ALPHA_INS(BIS):
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@ -293,10 +316,6 @@ static void alpha_op_set_type(RzAsmAlphaContext *ctx, RzAnalysisOp *op) {
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case RZ_ALPHA_INS(CMPEQ):
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case RZ_ALPHA_INS(CMPLE):
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case RZ_ALPHA_INS(CMPLT):
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case RZ_ALPHA_INS(CMPTEQsSU):
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case RZ_ALPHA_INS(CMPTLEsSU):
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case RZ_ALPHA_INS(CMPTLTsSU):
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case RZ_ALPHA_INS(CMPTUNsSU):
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case RZ_ALPHA_INS(CMPULE):
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case RZ_ALPHA_INS(CMPULT):
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case RZ_ALPHA_INS(COND_BRANCH):
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@ -306,13 +325,6 @@ static void alpha_op_set_type(RzAsmAlphaContext *ctx, RzAnalysisOp *op) {
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case RZ_ALPHA_INS(CTLZ):
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case RZ_ALPHA_INS(CTPOP):
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case RZ_ALPHA_INS(CTTZ):
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case RZ_ALPHA_INS(CVTQSsSUI):
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case RZ_ALPHA_INS(CVTQTsSUI):
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case RZ_ALPHA_INS(CVTSTsS):
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case RZ_ALPHA_INS(CVTTQsSVC):
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case RZ_ALPHA_INS(CVTTSsSUI):
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case RZ_ALPHA_INS(DIVSsSU):
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case RZ_ALPHA_INS(DIVTsSU):
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case RZ_ALPHA_INS(ECB):
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case RZ_ALPHA_INS(EQV):
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case RZ_ALPHA_INS(EXCB):
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@ -358,8 +370,6 @@ static void alpha_op_set_type(RzAsmAlphaContext *ctx, RzAnalysisOp *op) {
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case RZ_ALPHA_INS(MSKWL):
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case RZ_ALPHA_INS(MULL):
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case RZ_ALPHA_INS(MULQ):
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case RZ_ALPHA_INS(MULSsSU):
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case RZ_ALPHA_INS(MULTsSU):
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case RZ_ALPHA_INS(ORNOT):
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case RZ_ALPHA_INS(RC):
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case RZ_ALPHA_INS(RPCC):
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@ -375,22 +385,37 @@ static void alpha_op_set_type(RzAsmAlphaContext *ctx, RzAnalysisOp *op) {
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case RZ_ALPHA_INS(SEXTB):
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case RZ_ALPHA_INS(SEXTW):
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case RZ_ALPHA_INS(SLL):
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case RZ_ALPHA_INS(SQRTSsSU):
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case RZ_ALPHA_INS(SQRTTsSU):
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case RZ_ALPHA_INS(SRA):
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case RZ_ALPHA_INS(SRL):
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case RZ_ALPHA_INS(STS):
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case RZ_ALPHA_INS(STT):
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case RZ_ALPHA_INS(SUBL):
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case RZ_ALPHA_INS(SUBQ):
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case RZ_ALPHA_INS(SUBSsSU):
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case RZ_ALPHA_INS(SUBTsSU):
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case RZ_ALPHA_INS(TRAPB):
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case RZ_ALPHA_INS(UMULH):
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case RZ_ALPHA_INS(WH64):
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case RZ_ALPHA_INS(WH64EN):
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case RZ_ALPHA_INS(WMB):
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case RZ_ALPHA_INS(ZAPNOT):
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case RZ_ALPHA_INS(CMPTEQsSU):
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case RZ_ALPHA_INS(CMPTLEsSU):
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case RZ_ALPHA_INS(CMPTLTsSU):
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case RZ_ALPHA_INS(CMPTUNsSU):
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case RZ_ALPHA_INS(CVTQSsSUI):
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case RZ_ALPHA_INS(CVTQTsSUI):
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case RZ_ALPHA_INS(CVTSTsS):
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case RZ_ALPHA_INS(CVTTQsSVC):
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case RZ_ALPHA_INS(CVTTSsSUI):
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case RZ_ALPHA_INS(DIVSsSU):
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case RZ_ALPHA_INS(DIVTsSU):
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case RZ_ALPHA_INS(MULSsSU):
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case RZ_ALPHA_INS(MULTsSU):
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case RZ_ALPHA_INS(SQRTSsSU):
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case RZ_ALPHA_INS(SQRTTsSU):
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case RZ_ALPHA_INS(SUBSsSU):
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case RZ_ALPHA_INS(SUBTsSU):
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case RZ_ALPHA_INS(ADDSsSU):
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case RZ_ALPHA_INS(ADDTsSU):
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break;
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}
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}
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@ -34,6 +34,7 @@ static char **xtensa_cpu_descriptions() {
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static char *cpu_desc[] = {
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"esp32", "Xtensa microcontroller with Wi-Fi and Bluetooth capabilities",
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"esp32s2", "Xtensa microcontroller with Wi-Fi and USB OTG support",
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"esp32s3", "Xtensa microcontroller with Wi-Fi, USB OTG support, and HIFI3",
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"esp8266", "Xtensa microcontroller with Wi-Fi support",
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NULL
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};
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@ -46,7 +47,7 @@ RzAsmPlugin rz_asm_plugin_xtensa_cs = {
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.desc = "Tensilica Xtensa Capstone-based disassembler",
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.author = "billow",
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.arch = "xtensa",
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.cpus = "esp32,esp32s2,esp8266",
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.cpus = "esp32,esp32s2,esp32s3,esp8266",
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.bits = 32,
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.endian = RZ_SYS_ENDIAN_LITTLE | RZ_SYS_ENDIAN_BIG,
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.disassemble = asm_xtensa_disassemble,
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@ -114,9 +114,11 @@ static void update_asmbits_options(RzCore *core, RzConfigNode *node) {
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int bits = rz_asm_get_plugin_bits(core->rasm);
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rz_set_s_clear(node->options);
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char b[32] = { 0 };
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for (int i = 1; i <= bits; i <<= 1) {
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if (i & bits) {
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SETOPTIONS(node, rz_str_newf("%d", i), NULL);
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rz_strf(b, "%d", i);
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SETOPTIONS(node, b, NULL);
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}
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}
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}
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@ -736,11 +736,12 @@ RZ_API int rz_main_rz_asm(int argc, const char *argv[]) {
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rz_analysis_set_big_endian(as->analysis, canbebig);
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}
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if (whatsop) {
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const char *s = rz_asm_describe(as->a, opt.argv[opt.ind]);
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char *s = rz_asm_describe(as->a, opt.argv[opt.ind]);
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ret = 1;
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if (s) {
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printf("%s\n", s);
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ret = 0;
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free(s);
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}
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goto beach;
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}
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16
meson.build
16
meson.build
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@ -215,22 +215,6 @@ else
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add_project_arguments(['-DUSE_SYS_CAPSTONE'], language: 'c')
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endif
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has_capstone_alpha_uppercase_insns = cc.compiles('''
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#include <capstone/capstone.h>
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#include <capstone/alpha.h>
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int main(void) {
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alpha_insn insn = ALPHA_INS_INVALID;
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return insn == ALPHA_INS_INVALID;
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}
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''',
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dependencies: capstone_check_deps,
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include_directories: capstone_check_includes,
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name: 'Capstone has uppercase Alpha instruction IDs'
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)
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if has_capstone_alpha_uppercase_insns
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add_project_arguments(['-DRZ_CAPSTONE_ALPHA_INSNS_UPPERCASE'], language: 'c')
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endif
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has_capstone_m68k_cpu32 = cc.compiles('''
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#include <capstone/capstone.h>
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int main(void) {
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@ -1,6 +1,6 @@
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[wrap-git]
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url = https://github.com/capstone-engine/capstone.git
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revision = ae11e4232cb1f0df4847bf2d66825b9f1cb119a2
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revision = 6fb5a1717604d171637012dc87baef93773f8f5a
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directory = capstone-next
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patch_directory = capstone-next
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depth = 1
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@ -1,6 +1,6 @@
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[wrap-file]
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source_url = https://github.com/capstone-engine/capstone/releases/download/6.0.0-Alpha9/capstone-6.0.0-Alpha9.tar.xz
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source_filename = capstone-6.0.0-Alpha9.tar.xz
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source_hash = 4c8e4f98827236d43be41b91f3faa7cc70f2f0699b97356a60b6a9d492540ed7
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directory = capstone-6.0.0-Alpha9
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patch_directory = capstone-6.0.0-alpha9
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source_url = https://github.com/capstone-engine/capstone/releases/download/6.0.0-Alpha10/capstone-6.0.0-Alpha10.tar.xz
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source_filename = capstone-6.0.0-Alpha10.tar.xz
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source_hash = 3eabbad2c6e6b6904c78c72110527e5c560a245421fcc2dfbb135aa292a95e94
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directory = capstone-6.0.0-Alpha10
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patch_directory = capstone-6.0.0-alpha10
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@ -80,6 +80,7 @@ static TAG_CALLBACK(spp_get) {
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var = spp_var_get (buf);
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if (var) {
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out_printf (out, "%s", var);
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free(var);
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}
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return 0;
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}
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@ -230,6 +231,7 @@ static TAG_CALLBACK(spp_ifeq) {
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else state->echo[state->ifl + 1] = 0;
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//fprintf(stderr, "IFEQ(%s)(%s)=%d\n", buf, value, echo[ifl]);
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}
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free(value);
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return 1;
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}
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@ -98,6 +98,20 @@ a "nop" 90 # Assembly is correct
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dB "nopppp" 90 # Disassembly test is broken
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```
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#### Select bits and cpu
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Some instructions are only valid for a certain ISA version.
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For that `rz-test` is setup with the correct architecture, bits, and cpu model from the file name.
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The possible formats are:
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1. `<arch>`
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Example: `arm`
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2. <arch>_<bits>
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Example: `arm_32`
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3. <arch>_<cpu>_<bits>
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Example: `arm_cortex_32`
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#### Multiple instructions in a single test
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Some instructions change if they appear together with another instructions.
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@ -227,26 +227,6 @@ d "rsil a1, 0xf" 106f00 0x0 (seq (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+
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d "rsqrt0.s f1, f2" a012fa 0x0 nop
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d "rsr a1, litbase" 100503 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var litbase))
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d "rsync" 102000 0x0 nop
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d "rur.accx_0 a0" 0000e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_0))
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d "rur.accx_0 a1" 0010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_0))
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d "rur.accx_1 a1" 1010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_1))
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d "rur.qacc_h_0 a1" 2010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_0))
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d "rur.qacc_h_1 a1" 3010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_1))
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d "rur.qacc_h_2 a1" 4010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_2))
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d "rur.qacc_h_3 a1" 5010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_3))
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d "rur.qacc_h_4 a1" 6010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_4))
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d "rur.qacc_l_0 a1" 7010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_0))
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d "rur.qacc_l_1 a1" 8010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_1))
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d "rur.qacc_l_2 a1" 9010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_2))
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d "rur.qacc_l_3 a1" a010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_3))
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d "rur.qacc_l_4 a1" b010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_4))
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d "rur.gpio_out a1" c010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var gpio_out))
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d "rur.sar_byte a1" d010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var sar_byte))
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d "rur.fft_bit_width a1" e010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var fft_bit_width))
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d "rur.ua_state_0 a1" f010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_0))
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d "rur.ua_state_1 a1" 0011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_1))
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d "rur.ua_state_2 a1" 1011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_2))
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d "rur.ua_state_3 a1" 2011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_3))
|
||||
d "s8i a1, a2, 0xff" 1242ff 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0xff))) (store 0 (var vAddr) (cast 8 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))))
|
||||
d "s16i a1, a2, 0x1fe" 1252ff 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1fe))) (storew 0 (var vAddr) (cast 16 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))))
|
||||
d "s32c1i a1, a2, 0x3fc" 12e2ff 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3fc))) (set mem (loadw 0 32 (var vAddr))) (branch (== (var mem) (var scompare1)) (storew 0 (var vAddr) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) nop) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var mem)))
|
||||
|
|
@ -298,21 +278,6 @@ d "wsr a1, br" 100413 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var wi
|
|||
d "wsr a1, litbase" 100513 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var litbase))
|
||||
d "wsr a1, scompare1" 100c13 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var scompare1))
|
||||
d "witlb a1, a2" 106250 0x0 nop
|
||||
d "wur.accx_1 a1" 1001f3 0x0 (set accx_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_h_0 a1" 1002f3 0x0 (set qacc_h_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_h_1 a1" 1003f3 0x0 (set qacc_h_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_h_2 a1" 1004f3 0x0 (set qacc_h_2 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_h_3 a1" 1005f3 0x0 (set qacc_h_3 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_h_4 a1" 1006f3 0x0 (set qacc_h_4 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_l_0 a1" 1007f3 0x0 (set qacc_l_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_l_1 a1" 1008f3 0x0 (set qacc_l_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_l_2 a1" 1009f3 0x0 (set qacc_l_2 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_l_3 a1" 100af3 0x0 (set qacc_l_3 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_l_4 a1" 100bf3 0x0 (set qacc_l_4 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.gpio_out a1" 100cf3 0x0 (set gpio_out (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.sar_byte a1" 100df3 0x0 (set sar_byte (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.fft_bit_width a1" 100ef3 0x0 (set fft_bit_width (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.ua_state_0 a1" 100ff3 0x0 (set ua_state_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "xsr a1, lend" 100161 0x0 (seq (set t0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var lend)) (set lend (var t0)))
|
||||
d "xsr a1, lcount" 100261 0x0 (seq (set t0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var lcount)) (set lcount (var t0)))
|
||||
d "xsr a1, sar" 100361 0x0 (seq (set t0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var sar)) (set sar (var t0)))
|
||||
|
|
|
|||
35
test/db/asm/xtensa_esp32s3_32
Normal file
35
test/db/asm/xtensa_esp32s3_32
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
d "rur.accx_0 a0" 0000e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_0))
|
||||
d "rur.accx_0 a1" 0010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_0))
|
||||
d "rur.accx_1 a1" 1010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_1))
|
||||
d "rur.qacc_h_0 a1" 2010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_0))
|
||||
d "rur.qacc_h_1 a1" 3010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_1))
|
||||
d "rur.qacc_h_2 a1" 4010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_2))
|
||||
d "rur.qacc_h_3 a1" 5010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_3))
|
||||
d "rur.qacc_h_4 a1" 6010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_4))
|
||||
d "rur.qacc_l_0 a1" 7010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_0))
|
||||
d "rur.qacc_l_1 a1" 8010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_1))
|
||||
d "rur.qacc_l_2 a1" 9010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_2))
|
||||
d "rur.qacc_l_3 a1" a010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_3))
|
||||
d "rur.qacc_l_4 a1" b010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_4))
|
||||
d "rur.gpio_out a1" c010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var gpio_out))
|
||||
d "rur.sar_byte a1" d010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var sar_byte))
|
||||
d "rur.fft_bit_width a1" e010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var fft_bit_width))
|
||||
d "rur.ua_state_0 a1" f010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_0))
|
||||
d "rur.ua_state_1 a1" 0011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_1))
|
||||
d "rur.ua_state_2 a1" 1011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_2))
|
||||
d "rur.ua_state_3 a1" 2011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_3))
|
||||
d "wur.accx_1 a1" 1001f3 0x0 (set accx_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_h_0 a1" 1002f3 0x0 (set qacc_h_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_h_1 a1" 1003f3 0x0 (set qacc_h_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_h_2 a1" 1004f3 0x0 (set qacc_h_2 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_h_3 a1" 1005f3 0x0 (set qacc_h_3 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_h_4 a1" 1006f3 0x0 (set qacc_h_4 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_l_0 a1" 1007f3 0x0 (set qacc_l_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_l_1 a1" 1008f3 0x0 (set qacc_l_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_l_2 a1" 1009f3 0x0 (set qacc_l_2 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_l_3 a1" 100af3 0x0 (set qacc_l_3 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.qacc_l_4 a1" 100bf3 0x0 (set qacc_l_4 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.gpio_out a1" 100cf3 0x0 (set gpio_out (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.sar_byte a1" 100df3 0x0 (set sar_byte (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.fft_bit_width a1" 100ef3 0x0 (set fft_bit_width (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
d "wur.ua_state_0 a1" 100ff3 0x0 (set ua_state_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))
|
||||
|
|
@ -124,6 +124,7 @@ noptr64 Special MIPS configuration to disable support for 64-bit pointer
|
|||
nofloat Special MIPS configuration to disable support for floating-points
|
||||
esp32 Xtensa microcontroller with Wi-Fi and Bluetooth capabilities
|
||||
esp32s2 Xtensa microcontroller with Wi-Fi and USB OTG support
|
||||
esp32s3 Xtensa microcontroller with Wi-Fi, USB OTG support, and HIFI3
|
||||
esp8266 Xtensa microcontroller with Wi-Fi support
|
||||
v8 ARMv8 version
|
||||
cortexm ARM Cortex-M family
|
||||
|
|
|
|||
|
|
@ -546,6 +546,7 @@ ARGS=-m xtensa
|
|||
EXPECT=<<EOF
|
||||
esp32 Xtensa microcontroller with Wi-Fi and Bluetooth capabilities
|
||||
esp32s2 Xtensa microcontroller with Wi-Fi and USB OTG support
|
||||
esp32s3 Xtensa microcontroller with Wi-Fi, USB OTG support, and HIFI3
|
||||
esp8266 Xtensa microcontroller with Wi-Fi support
|
||||
EOF
|
||||
RUN
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue