mirror of
https://github.com/rizinorg/rizin
synced 2026-08-22 20:26:16 -04:00
5c79c42a56
* Basic framework of rx implemented * Add match and parse flow * Add part of description for RxV1 instruction set * Add datasheet for rxv1 * Implement stringify op for rx * Add missing TST instruction in datasheet * Test to div instruction and fix bugs * Test known rxv1 instruction set * Fix bugs in rx disasm plugin and add SPDX * Add rz_analysis for renesas rx * Fix rz_analysis bug for renesas rx * Add rz_asm test and fix bug in datasheet * Add analysis test and fix bugs for renesas rx
204 lines
4.9 KiB
Text
204 lines
4.9 KiB
Text
d "itof.UB r1, r2," fc4712
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d "mov.W [r1], r2," dc12
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d "bclr r1, r2," fc6721
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d "itof 0x4[r1].L, r2," 06a1111204
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d "sub r1, r2, r3" ff0312
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d "xor.UB r1, r2," fc3712
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d "sub.UB r1, r2," 4312
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d "bmgeu #0x7, [r2]" fcfc22
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d "rts" 02
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d "emulu 0x4[r1].UW, r2," 06e1071204
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d "shlr #0x3, r1, r2" fd8312
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d "bset #0x7, [r2]," f027
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d "div 0x3[r1].B, r2," 0621081203
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d "divu.UB 0x3[r1], r2," fc251203
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d "divu [r1].L, r2," 06a00912
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d "mvtipl #0x2," 757002
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d "racw #0x0," fd1800
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d "mul.UB r1, r2," 4f12
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d "setpsw C," 7fa0
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d "add [r1].L, r2," 068812
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d "bltu.B #0x5," 2305
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d "mov.W [r1,r2], r3," fe5123
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d "or #0x8, r1," 6581
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d "bnot #0x1f, r2," fdfff2
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d "rmpa.W" 7f8d
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d "bclr r1, [r2]," fc6421
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d "cmp #0x7, r2," 6172
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d "emul #0xa, r2," fd74620a
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d "max #0xa, r2," fd74420a
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d "or r1, r2, r3" ff5312
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d "revw r1, r2," fd6512
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d "shlr #0x3, r2," 6832
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d "shar #0x3, r2," 6a32
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d "rtfi" 7f94
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d "shar r1, r2," fd6112
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d "or 0x2[r1].L, r2," 06951202
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d "smovb" 7f8b
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d "xor 0x4[r1].L, r2," 06a10d1204
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d "btst #0x7, [r2]," f427
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d "emul [r1].L, r2," 06a00612
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d "push.B r1," 7e81
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d "setpsw Z," 7fa1
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d "bra.L r2," 7f42
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d "mov #0x0, r2," 6602
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d "mov.W r1, [r2]," d321
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d "max 0x3[r1].B, r2," 0621041203
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d "max.UB r1, r2," fc1312
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d "fmul [r1], r2," fc8c12
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d "bra.L r1," 7f41
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d "mullo r1, r2," fd0112
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d "bsr.L r2," 7f52
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d "satr" 7f93
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d "add #0x7f, r1, r2" 71127f
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d "mov.B [-r1], r2," fd2c12
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d "and [r1].UW, r2," 06d012
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d "mvfachi r1," fd1f01
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d "clrpsw C," 7fb0
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d "bmeq #0x1f, r2" fdff02
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d "round [r1], r2," fc9812
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d "rotl r1, r2," fd6612
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d "btst r1, r2," fc6b21
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d "emul 0x4[r1].W, r2," 0661061204
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d "popc psw," 7ee0
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d "fdiv [r1], r2," fc9012
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d "neg r1, r2," fc0712
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d "emul.UB r1, r2," fc1b12
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d "mov.L r1, r2," ef12
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d "bnot r1, [r2]," fc6c21
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d "or [r1].L, r2," 069412
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d "movu.W 0x1[r1], r2," b81a
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d "mul #0xa, r2," 63a2
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d "bnot r1, r2," fc6f21
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d "mov.B r1, [r2+]," fd2021
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d "abs r0," 7e20
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d "neg r1," 7e11
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d "min #0xa, r2," fd74520a
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d "bsr.L r1," 7f51
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d "div.UB r1, r2," fc2312
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d "add #0xf, r2," 62f2
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d "rorc r1," 7e41
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d "scgeu.L r2," fcdb22
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d "suntil.W" 7f81
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d "or.UB r1, r2," 5712
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d "tst #0x7, r2," fd74c207
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d "add r1, r2, r3" ff2312
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d "mvtc r1, usp," fd6812
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d "divu.UB r1, r2," fc2712
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d "revl r1, r2," fd6712
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d "adc [r1].L, r2," 06a00212
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d "ftoi [r1], r2," fc9412
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d "machi r1, r2," fd0412
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d "sat r1," 7e31
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d "max [r1].L, r2," 06a00412
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d "mul [r1].L, r2," 068c12
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d "fsub [r1], r2," fc8012
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d "tst.UB 0x1[r1], r2," fc311201
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d "sbb [r1], r2," 06a00012
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d "sub #0xf, r2," 60f2
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d "mul r1, r2, r3" ff3312
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d "bra.W #0xfc8," 38c80f
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d "and #0xf, r2," 64f2
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d "btst r1, [r2]," fc6821
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d "mulhi r0, r0," fd0000
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d "rolc r1," 7e51
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d "bnot #0x7, [r2]," fcfc2f
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d "not r1," 7e01
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d "adc r1, r2," fc0b12
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d "emulu.UB r1, r2," fc1f12
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d "add.UB [r1], r2," 4812
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d "mul 0x2[r1].W, r2," 064d1202
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d "adc #0x7f, r2," fd74227f
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d "fmul r1, r2," fc8f12
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d "mvfacmi r1," fd1f21
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d "abs r1, r0," fc0f10
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d "cmp.UB r1, r2," 4712
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d "push.L [r1]," f41a
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d "btst #0x1f, r2," 7df2
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d "xor #0x8, r1," fd74d108
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d "maclo r1, r2," fd0512
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d "popm r4, r8," 6f48
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d "mov.B [r1+], r2," fd2812
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d "ftoi r1, r2," fc9712
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d "mvfc usp, r1," fd6a21
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d "rotr #0x1, r1," fd6c11
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d "bra.A #0x0," 04000000
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d "rtsd #0x1," 6701
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d "not r1, r2," fc3b12
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d "stz #0x1, r2," fd74e201
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d "swhile.W" 7f85
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d "div #0xa, r2," fd74820a
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d "fcmp r1, r2," fc8712
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d "bset r1, [r2]," fc6021
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d "emulu #0xa, r2," fd74720a
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d "bset r1, r2," fc6321
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d "fadd r1, r2," fc8b12
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d "itof [r1].L, r2," 06a01112
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d "cmp [r1].L, r2," 068412
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d "jmp r1," 7f01
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d "add.UB r1, r2," 4b12
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d "fcmp [r1], r2," fc8412
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d "mvtachi r1," fd1701
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d "clrpsw Z," 7fb1
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d "scmpu" 7f83
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d "rte" 7f95
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d "bclr #0x7, [r2]," f02f
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d "min 0x3[r1].B, r2," 0621051203
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d "mov.W r1, [r2,r3]," fe1231
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d "mvtaclo r1," fd1711
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d "round r1, r2," fc9b12
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d "bclr #0x1f, r2," 7bf2
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d "pushm r4, r8," 6e48
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d "rotr r1, r2," fd6412
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d "shar #0x3, r1, r2" fda312
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d "mov #0x80, r2," fb2680
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d "shll #0x3, r2," 6c32
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d "stnz #0x1, r2," fd74f201
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d "fsub r1, r2," fc8312
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d "pushm r1, r3," 6e13
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d "emulu [r1].L, r2," 06a00712
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d "rtsd #0x4, r7," 3f5704
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d "smovu" 7f87
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d "pop r1," 7eb1
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d "scne.W [r2]," fcd421
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d "mvtc #0xf000, intb," fd7b0c00f0
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d "mov #0x80, r2," 754280
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d "pushc psw," 7ec0
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d "rotl #0x1, r1," fd6e11
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d "and [r1].L, r2," 069012
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d "nop" 03
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d "shll #0x3, r1, r2" fdc312
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d "tst [r1].L, r2," 06a00c12
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d "brk" 00
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d "sub 0x1[r1].B, r2," 06011201
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d "wait" 7f96
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d "fadd [r1], r2," fc8812
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d "fdiv r1, r2," fc9312
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d "sstr.W" 7f89
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d "shll r1, r2," fd6212
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d "tst.UB r1, r2," fc3312
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d "sub [r1].L, r2," 068012
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d "sbb r1, r2," fc0312
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d "movu.W r1, r2," 5f12
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d "div [r1].L, r2," 06a00812
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d "mov.W [r1], [r2]," d012
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d "bset #0x1f, r2," 79f2
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d "int #0x0," 756000
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d "divu #0xa, r2," fd74920a
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d "smovf" 7f8f
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d "jsr r1," 7f11
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d "mulhi r1, r2," fd0012
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d "xchg.UB r1, r2," fc4312
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d "racw #0x1," fd1810
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d "movu.B [-r1], r2," fd3c12
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d "xchg [r1].W, r2," 06601012
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d "mov.L #0x0, [r2]," f82600
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d "xor [r1].L, r2," 06a00d12
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d "and.UB r1, r2," 5312
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d "and r1, r2, r3" ff4312
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d "min [r1].L, r2," 06a00512
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d "movu.B [r1+], r2," fd3812
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d "mov.B r1, [-r2]," fd2421
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d "popm r1, r3," 6f13
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d "bsr.A #0x0," 05000000
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d "min.UB r1, r2," fc1712
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