mmo-ref/dep-libtomcrypt
1
0
Fork 0
mirror of https://github.com/libtom/libtomcrypt synced 2026-08-25 20:26:07 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Use s_x86_cpuid() in s_{aesni,pclmul}_is_supported().

Browse source 
Hopefully at one point we can get rid of its duplication. Why again don't
we use inline functions as they should be used?

Signed-off-by: Steffen Jaeckel <s@jaeckel.eu>
This commit is contained in:
Steffen Jaeckel 2026-04-14 16:46:37 +02:00
parent e3bf539e5d
commit ec3804c452
2 changed files with 54 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

48
src/ciphers/aes/aes_desc.c
View file

@ -48,36 +48,42 @@ const struct ltc_cipher_descriptor aes_enc_desc =
#endif
/* Code partially borrowed from https://software.intel.com/content/www/us/en/develop/articles/intel-sha-extensions.html */
#if defined(LTC_AES_NI)
#if !defined (LTC_S_X86_CPUID)
#define LTC_S_X86_CPUID
static LTC_INLINE void s_x86_cpuid(int* regs, int leaf)
{
#if defined _MSC_VER
__cpuid(regs, leaf);
#else
int a, b, c, d;
a = leaf;
b = c = d = 0;
asm volatile ("cpuid"
:"=a"(a), "=b"(b), "=c"(c), "=d"(d)
:"a"(a), "c"(c)
);
regs[0] = a;
regs[1] = b;
regs[2] = c;
regs[3] = d;
#endif
}
#endif /* LTC_S_X86_CPUID */
static LTC_INLINE int s_aesni_is_supported(void)
{
static int initialized = 0, is_supported = 0;
if (initialized == 0) {
int a, b, c, d;
/* Look for CPUID.1.0.ECX[19] (SSE4.1) and CPUID.1.0.ECX[25] (AES-NI)
* EAX = 1, ECX = 0
*/
a = 1;
c = 0;
#if defined(_MSC_VER) && !defined(__clang__)
int arr[4];
__cpuidex(arr, a, c);
a = arr[0];
b = arr[1];
c = arr[2];
d = arr[3];
#else
__asm__ volatile ("cpuid"
:"=a"(a), "=b"(b), "=c"(c), "=d"(d)
:"a"(a), "c"(c)
);
#endif
is_supported = ((c >> 19) & 1) && ((c >> 25) & 1);
int regs[4];
s_x86_cpuid(regs, 1);
is_supported = ((regs[2] >> 19) & 1) && ((regs[2] >> 25) & 1);
initialized = 1;
}

43
src/encauth/gcm/gcm_gf_mult.c
View file

@ -21,27 +21,38 @@
#include <smmintrin.h>
#include <emmintrin.h>
#if !defined (LTC_S_X86_CPUID)
#define LTC_S_X86_CPUID
static LTC_INLINE void s_x86_cpuid(int* regs, int leaf)
{
#if defined _MSC_VER
__cpuid(regs, leaf);
#else
int a, b, c, d;
a = leaf;
b = c = d = 0;
asm volatile ("cpuid"
:"=a"(a), "=b"(b), "=c"(c), "=d"(d)
:"a"(a), "c"(c)
);
regs[0] = a;
regs[1] = b;
regs[2] = c;
regs[3] = d;
#endif
}
#endif /* LTC_S_X86_CPUID */
static LTC_INLINE int s_pclmul_is_supported(void)
{
static int initialized = 0, is_supported = 0;
if (initialized == 0) {
/* Test CPUID.1.0.ECX[1]
* EAX = 1, ECX = 0 */
#if defined(_MSC_VER)
int cpuInfo[4];
__cpuid(cpuInfo, 1);
is_supported = ((cpuInfo[2] >> 1) & 1);
#else
int a = 1 , b, c = 0, d;
asm volatile ("cpuid"
:"=a"(a), "=b"(b), "=c"(c), "=d"(d)
:"a"(a), "c"(c)
);
is_supported = ((c >> 1) & 1);
#endif
int regs[4];
s_x86_cpuid(regs, 1);
/* Test CPUID.1.0.ECX[1] (PCLMUL) and CPUID.1.0.ECX[9] (SSSE3) */
is_supported = ((regs[2] >> 1) & 1) && ((regs[2] >> 9) & 1);
initialized = 1;
}