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cpld-clean
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3d517954c5 | ||
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c6a1f82340 | ||
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dc80d0207a |
3 changed files with 68 additions and 68 deletions
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@ -1,4 +1,5 @@
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#
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# Copyright 2012-2022 Great Scott Gadgets <info@greatscottgadgets.com>
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# Copyright 2012 Jared Boone
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#
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# This file is part of HackRF.
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@ -26,47 +27,47 @@ TIMEGRP "adc_data" OFFSET = IN 16 ns BEFORE "CODEC_X2_CLK";
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TIMEGRP "dac_data" OFFSET = OUT 15 ns AFTER "CODEC_X2_CLK";
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TIMEGRP "to_host" OFFSET = OUT 20 ns AFTER "CODEC_X2_CLK";
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#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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NET "CODEC_CLK" LOC = "P23" ;
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NET "CODEC_X2_CLK" LOC = "P27" ;
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NET "DA<0>" LOC = "P43" ;
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NET "DA<1>" LOC = "P42" ;
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NET "DA<2>" LOC = "P41" ;
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NET "DA<3>" LOC = "P40" ;
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NET "DA<4>" LOC = "P39" ;
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NET "DA<5>" LOC = "P37" ;
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NET "DA<6>" LOC = "P36" ;
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NET "DA<7>" LOC = "P35" ;
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NET "DD<0>" LOC = "P34" ;
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NET "DD<1>" LOC = "P33" ;
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NET "DD<2>" LOC = "P32" ;
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NET "DD<3>" LOC = "P30" ;
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NET "DD<4>" LOC = "P29" ;
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NET "DD<5>" LOC = "P28" ;
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NET "DD<6>" LOC = "P24" ;
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NET "DD<7>" LOC = "P19" ;
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NET "DD<8>" LOC = "P18" ;
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NET "DD<9>" LOC = "P17" ;
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NET "HOST_CAPTURE" LOC = "P91" ;
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NET "HOST_DATA<0>" LOC = "P89" ;
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NET "HOST_DATA<1>" LOC = "P79" ;
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NET "HOST_DATA<2>" LOC = "P74" ;
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NET "HOST_DATA<3>" LOC = "P72" ;
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NET "HOST_DATA<4>" LOC = "P67" ;
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NET "HOST_DATA<5>" LOC = "P64" ;
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NET "HOST_DATA<6>" LOC = "P61" ;
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NET "HOST_DATA<7>" LOC = "P77" ;
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NET "HOST_DIRECTION" LOC = "P71" ;
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NET "HOST_DISABLE" LOC = "P76" ;
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NET "HOST_Q_INVERT" LOC = "P70" ;
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NET "HOST_SYNC_EN" LOC = "P90" ;
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NET "HOST_SYNC" LOC = "P55" | PULLUP ;
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NET "HOST_SYNC_CMD" LOC = "P56" ;
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#PACE: Start of PACE Area Constraints
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#PACE: Start of PACE Prohibit Constraints
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#PACE: End of Constraints generated by PACE
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#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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NET "CODEC_CLK" LOC = "P23" ;
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NET "CODEC_X2_CLK" LOC = "P27" ;
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NET "DA<0>" LOC = "P43" ;
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NET "DA<1>" LOC = "P42" ;
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NET "DA<2>" LOC = "P41" ;
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NET "DA<3>" LOC = "P40" ;
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NET "DA<4>" LOC = "P39" ;
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NET "DA<5>" LOC = "P37" ;
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NET "DA<6>" LOC = "P36" ;
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NET "DA<7>" LOC = "P35" ;
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NET "DD<0>" LOC = "P34" ;
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NET "DD<1>" LOC = "P33" ;
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NET "DD<2>" LOC = "P32" ;
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NET "DD<3>" LOC = "P30" ;
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NET "DD<4>" LOC = "P29" ;
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NET "DD<5>" LOC = "P28" ;
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NET "DD<6>" LOC = "P24" ;
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NET "DD<7>" LOC = "P19" ;
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NET "DD<8>" LOC = "P18" ;
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NET "DD<9>" LOC = "P17" ;
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NET "HOST_CAPTURE" LOC = "P91" ;
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NET "HOST_DATA<0>" LOC = "P89" ;
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NET "HOST_DATA<1>" LOC = "P79" ;
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NET "HOST_DATA<2>" LOC = "P74" ;
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NET "HOST_DATA<3>" LOC = "P72" ;
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NET "HOST_DATA<4>" LOC = "P67" ;
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NET "HOST_DATA<5>" LOC = "P64" ;
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NET "HOST_DATA<6>" LOC = "P61" ;
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NET "HOST_DATA<7>" LOC = "P77" ;
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NET "HOST_DIRECTION" LOC = "P71" ;
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NET "HOST_DISABLE" LOC = "P76" ;
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NET "HOST_Q_INVERT" LOC = "P70" ;
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NET "HOST_SYNC_EN" LOC = "P90" ;
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NET "HOST_SYNC" LOC = "P55" | PULLUP ;
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NET "HOST_SYNC_CMD" LOC = "P56" ;
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#PACE: Start of PACE Area Constraints
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#PACE: Start of PACE Prohibit Constraints
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#PACE: End of Constraints generated by PACE
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@ -1,4 +1,5 @@
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--
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-- Copyright 2012-2022 Great Scott Gadgets <info@greatscottgadgets.com>
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-- Copyright 2012 Jared Boone
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-- Copyright 2013 Benjamin Vernoux
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--
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@ -29,8 +30,8 @@ use UNISIM.vcomponents.all;
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entity top is
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Port(
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HOST_DATA : inout std_logic_vector(7 downto 0);
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HOST_CAPTURE : out std_logic;
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HOST_SYNC_EN : in std_logic;
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HOST_CAPTURE : out std_logic;
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HOST_SYNC_EN : in std_logic;
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HOST_SYNC_CMD : out std_logic;
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HOST_SYNC : in std_logic;
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HOST_DISABLE : in std_logic;
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@ -58,8 +59,8 @@ architecture Behavioral of top is
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signal transfer_direction_i : transfer_direction;
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signal host_data_enable_i : std_logic;
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signal host_data_capture_o : std_logic;
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signal host_sync_enable : std_logic := '0';
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signal host_data_capture_o : std_logic;
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signal host_sync_enable : std_logic := '0';
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signal host_sync_o : std_logic := '0';
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signal host_sync_i : std_logic := '0';
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signal host_sync_latched : std_logic := '0';
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@ -93,11 +94,11 @@ begin
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HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
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else (others => 'Z');
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HOST_CAPTURE <= host_data_capture_o;
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host_sync_enable <= HOST_SYNC_EN;
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host_sync_i <= HOST_SYNC;
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HOST_SYNC_CMD <= host_sync_o;
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HOST_CAPTURE <= host_data_capture_o;
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host_sync_enable <= HOST_SYNC_EN;
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host_sync_i <= HOST_SYNC;
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HOST_SYNC_CMD <= host_sync_o;
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host_data_enable_i <= not HOST_DISABLE;
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transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
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else from_adc;
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@ -1,4 +1,5 @@
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--
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-- Copyright 2012-2022 Great Scott Gadgets <info@greatscottgadgets.com>
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-- Copyright 2012 Jared Boone
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--
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-- This file is part of HackRF.
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@ -31,8 +32,7 @@ ARCHITECTURE behavior OF top_tb IS
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HOST_DATA : INOUT std_logic_vector(7 downto 0);
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HOST_CAPTURE : OUT std_logic;
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HOST_DISABLE : IN std_logic;
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HOST_DIRECTION : IN std_logic;
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HOST_DECIM_SEL : IN std_logic_vector(2 downto 0);
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HOST_DIRECTION : IN std_logic;
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DA : IN std_logic_vector(7 downto 0);
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DD : OUT std_logic_vector(9 downto 0);
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CODEC_CLK : IN std_logic;
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@ -45,13 +45,12 @@ ARCHITECTURE behavior OF top_tb IS
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signal CODEC_CLK : std_logic := '0';
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signal CODEC_X2_CLK : std_logic := '0';
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signal HOST_DISABLE : std_logic := '1';
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signal HOST_DIRECTION : std_logic := '0';
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signal HOST_DECIM_SEL : std_logic_vector(2 downto 0) := "010";
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signal HOST_DIRECTION : std_logic := '0';
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--BiDirs
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--BiDirs
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signal HOST_DATA : std_logic_vector(7 downto 0);
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--Outputs
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--Outputs
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signal DD : std_logic_vector(9 downto 0);
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signal HOST_CAPTURE : std_logic;
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@ -61,8 +60,7 @@ begin
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HOST_DATA => HOST_DATA,
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HOST_CAPTURE => HOST_CAPTURE,
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HOST_DISABLE => HOST_DISABLE,
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HOST_DIRECTION => HOST_DIRECTION,
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HOST_DECIM_SEL => HOST_DECIM_SEL,
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HOST_DIRECTION => HOST_DIRECTION,
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DA => DA,
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DD => DD,
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CODEC_CLK => CODEC_CLK,
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@ -71,15 +69,15 @@ begin
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clk_process :process
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begin
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CODEC_CLK <= '1';
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CODEC_CLK <= '1';
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CODEC_X2_CLK <= '1';
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wait for 12.5 ns;
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CODEC_X2_CLK <= '0';
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wait for 12.5 ns;
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wait for 12.5 ns;
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CODEC_X2_CLK <= '0';
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wait for 12.5 ns;
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CODEC_CLK <= '0';
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CODEC_X2_CLK <= '1';
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wait for 12.5 ns;
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CODEC_X2_CLK <= '0';
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wait for 12.5 ns;
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CODEC_X2_CLK <= '0';
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wait for 12.5 ns;
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end process;
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@ -129,4 +127,4 @@ begin
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wait;
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end process;
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end;
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end;
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