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x86: fix {er} decorator placement for integer-source VCVT* instructions
For `VCVTUSI2SD`, `VCVTUSI2SS`, and `VCVTUSI2SH`, the `|er` flag in
`insns.dat` was attached to the XMM pass-through source (operand 2, the
vvvv field) rather than the integer source (operand 3, the rm field).
This caused NASM to require the embedded-rounding decorator before the
integer register rather than after it, which is wrong; the correct
syntax is `vcvtusi2ss xmm0,xmm1,eax,{rn-sae}`, not `vcvtusi2ss
xmm0,xmm1,{rn-sae},eax`.
Move `|er` to the integer source operand for all six affected entries,
and change the XMM source from `xmmreg|er` to `xmmreg*` (optional
duplicate of the destination, consistent with every other scalar
integer-to-float convert in the file).
Also fix a copy-paste error in `insns.dat` where the second `VCVTUSI2SH`
entry (W=1, rm64) was mis-labeled as `VCVTUSI2SS`.
Update `travis/test/avx512f.asm` to use the correct decorator syntax
(`reg,{rN-sae}` instead of `{rN-sae},reg`) for the ER forms of
`VCVTSI2SD`, `VCVTSI2SS`, `VCVTUSI2SD`, and `VCVTUSI2SS`; regenerate the
golden `avx512f.bin.t`. The encoded bytes are unchanged.
`travis/test/avx512f.json` had a trailing comma after the last field of
the JSON object, making it invalid JSON. Remove the trailing comma.
Signed-off-by: Joe Konno <joe.konno@intel.com>
Fixes: https://github.com/netwide-assembler/nasm/pull/229
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
This commit is contained in:
Joe Konno
H. Peter Anvin (Intel)
parent
d2541cb884
commit
6d8ea837c6
4 changed files with 63 additions and 63 deletions
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@ -2475,15 +2475,15 @@ testcase { 0x62, 0x61, 0x17, 0x00, 0x2a, 0xb2, 0x00, 0x02, 0x00, 0x00
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testcase { 0x62, 0x61, 0x17, 0x00, 0x2a, 0x72, 0x80 }, { vcvtsi2sd xmm30,xmm29,DWORD [rdx-0x200] }
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testcase { 0x62, 0x61, 0x17, 0x00, 0x2a, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vcvtsi2sd xmm30,xmm29,DWORD [rdx-0x204] }
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testcase { 0x62, 0x61, 0x97, 0x00, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,rax }
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testcase { 0x62, 0x61, 0x97, 0x10, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,{rn-sae},rax }
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testcase { 0x62, 0x61, 0x97, 0x50, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,{ru-sae},rax }
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testcase { 0x62, 0x61, 0x97, 0x30, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,{rd-sae},rax }
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testcase { 0x62, 0x61, 0x97, 0x70, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,{rz-sae},rax }
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testcase { 0x62, 0x61, 0x97, 0x10, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,rax,{rn-sae} }
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testcase { 0x62, 0x61, 0x97, 0x50, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,rax,{ru-sae} }
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testcase { 0x62, 0x61, 0x97, 0x30, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,rax,{rd-sae} }
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testcase { 0x62, 0x61, 0x97, 0x70, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,rax,{rz-sae} }
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testcase { 0x62, 0x41, 0x97, 0x00, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,r8 }
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testcase { 0x62, 0x41, 0x97, 0x10, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,{rn-sae},r8 }
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testcase { 0x62, 0x41, 0x97, 0x50, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,{ru-sae},r8 }
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testcase { 0x62, 0x41, 0x97, 0x30, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,{rd-sae},r8 }
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testcase { 0x62, 0x41, 0x97, 0x70, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,{rz-sae},r8 }
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testcase { 0x62, 0x41, 0x97, 0x10, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,r8,{rn-sae} }
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testcase { 0x62, 0x41, 0x97, 0x50, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,r8,{ru-sae} }
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testcase { 0x62, 0x41, 0x97, 0x30, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,r8,{rd-sae} }
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testcase { 0x62, 0x41, 0x97, 0x70, 0x2a, 0xf0 }, { vcvtsi2sd xmm30,xmm29,r8,{rz-sae} }
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testcase { 0x62, 0x61, 0x97, 0x00, 0x2a, 0x31 }, { vcvtsi2sd xmm30,xmm29,QWORD [rcx] }
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testcase { 0x62, 0x21, 0x97, 0x00, 0x2a, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vcvtsi2sd xmm30,xmm29,QWORD [rax+r14*8+0x123] }
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testcase { 0x62, 0x61, 0x97, 0x00, 0x2a, 0x72, 0x7f }, { vcvtsi2sd xmm30,xmm29,QWORD [rdx+0x3f8] }
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@ -2491,20 +2491,20 @@ testcase { 0x62, 0x61, 0x97, 0x00, 0x2a, 0xb2, 0x00, 0x04, 0x00, 0x00
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testcase { 0x62, 0x61, 0x97, 0x00, 0x2a, 0x72, 0x80 }, { vcvtsi2sd xmm30,xmm29,QWORD [rdx-0x400] }
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testcase { 0x62, 0x61, 0x97, 0x00, 0x2a, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vcvtsi2sd xmm30,xmm29,QWORD [rdx-0x408] }
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testcase { 0x62, 0x61, 0x16, 0x00, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,eax }
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testcase { 0x62, 0x61, 0x16, 0x10, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,{rn-sae},eax }
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testcase { 0x62, 0x61, 0x16, 0x50, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,{ru-sae},eax }
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testcase { 0x62, 0x61, 0x16, 0x30, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,{rd-sae},eax }
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testcase { 0x62, 0x61, 0x16, 0x70, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,{rz-sae},eax }
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testcase { 0x62, 0x61, 0x16, 0x10, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,eax,{rn-sae} }
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testcase { 0x62, 0x61, 0x16, 0x50, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,eax,{ru-sae} }
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testcase { 0x62, 0x61, 0x16, 0x30, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,eax,{rd-sae} }
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testcase { 0x62, 0x61, 0x16, 0x70, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,eax,{rz-sae} }
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testcase { 0x62, 0x61, 0x16, 0x00, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,ebp }
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testcase { 0x62, 0x61, 0x16, 0x10, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,{rn-sae},ebp }
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testcase { 0x62, 0x61, 0x16, 0x50, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,{ru-sae},ebp }
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testcase { 0x62, 0x61, 0x16, 0x30, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,{rd-sae},ebp }
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testcase { 0x62, 0x61, 0x16, 0x70, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,{rz-sae},ebp }
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testcase { 0x62, 0x61, 0x16, 0x10, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,ebp,{rn-sae} }
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testcase { 0x62, 0x61, 0x16, 0x50, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,ebp,{ru-sae} }
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testcase { 0x62, 0x61, 0x16, 0x30, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,ebp,{rd-sae} }
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testcase { 0x62, 0x61, 0x16, 0x70, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,ebp,{rz-sae} }
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testcase { 0x62, 0x41, 0x16, 0x00, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,r13d }
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testcase { 0x62, 0x41, 0x16, 0x10, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,{rn-sae},r13d }
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testcase { 0x62, 0x41, 0x16, 0x50, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,{ru-sae},r13d }
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testcase { 0x62, 0x41, 0x16, 0x30, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,{rd-sae},r13d }
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testcase { 0x62, 0x41, 0x16, 0x70, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,{rz-sae},r13d }
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testcase { 0x62, 0x41, 0x16, 0x10, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,r13d,{rn-sae} }
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testcase { 0x62, 0x41, 0x16, 0x50, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,r13d,{ru-sae} }
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testcase { 0x62, 0x41, 0x16, 0x30, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,r13d,{rd-sae} }
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testcase { 0x62, 0x41, 0x16, 0x70, 0x2a, 0xf5 }, { vcvtsi2ss xmm30,xmm29,r13d,{rz-sae} }
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testcase { 0x62, 0x61, 0x16, 0x00, 0x2a, 0x31 }, { vcvtsi2ss xmm30,xmm29,DWORD [rcx] }
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testcase { 0x62, 0x21, 0x16, 0x00, 0x2a, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vcvtsi2ss xmm30,xmm29,DWORD [rax+r14*8+0x123] }
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testcase { 0x62, 0x61, 0x16, 0x00, 0x2a, 0x72, 0x7f }, { vcvtsi2ss xmm30,xmm29,DWORD [rdx+0x1fc] }
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@ -2512,15 +2512,15 @@ testcase { 0x62, 0x61, 0x16, 0x00, 0x2a, 0xb2, 0x00, 0x02, 0x00, 0x00
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testcase { 0x62, 0x61, 0x16, 0x00, 0x2a, 0x72, 0x80 }, { vcvtsi2ss xmm30,xmm29,DWORD [rdx-0x200] }
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testcase { 0x62, 0x61, 0x16, 0x00, 0x2a, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vcvtsi2ss xmm30,xmm29,DWORD [rdx-0x204] }
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testcase { 0x62, 0x61, 0x96, 0x00, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,rax }
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testcase { 0x62, 0x61, 0x96, 0x10, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,{rn-sae},rax }
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testcase { 0x62, 0x61, 0x96, 0x50, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,{ru-sae},rax }
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testcase { 0x62, 0x61, 0x96, 0x30, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,{rd-sae},rax }
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testcase { 0x62, 0x61, 0x96, 0x70, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,{rz-sae},rax }
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testcase { 0x62, 0x61, 0x96, 0x10, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,rax,{rn-sae} }
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testcase { 0x62, 0x61, 0x96, 0x50, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,rax,{ru-sae} }
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testcase { 0x62, 0x61, 0x96, 0x30, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,rax,{rd-sae} }
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testcase { 0x62, 0x61, 0x96, 0x70, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,rax,{rz-sae} }
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testcase { 0x62, 0x41, 0x96, 0x00, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,r8 }
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testcase { 0x62, 0x41, 0x96, 0x10, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,{rn-sae},r8 }
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testcase { 0x62, 0x41, 0x96, 0x50, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,{ru-sae},r8 }
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testcase { 0x62, 0x41, 0x96, 0x30, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,{rd-sae},r8 }
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testcase { 0x62, 0x41, 0x96, 0x70, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,{rz-sae},r8 }
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testcase { 0x62, 0x41, 0x96, 0x10, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,r8,{rn-sae} }
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testcase { 0x62, 0x41, 0x96, 0x50, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,r8,{ru-sae} }
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testcase { 0x62, 0x41, 0x96, 0x30, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,r8,{rd-sae} }
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testcase { 0x62, 0x41, 0x96, 0x70, 0x2a, 0xf0 }, { vcvtsi2ss xmm30,xmm29,r8,{rz-sae} }
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testcase { 0x62, 0x61, 0x96, 0x00, 0x2a, 0x31 }, { vcvtsi2ss xmm30,xmm29,QWORD [rcx] }
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testcase { 0x62, 0x21, 0x96, 0x00, 0x2a, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vcvtsi2ss xmm30,xmm29,QWORD [rax+r14*8+0x123] }
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testcase { 0x62, 0x61, 0x96, 0x00, 0x2a, 0x72, 0x7f }, { vcvtsi2ss xmm30,xmm29,QWORD [rdx+0x3f8] }
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@ -6199,15 +6199,15 @@ testcase { 0x62, 0x61, 0x17, 0x00, 0x7b, 0xb2, 0x00, 0x02, 0x00, 0x00
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testcase { 0x62, 0x61, 0x17, 0x00, 0x7b, 0x72, 0x80 }, { vcvtusi2sd xmm30,xmm29,DWORD [rdx-0x200] }
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testcase { 0x62, 0x61, 0x17, 0x00, 0x7b, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vcvtusi2sd xmm30,xmm29,DWORD [rdx-0x204] }
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testcase { 0x62, 0x61, 0x97, 0x00, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,rax }
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testcase { 0x62, 0x61, 0x97, 0x10, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,{rn-sae},rax }
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testcase { 0x62, 0x61, 0x97, 0x50, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,{ru-sae},rax }
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testcase { 0x62, 0x61, 0x97, 0x30, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,{rd-sae},rax }
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testcase { 0x62, 0x61, 0x97, 0x70, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,{rz-sae},rax }
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testcase { 0x62, 0x61, 0x97, 0x10, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,rax,{rn-sae} }
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testcase { 0x62, 0x61, 0x97, 0x50, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,rax,{ru-sae} }
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testcase { 0x62, 0x61, 0x97, 0x30, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,rax,{rd-sae} }
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testcase { 0x62, 0x61, 0x97, 0x70, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,rax,{rz-sae} }
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testcase { 0x62, 0x41, 0x97, 0x00, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,r8 }
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testcase { 0x62, 0x41, 0x97, 0x10, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,{rn-sae},r8 }
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testcase { 0x62, 0x41, 0x97, 0x50, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,{ru-sae},r8 }
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testcase { 0x62, 0x41, 0x97, 0x30, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,{rd-sae},r8 }
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testcase { 0x62, 0x41, 0x97, 0x70, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,{rz-sae},r8 }
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testcase { 0x62, 0x41, 0x97, 0x10, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,r8,{rn-sae} }
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testcase { 0x62, 0x41, 0x97, 0x50, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,r8,{ru-sae} }
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testcase { 0x62, 0x41, 0x97, 0x30, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,r8,{rd-sae} }
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testcase { 0x62, 0x41, 0x97, 0x70, 0x7b, 0xf0 }, { vcvtusi2sd xmm30,xmm29,r8,{rz-sae} }
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testcase { 0x62, 0x61, 0x97, 0x00, 0x7b, 0x31 }, { vcvtusi2sd xmm30,xmm29,QWORD [rcx] }
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testcase { 0x62, 0x21, 0x97, 0x00, 0x7b, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vcvtusi2sd xmm30,xmm29,QWORD [rax+r14*8+0x123] }
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testcase { 0x62, 0x61, 0x97, 0x00, 0x7b, 0x72, 0x7f }, { vcvtusi2sd xmm30,xmm29,QWORD [rdx+0x3f8] }
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@ -6215,20 +6215,20 @@ testcase { 0x62, 0x61, 0x97, 0x00, 0x7b, 0xb2, 0x00, 0x04, 0x00, 0x00
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testcase { 0x62, 0x61, 0x97, 0x00, 0x7b, 0x72, 0x80 }, { vcvtusi2sd xmm30,xmm29,QWORD [rdx-0x400] }
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testcase { 0x62, 0x61, 0x97, 0x00, 0x7b, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vcvtusi2sd xmm30,xmm29,QWORD [rdx-0x408] }
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testcase { 0x62, 0x61, 0x16, 0x00, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,eax }
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testcase { 0x62, 0x61, 0x16, 0x10, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,{rn-sae},eax }
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testcase { 0x62, 0x61, 0x16, 0x50, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,{ru-sae},eax }
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testcase { 0x62, 0x61, 0x16, 0x30, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,{rd-sae},eax }
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testcase { 0x62, 0x61, 0x16, 0x70, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,{rz-sae},eax }
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testcase { 0x62, 0x61, 0x16, 0x10, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,eax,{rn-sae} }
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testcase { 0x62, 0x61, 0x16, 0x50, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,eax,{ru-sae} }
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testcase { 0x62, 0x61, 0x16, 0x30, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,eax,{rd-sae} }
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testcase { 0x62, 0x61, 0x16, 0x70, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,eax,{rz-sae} }
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testcase { 0x62, 0x61, 0x16, 0x00, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,ebp }
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testcase { 0x62, 0x61, 0x16, 0x10, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,{rn-sae},ebp }
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testcase { 0x62, 0x61, 0x16, 0x50, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,{ru-sae},ebp }
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testcase { 0x62, 0x61, 0x16, 0x30, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,{rd-sae},ebp }
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testcase { 0x62, 0x61, 0x16, 0x70, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,{rz-sae},ebp }
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testcase { 0x62, 0x61, 0x16, 0x10, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,ebp,{rn-sae} }
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testcase { 0x62, 0x61, 0x16, 0x50, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,ebp,{ru-sae} }
|
||||
testcase { 0x62, 0x61, 0x16, 0x30, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,ebp,{rd-sae} }
|
||||
testcase { 0x62, 0x61, 0x16, 0x70, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,ebp,{rz-sae} }
|
||||
testcase { 0x62, 0x41, 0x16, 0x00, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,r13d }
|
||||
testcase { 0x62, 0x41, 0x16, 0x10, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,{rn-sae},r13d }
|
||||
testcase { 0x62, 0x41, 0x16, 0x50, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,{ru-sae},r13d }
|
||||
testcase { 0x62, 0x41, 0x16, 0x30, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,{rd-sae},r13d }
|
||||
testcase { 0x62, 0x41, 0x16, 0x70, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,{rz-sae},r13d }
|
||||
testcase { 0x62, 0x41, 0x16, 0x10, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,r13d,{rn-sae} }
|
||||
testcase { 0x62, 0x41, 0x16, 0x50, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,r13d,{ru-sae} }
|
||||
testcase { 0x62, 0x41, 0x16, 0x30, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,r13d,{rd-sae} }
|
||||
testcase { 0x62, 0x41, 0x16, 0x70, 0x7b, 0xf5 }, { vcvtusi2ss xmm30,xmm29,r13d,{rz-sae} }
|
||||
testcase { 0x62, 0x61, 0x16, 0x00, 0x7b, 0x31 }, { vcvtusi2ss xmm30,xmm29,DWORD [rcx] }
|
||||
testcase { 0x62, 0x21, 0x16, 0x00, 0x7b, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vcvtusi2ss xmm30,xmm29,DWORD [rax+r14*8+0x123] }
|
||||
testcase { 0x62, 0x61, 0x16, 0x00, 0x7b, 0x72, 0x7f }, { vcvtusi2ss xmm30,xmm29,DWORD [rdx+0x1fc] }
|
||||
|
|
@ -6236,15 +6236,15 @@ testcase { 0x62, 0x61, 0x16, 0x00, 0x7b, 0xb2, 0x00, 0x02, 0x00, 0x00
|
|||
testcase { 0x62, 0x61, 0x16, 0x00, 0x7b, 0x72, 0x80 }, { vcvtusi2ss xmm30,xmm29,DWORD [rdx-0x200] }
|
||||
testcase { 0x62, 0x61, 0x16, 0x00, 0x7b, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vcvtusi2ss xmm30,xmm29,DWORD [rdx-0x204] }
|
||||
testcase { 0x62, 0x61, 0x96, 0x00, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,rax }
|
||||
testcase { 0x62, 0x61, 0x96, 0x10, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,{rn-sae},rax }
|
||||
testcase { 0x62, 0x61, 0x96, 0x50, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,{ru-sae},rax }
|
||||
testcase { 0x62, 0x61, 0x96, 0x30, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,{rd-sae},rax }
|
||||
testcase { 0x62, 0x61, 0x96, 0x70, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,{rz-sae},rax }
|
||||
testcase { 0x62, 0x61, 0x96, 0x10, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,rax,{rn-sae} }
|
||||
testcase { 0x62, 0x61, 0x96, 0x50, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,rax,{ru-sae} }
|
||||
testcase { 0x62, 0x61, 0x96, 0x30, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,rax,{rd-sae} }
|
||||
testcase { 0x62, 0x61, 0x96, 0x70, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,rax,{rz-sae} }
|
||||
testcase { 0x62, 0x41, 0x96, 0x00, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,r8 }
|
||||
testcase { 0x62, 0x41, 0x96, 0x10, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,{rn-sae},r8 }
|
||||
testcase { 0x62, 0x41, 0x96, 0x50, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,{ru-sae},r8 }
|
||||
testcase { 0x62, 0x41, 0x96, 0x30, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,{rd-sae},r8 }
|
||||
testcase { 0x62, 0x41, 0x96, 0x70, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,{rz-sae},r8 }
|
||||
testcase { 0x62, 0x41, 0x96, 0x10, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,r8,{rn-sae} }
|
||||
testcase { 0x62, 0x41, 0x96, 0x50, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,r8,{ru-sae} }
|
||||
testcase { 0x62, 0x41, 0x96, 0x30, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,r8,{rd-sae} }
|
||||
testcase { 0x62, 0x41, 0x96, 0x70, 0x7b, 0xf0 }, { vcvtusi2ss xmm30,xmm29,r8,{rz-sae} }
|
||||
testcase { 0x62, 0x61, 0x96, 0x00, 0x7b, 0x31 }, { vcvtusi2ss xmm30,xmm29,QWORD [rcx] }
|
||||
testcase { 0x62, 0x21, 0x96, 0x00, 0x7b, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vcvtusi2ss xmm30,xmm29,QWORD [rax+r14*8+0x123] }
|
||||
testcase { 0x62, 0x61, 0x96, 0x00, 0x7b, 0x72, 0x7f }, { vcvtusi2ss xmm30,xmm29,QWORD [rdx+0x3f8] }
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -7,6 +7,6 @@
|
|||
"option": "-O0 -DSRC",
|
||||
"target": [
|
||||
{ "output": "avx512f.bin" }
|
||||
],
|
||||
]
|
||||
}
|
||||
]
|
||||
|
|
|
|||
|
|
@ -3633,10 +3633,10 @@ VCVTUQQ2PD zmmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.f3.0f.w1 7a
|
|||
VCVTUQQ2PS xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.f2.0f.w1 7a /r ] AVX512VL,AVX512DQ
|
||||
VCVTUQQ2PS xmmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.f2.0f.w1 7a /r ] AVX512VL,AVX512DQ
|
||||
VCVTUQQ2PS ymmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.f2.0f.w1 7a /r ] AVX512DQ
|
||||
VCVTUSI2SD xmmreg,xmmreg|er,rm32 [rvm:t1s: evex.nds.lig.f2.0f.w0 7b /r ] AVX512
|
||||
VCVTUSI2SD xmmreg,xmmreg|er,rm64 [rvm:t1s: evex.nds.lig.f2.0f.w1 7b /r ] AVX512
|
||||
VCVTUSI2SS xmmreg,xmmreg|er,rm32 [rvm:t1s: evex.nds.lig.f3.0f.w0 7b /r ] AVX512
|
||||
VCVTUSI2SS xmmreg,xmmreg|er,rm64 [rvm:t1s: evex.nds.lig.f3.0f.w1 7b /r ] AVX512
|
||||
VCVTUSI2SD xmmreg,xmmreg*,rm32|er [rvm:t1s: evex.nds.lig.f2.0f.w0 7b /r ] AVX512
|
||||
VCVTUSI2SD xmmreg,xmmreg*,rm64|er [rvm:t1s: evex.nds.lig.f2.0f.w1 7b /r ] AVX512
|
||||
VCVTUSI2SS xmmreg,xmmreg*,rm32|er [rvm:t1s: evex.nds.lig.f3.0f.w0 7b /r ] AVX512
|
||||
VCVTUSI2SS xmmreg,xmmreg*,rm64|er [rvm:t1s: evex.nds.lig.f3.0f.w1 7b /r ] AVX512
|
||||
VDBPSADBW xmmreg|mask|z,xmmreg*,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w0 42 /r ib ] AVX512VL,AVX512BW
|
||||
VDBPSADBW ymmreg|mask|z,ymmreg*,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w0 42 /r ib ] AVX512VL,AVX512BW
|
||||
VDBPSADBW zmmreg|mask|z,zmmreg*,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w0 42 /r ib ] AVX512BW
|
||||
|
|
@ -5529,8 +5529,8 @@ VCVTUDQ2PH ymmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.f2.map5.w0 7a /r] AVX512F
|
|||
VCVTUQQ2PH xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.f2.map5.w1 7a /r] AVX512FP16,AVX512VL
|
||||
VCVTUQQ2PH xmmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.f2.map5.w1 7a /r] AVX512FP16,AVX512VL
|
||||
VCVTUQQ2PH xmmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.f2.map5.w1 7a /r] AVX512FP16
|
||||
VCVTUSI2SH xmmreg,xmmreg|er,rm32|er [rvm:t1s: evex.nds.lig.f3.map5.w0 7b /r] AVX512FP16
|
||||
VCVTUSI2SS xmmreg,xmmreg|er,rm64|er [rvm:t1s: evex.nds.lig.f3.map5.w1 7b /r] AVX512FP16
|
||||
VCVTUSI2SH xmmreg,xmmreg*,rm32|er [rvm:t1s: evex.nds.lig.f3.map5.w0 7b /r] AVX512FP16
|
||||
VCVTUSI2SH xmmreg,xmmreg*,rm64|er [rvm:t1s: evex.nds.lig.f3.map5.w1 7b /r] AVX512FP16
|
||||
VCVTUW2PH xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.f2.map5.w0 7d /r] AVX512FP16,AVX512VL
|
||||
VCVTUW2PH ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.f2.map5.w0 7d /r] AVX512FP16,AVX512VL
|
||||
VCVTUW2PH zmmreg|mask|z,zmmrm512|b16|er [rm:fv: evex.512.f2.map5.w0 7d /r] AVX512FP16
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue