- Updated to LLVM-18
- Operands have now read/write access information
- Previously only the basic extensions and the compressed ISA was supported, now every extension supported by LLVM-18 also available (e.g. vector, crypto, ...)
- Changed register names
* FP Regs: Instead of `RISCV_REG_F<n>_32` and `RISCV_REG_F<n>_64`, they're named `RISCV_REG_F<n>_F`
and `RISCV_REG_F<n>_D` for n in `0..31`
- Added register names
* Vector registes and combinations thereof `RISCV_REG_V<n>[_V<n_i>]*`, examples
* `RISCV_REG_V21`
* `RISCV_REG_V9_V10`
* `RISCV_REG_V3_V4_V5`
* etc... up to 8-register combinations
* Half-percision (16-bit) FP registers `RISCV_REG_F<n>_H` for n in `0..31`
- Changed instruction names
* Instructions ending in `_AQ_RL` now end in `_AQRL`
- Added instruction names: massive amount, see `include/capstone/riscv.h`
- Added `dimm` and `csr` fields inside the union data of `cs_riscv_op`, with corresponding `riscv_op_type`
* `dimm` is used for instructions with FP immediates
* `csr` is used for instructions with CSR systrem registes
- Added ISA flags to turn ISA extensions on and off
* Add workflow to check for C formatting
Rename run-clang-tidy.sh for consistency with clang-format script
Don't align trailing comments.
It leads to unreproducable formatting.
Reformat some comments leading in-compilable up code after clang-format
Format generated compatibility header.
Add clang-format script
Be more verbose with clean-up scripts and fail early.
Pass clang-format via command line
Install clang-format for the HeaderPatcher
* Format code with clang-format-17
* Add Sparc inc fils, delete old files and update AS with Sparc config.
* AS: Refuse to run differ if an old file is missing.
* AS: Refer to the RefactorGuide.md
* Add first translated Sparc files.
* Fixup SparcMCTargetDesc.h
* Fixup SparcDisassembler.h
* Fixup instruction printer.
* Fixup SparcInstPrinter
* Basic functions of Capstone module
* Fix SP sparc namespace prefix.
* Fix build script and linking
* Fix disassembler not actually reading bytes.
* Match \!encoding in llvm-mc output (Sparc has this).
* Add Sparc LE and and make v9 a feature to enable.
* Update test files for Sparc
* Fix tests.
* Add assembly tests
* AS: Add settings to use assembly tests.
* Test fixes
* Fix typos
* Add reg and imm details.
* Add mem details and instruction formats.
* Handle condition codes.
* Formatting
* Add hints.
* Add membar and asi tags
* Update Python bindings
* Add asi and membar to cstest
* Restructure test file
* Capstone fix for llvm-project/#139284.
* Fix branch detail tests
* Handle faulty mem operand defintions.
* Add membar and asi tests
* Add one more branch instruction test.
* Add missing call alias
* Fix tests.
Updated after fixing branch disponents.
Issues with the generated assembly tests. The assembly tests don't check the feature flags enabled. And hence V9 tests are added to the none V9 test file.
* Fix alias lookup with , in the asm_text
* Fix common detail tests.
* Fix issue.yaml
* Add Sparc changelog
* Add changelog for Sparc to v6 guide
* Fix incorrect translated array size check.
* Reading the ISA and thinking would help...
This is not how alignment is calculated -.-
* Fix call targets
* Remove 'real' BA instruction (which is only an alias).
* Add missing property getters.
* Add missing format details
* Set correct detail struct
* Support access detail testing for Sparc.
* Add hard-coded special registers tbr, wim, psr
* Add alias tests for call and ba.
* Fix copy paste mistake.
* Add note about big/little endian into guide.
* Add implied flag for SparcV9
* Format
* Store CC field consistently in an extra field.
The CC field used was sometimes stored as register,
sometimes as not at all.
Now it is consistently stored in a separated field.
* Add an invalid ASI tag.
* Fix LDSTUB/A memory access and incorrect operand details.
* Handle condition codes more elegantly.
Also fixes bugs with wrong cc fields, or missing fields.
* Add separation ; character for assembly tests.
* Apply fix from llvm-project/#143232
* Use enum types for memory operands
* Update Pythyon constants
* Fix CID 508418 - Uninitialized struct
* Fix CID 509089 - Fix OOB read and write
* Fix CID 509088 - OOB.
Also adds tests and to ensure no OOB access.
* Fix CID 509085 - Resource leak.
* Fix CID 508414 and companions - Using undefined values.
* Fix CID 508405 - Use of uninitialized value
* Remove unnecessary and badly implemented dev fuzz code.
* Fix CID 508396 - Uninitialzied variable.
* Fix CID 508393, 508365 -- OOB read.
* Fix CID 432207 - OVerlapping memory access.
* Remove unused functions
* Fix CID 432170 - Overlapping memory access.
* Fix CID 166022 - Check for negative index
* Let strncat not depend n src operand.
* Fix 509083 and 509084 - NULL dereference
* Remove duplicated code.
* Initialize sysop
* Fix resource leak
* Remove unreachable code.
* Remove duplicate code.
* Add assert to check return value of cmoack
* Fixed: d should be a signed value, since it is checked against < 0
* Add missing break.
* Add NULL check
* Fix signs of binary search comparisons.
* Add explicit cast of or result
* Fix correct scope of case.
* Handle invalid integer type.
* Return UINT_MAX instead of implicitly casted -1
* Remove dead code
* Fix type of im
* Fix type of d
* Remove duplicated code.
* Add returns after CS_ASSERTS
* Check for len == 0 case.
* Ensure shift operates on uint64
* Replace strcpy with strncpy.
* Handle edge cases for 32bit rotate
* Fix some out of enum warnings
* Replace a strcpy with strncpy.
* Fix increment of address
* Skip some linting
* Fix: set instruction id
* Remove unused enum
* Replace the last usages of strcpy with SStream functions.
* Increase number of allowed AArch64 operands.
* Check safety of incrementing t the next operand.
* Fix naming of operand
* Update python constants
* Fix option setup of CS_OPT_DETAIL_REAL
* Document DETAIL_REAL has to be used with CS_OPT_ON.
* Run Coverity scan every Monday.
* Remove dead code
* Fix OOB read
* Rename macro to reflect it is only used with sstreams
* Fix rebase issues
* Replace one- and sign-extend with MathExtra.h functions.
This fixes incorrect sign extensions and reachable
aborts().
* Wrap around PC relative values instead of abort in case of overflow.
---------
Co-authored-by: billow <billow.fun@gmail.com>
* Add auto-sync updater.
* Update Capstone core with auto-sync changes.
* Update ARM via auto-sync.
* Make changes to arch modules which are introduced by auto-sync.
* Update tests for ARM.
* Fix build warnings for make
* Remove meson.build
* Print shift amount in decimal
* Patch non LLVM register alias.
* Change type of immediate operand to unsiged (due to: #771)
* Replace all occurances of a register with its alias.
* Fix printing of signed imms
* Print rotate amount in decimal
* CHange imm type to int64_t to match LLVM imm type.
* Fix search for register names, by completing string first.
* Print ModImm operands always in decimal
* Use number format of previous capstone version.
* Correct implicit writes and update_flags according to SBit.
* Add missing test for RegImmShift
* Reverse incorrect comparision.
* Set shift information for move instructions.
* Set mem access for all memory operands
* Set subtracted flag if offset is negative.
* Add flag for post-index memory operands.
* Add detail op for BX_RET and MOVPCLR
* Use instruction post_index operand.
* Add VPOP and VPUSH as unique CS IDs.
* Add shifting info for MOVsr.
* Add TODOs.
* Add in LLVM hardcoded operands to detail.
* Move detail editing from InstPrinter to Mapping
* Formatting
* Add removed check.
* Add writeback register and constraints to RFEI instructions.
* Translate shift immediate
* Print negative immediates
* Remove duplicate invalid entry
* Add CS groups to instructions
* Fix write attriutes of stores.
* Add missing names of added instructions
* Fix LLVM bug
* Add more post_index flags
* http -> https
* Make generated functions static
* Remove tab prefix for alias instructions.
* Set ValidateMCOperand to NULL.
* Fix AddrMode3Operand operands
* Allow getting system and banked register name via API
* Add writeback to STC/LDC instructions.
* Fix (hopefully) last case where disp is negative and subtracted = true
* Remove accidentially introduced regressions
Added support for building binaries for Windows CE 7 on ARMv7 (a.k.a., Windows Embedded Compact 7) and for Windows CE 8 on ARMv7 (a.k.a., Windows Embedded Compact 2013).
Added support for building binaries for Windows CE 7 on ARMv7 (a.k.a., Windows Embedded Compact 7) and for Windows CE 8 on ARMv7 (a.k.a., Windows Embedded Compact 2013).
Replaced header inclusions of "stdint.h" and "intrin.h" by selective inclusions to support platforms that do not provide those headers. The header "platform.h" handles the platform test.
Updated the build script for Windows CE 7 on ARMv7.
