Otherwise python setup.py install from bindings/python
will fail with
SyntaxError: Non-ASCII character '\xe2' in file setup.py on line 223,
but no encoding declared; see http://python.org/dev/peps/pep-0263/ for details
* Add __repr__ for capstone.CsInsn
Currently, a `print(instruction)` displays a not very useful string like `<capstone.CsInsn object at 0x7f3759d88128>`.
This PR enhances adds a `__repr__` magic method to the `capstone.CsInsn` class so it displays as follows:
```
<cs.CsInsn: address=0x5555555545fa, size=1, mnemonic=push, op_str=rbp>
```
* Update __init__.py
* Bump the "cs_insn.bytes[]" size to 24 (from 16) to support M680x0 instructions with full EA (maximum 11 words)
Added a test for this in test_m68k.s
* Bump the "cs_detail.regs_read[]" size to 16 (from 12) to support M680x0 instructions with full REG_BITS (Dn+An = 16)
* m68k: use immediate mode syntax (#$0) for movem/fmovem instructions with empty register list
* update bindings to match changes to cs_insn and cs_detail
* Fix skipdata_setup for when _cb is None
ctypes prototype does not accept None value,
so if we want to get a NULL function pointer
then we should either call it with no arguments
or pass zero as an argument.
Fixes#1316
* Do store and return skipdata_setup data
* Add convenience wrappers for skipdata_setup
* Uncomment skipdata_setup tests
* Add alternate usage variants to test_skipdata.py
* document getter
* merge encoding branch into next branch
* added python bindings and updated test to support encoding
* fix python import
* fix py binding fields
* fix disp size printing
* fixed py binding, again
* Update CREDITS.TXT
* fixed formatting and a cast
* Changed param from int to uint8_t, fixed warnings
* Added encoding field to instructions, as per encoding branch
The encoding branch appears to have added some useful fields
accessible from the public API, including the size and offsets
of displacements and immediates in instructions. I needed access
to these fields, but the encoding branch is months behind the
active branches, so I took the minimum code from the old encoding
branch and put them into a more recent version of master.
It does seem that the most recent version does not have an offset
for the modRM byte in the InternalInstruction struct, so I did
not keep this field when bringing it to the more recent version.
I also added some of the changes made by user jellever, who added
support for accessing these new fields from the python bindings.
(cherry picked from commit d358c4b987cc77af90e24da15937e021c42f682f)
* Fixed bug with python bindings from adding encoding field
I had forgotten an import that resulted in failure when trying
to obtain instruction details.
(cherry picked from commit 44a15e378900efb624e7cdb952d32558ba0de684)
* promoted displacement to 64 bits
* Added modrm offset
* formatting from review fixed
* updated 32 bit C tests
* Added 64 and 16 bit C tests
* Updated python tests
* fixed formatting and size in py bindings
* Delete Solution.VC.db-shm
* Delete Solution.VC.db-wal
* Update test_x86.c
* fixed formatting and conditional prints
* fixed formatting
* Branch targets are a separate addressing mode
Branch targets are relative displacements that identify code locations. These are neither .w nor .l nor immediates. This change removes the immediate #s before branch target addresses in disassembly, and represents the actual branch instructions more accurately in the cs_m68k_op datastructure.
M68K Python bindings have also been updated.
* m68k_inst.pc handles better; print target for PC relative offsets
Previous changes to branch operations relied on m68k_inst.pc pointing to (start of instruction + 2). This was not the case - it pointed to the end of the current instruction. This change makes it so that m68k_inst.pc points to (start of instruction), which is simple to work with.
It also changes printing of PC relative offsets to print the absolute target address, which is consistent with how most 68000 assemblers & disassemblers behave.
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
This is one of those “how did this ever work?” changes. Problem was that as m68k_op was aliased with the imm value so when changing that to something big it would trash the values in the mem struct which would make things go really bad.
Now m68k_op_mem has been moved out of the union so this will not happen again. Also fixed instruction printing bug related to this (just happend to “work” due to the old union layout)
