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Denys Melnyk 4eb90672f3
Xtensa: gate ESP32-S3 and HIFI3 ops behind CS_MODE_XTENSA_ESP32S3 (#2979) 
The Xtensa disassembler enabled the ESP32-S3 SIMD/AI (ee.*) and HiFi3 ops for
every target because the subtarget feature gates were stubbed to return true
(Xtensa_getFeatureBits and hasDensity/hasESP32S3Ops/hasHIFI3). As a result, on a
non-ESP32-S3 Xtensa config any instruction with op0=0xE/0xF was matched as a
4-byte ee.* op, so a base-ISA byte stream desynced.

Make Xtensa_getFeatureBits map the mode to a feature set (mirroring the SystemZ
precedent), thread MI->csh->mode into the three has*Ops gates, and add an opt-in
CS_MODE_XTENSA_ESP32S3. Base/esp32/esp32s2/esp8266 no longer emit ESP32-S3 ops;
CS_MODE_XTENSA_ESP32S3 preserves them. Concrete instance of issue #1992.

The saved auto-sync patch hashes are updated so the fix survives the next LLVM
re-sync. Adds tests/MC/Xtensa/esp32s3.s.yaml.

Co-authored-by: Denys Melnyk <denys@com2cloud.com>
2026-07-22 16:13:28 +00:00
..
__init__.py Xtensa: gate ESP32-S3 and HIFI3 ops behind CS_MODE_XTENSA_ESP32S3 (#2979) 2026-07-22 16:13:28 +00:00
aarch64.py Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) 2025-06-05 11:49:20 +08:00
aarch64_const.py Apple AArch64 proprietary (#2692) 2025-05-06 12:14:13 +08:00
alpha.py Fix imm to be 64bit wide (#2840) 2025-12-30 15:55:48 +00:00
alpha_const.py v6.0.0 Alpha10 (#2998) 2026-07-21 15:50:52 +00:00
arc.py Rebased #2570 (#2614) 2025-01-28 22:34:24 +08:00
arc_const.py Rebased #2570 (#2614) 2025-01-28 22:34:24 +08:00
arm.py Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) 2025-06-05 11:49:20 +08:00
arm64.py Add arm64 and sysz compatibility layer to Python bindings (#2559) 2024-12-05 19:35:18 +08:00
arm64_const.py Add arm64 and sysz compatibility layer to Python bindings (#2559) 2024-12-05 19:35:18 +08:00
arm_const.py chore(version): Update Version to 6.0.0-Alpha3 (#2616) 2025-01-29 00:59:30 +08:00
bpf.py Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) 2025-06-05 11:49:20 +08:00
bpf_const.py Update operand type enums of all arch modules to the one in capstone.h (#2633) 2025-03-03 11:59:24 +08:00
evm.py EVM: add missing files 2018-03-31 17:32:22 +08:00
evm_const.py Apply new EVM opcode updates (#2602) 2025-01-28 20:51:43 +08:00
hppa.py HPPA fix mem operands access and instruction printing (#2746) 2025-07-06 11:21:22 +00:00
hppa_const.py Update operand type enums of all arch modules to the one in capstone.h (#2633) 2025-03-03 11:59:24 +08:00
loongarch.py Modern Testing (#2456) 2024-08-31 21:33:38 +08:00
loongarch_const.py Fix LoongArch aliases and CS_OPT_SYNTAX_NO_DOLLAR support (#2594) 2025-01-06 18:12:44 +08:00
m68k.py Add M68K ColdFire ISA support (#2927) 2026-05-22 15:04:35 +00:00
m68k_const.py v6.0.0 Alpha10 (#2998) 2026-07-21 15:50:52 +00:00
m680x.py Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) 2025-06-05 11:49:20 +08:00
m680x_const.py Extend M680X support to HCS12X (#2898) 2026-05-02 09:04:08 +00:00
mips.py Fix duplication of memory operand (#2761) 2025-07-23 17:58:47 +00:00
mips_const.py Update operand type enums of all arch modules to the one in capstone.h (#2633) 2025-03-03 11:59:24 +08:00
mos65xx.py Update Python bindings for mos65xx 2023-07-20 13:49:38 +02:00
mos65xx_const.py Update operand type enums of all arch modules to the one in capstone.h (#2633) 2025-03-03 11:59:24 +08:00
ppc.py Modern Testing (#2456) 2024-08-31 21:33:38 +08:00
ppc_const.py chore(version): Update Version to 6.0.0-Alpha3 (#2616) 2025-01-29 00:59:30 +08:00
riscv.py Add frm operands to float/double instructions (#2972) 2026-06-23 13:28:28 +00:00
riscv_const.py Add frm operands to float/double instructions (#2972) 2026-06-23 13:28:28 +00:00
sh.py Add Python bindings for SH 2023-07-24 05:44:48 +02:00
sh_const.py Update operand type enums of all arch modules to the one in capstone.h (#2633) 2025-03-03 11:59:24 +08:00
sparc.py Auto-Sync update Sparc LLVM-18 (#2704) 2025-06-24 12:45:34 +00:00
sparc_const.py v6.0.0 Alpha6 (#2834) 2026-01-13 14:12:23 +00:00
systemz.py Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) 2025-06-05 11:49:20 +08:00
systemz_const.py Coverity defects (#2469) 2024-09-18 21:19:42 +08:00
sysz_const.py Add arm64 and sysz compatibility layer to Python bindings (#2559) 2024-12-05 19:35:18 +08:00
tms320c64x.py Added support for the TMS320C64x architecture. 2017-04-14 17:00:40 +03:00
tms320c64x_const.py Update operand type enums of all arch modules to the one in capstone.h (#2633) 2025-03-03 11:59:24 +08:00
tricore.py Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) 2025-06-05 11:49:20 +08:00
tricore_const.py Add tricore tc1.8 instructions (#2595) 2025-01-28 20:50:43 +08:00
wasm.py Add Python bindings for WASM 2023-07-19 17:26:56 +02:00
wasm_const.py Update operand type enums of all arch modules to the one in capstone.h (#2633) 2025-03-03 11:59:24 +08:00
x86.py Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) 2025-06-05 11:49:20 +08:00
x86_const.py Update operand type enums of all arch modules to the one in capstone.h (#2633) 2025-03-03 11:59:24 +08:00
xcore.py Re-apply changes from 1647720656 on next branch, that's the commit that lets the python bindings run in pypy 2016-06-16 15:47:43 -07:00
xcore_const.py Update operand type enums of all arch modules to the one in capstone.h (#2633) 2025-03-03 11:59:24 +08:00
xtensa.py xtensa: update to espressif/llvm-project (#2533) 2024-11-10 21:55:40 +08:00
xtensa_const.py Release prep v6 alpha5 (#2765) 2025-08-04 11:13:08 +00:00