Add CS_OPT_SYNTAX_AARCH64_EXPLICIT_WIDE_IMM to print shifted
MOVN and MOVZ instructions in their explicit forms instead of using
the equivalent MOV aliases.
Keep the existing LLVM-compatible alias output as the default, and
retain MOV aliases for unshifted instructions when the option is
enabled.
Expose the option through cstool and the Python bindings, and add
regression tests for MOVN, MOVZ, 32-bit and 64-bit forms.
Fixes#2890
Signed-off-by: Amaan Mujawar <amaansmujawar@gmail.com>
* Add support for M68060 architecture in M68K disassembler and tests
Add disassembly support for CAS instruction in M68060 and update tests
Add support for M68K CPU32 mode and new instructions
- Introduced CS_MODE_M68K_CPU32 to support the M68K CPU32 architecture in the Python bindings and C headers.
- Updated the instruction table generator to include new CPU32-specific instructions: `bgnd`, `tbls`, `tblu`, `tblsn`, and `tblun`.
- Enhanced the instruction decoding logic in `cs.c` to account for CPU32 mode.
- Added test cases for new instructions and ensured compatibility with existing M68K modes.
- Updated YAML test files to validate the behavior of new instructions under different M68K modes.
fix(M68K): fix cross-arch bugs in cpush/cinv and dc.w printing
build_cpush_cinv: use op1->reg instead of op1->imm for address
register operand. Writing to imm (uint64_t) when reg (m68k_reg,
uint32_t) is read back causes garbage values on big-endian targets
(PPC64, s390x) due to union byte order mismatch.
M68K_printInst: cast imm to uint32_t before passing to PRIx32
format. Passing uint64_t to a PRIx32 format specifier is UB; on
32-bit big-endian MIPS the high word (0) is read instead of the
low word containing the instruction bytes.
Fixes cstest details failures on QEMU Linux PPC64, s390x, Mips32.
run clang-format
fix[m68k]: ori build_imm_ea
fix[m68k]: btst
fix[m68k]: cast immediate values to unsigned int in build_imm_ea functions
* fix get_with_index_address_mode
* - Replaced specific assembly instructions with `dc.w` for invalid cases.
- Added new test cases for SBCD, PACK, UNPK, CHK.L, and coprocessor instructions to ensure correct behavior across different CPU models.
- Ensured that invalid instructions for CPU32 and 68000 are correctly identified.
- Updated expected outputs for fsdiv and PMMU related instructions to reflect their validity on specific architectures.
* Fix CMake test command to use target file reference for integration tests
* Refactor PMOVE instruction comments for clarity and accuracy in m68k.yaml
* Add tests for bitfield instructions and PC-relative addressing in m68k.yaml
* Refactor M68K instruction printing and enhance bitfield support
- Improved the M68K instruction printer by refactoring the handling of register bits and addressing modes.
- Introduced new functions for printing scale factors, index registers, and immediate values.
- Enhanced bitfield handling in the `m68k_op_mem` structure to support both static and register-encoded values.
- Updated tests to reflect changes in instruction formatting, particularly for `cinvl`, `cpushl`, and `cas2` instructions.
- Added new test cases for bitfield instructions to ensure correct parsing and output.
- Add details to tests/m68k.yaml
* Fix type casting for immediate values in addressing modes and enhance m68k architecture support in cstool
* Refactor type usage for immediate values and enhance switch handling in M68K disassembler
- Replace int with uint32_t for immediate values, register lists, and related parameters to ensure correct type handling and consistency.
- Add default cases to switch statements for improved robustness.
- Update bitfield printing to use explicit PRId8 formatting for clarity.
- Refactor detail handling in M68KInstPrinter to use helper functions for detail access.
- Minor code cleanups and improved type safety throughout disassembler logic.
* m68k: update v6 guide
* RISC-V: add reg_access and test its usages in C and Python
reg_access is a convenience wrapper over the `operands` array that filters the register operands (including those used as memory base address) and returns them sorted into read
and written registers. It wasn't implemented for RISC-V, this PR implements it.
The following decisions were made for RISC-V:
1- System registers (CSRs) are not registers
This follows existing Capstone convention, where almost every archiceture that have system registers except x86 treats them as a seperate address space.
From a purely practical POV, the reg_access function API returns registers as an array of integers, and the address space of normal registers intersects with that of system registers
so there is nothing in the return value to distinguish them.
2- PC is not an implicit register
Whenever an instruction reads PC (e.g. all call-ish instructions JAL[R]?) this is NOT counted as an implicit read of the PC.
The reason is that the PC is somewhat "second class" in RISC-V, it's an archiectural register but has no actual index and can never be directly written to by any instruction in any
standard extension no matter the privliege.
Meanwhile, all instruction that read the PC have names that make it obvious they read the PC so adding that information to the implicit reads array would be redundant.
* introduce a +noaliascompressed option to selectively enable none-aliasing for compressed instrcution only but leave aliasing for the rest of instructions
* add tests and documentation comments
* fix python bindings and formatting
* add docs
* Enable i686 Python libraries again.
* Add Mips32, ARM, i686 cross build files and as target to CI
* Replace strndup with own implementation for Windows.
* Fix asm text test errors on 32bit machines
* Replace all add_cs_detail() functions with the arch specific ones.
* Add note about 32 bit builds in release guide.
* x86: fix decoding of mandatory prefixes
* Add exception for instructions under 0F38F..
* Handle NOP ModR/M correctly; add more tests
* List correct opcode in comment for default case
---------
Co-authored-by: Jos <jos.craaijo@ou.nl>
* Ignore ES/CS/SS/DS segment overrides in x64 mode
* Add tests for x86 segment override prefixes
* Only update prefix1 if needed
* Also check prefix details in tests
* Fix formatting
* Update release notes
* Refactor segment override handling into separate function
* Make sure function name matches documentation
* Rename function so it passes clang-format and doesn't need to be split across two lines
* Run clang-format again
---------
Co-authored-by: Jos <jos.craaijo@ou.nl>
* Add several cross compilation toolchain files.
* Make cstest compile sucessfully on targets without libyaml.
* Add cross compilation tests to CI.
* Add test for issue #2339
* Document cross compilation improvements.
* Add Sparc inc fils, delete old files and update AS with Sparc config.
* AS: Refuse to run differ if an old file is missing.
* AS: Refer to the RefactorGuide.md
* Add first translated Sparc files.
* Fixup SparcMCTargetDesc.h
* Fixup SparcDisassembler.h
* Fixup instruction printer.
* Fixup SparcInstPrinter
* Basic functions of Capstone module
* Fix SP sparc namespace prefix.
* Fix build script and linking
* Fix disassembler not actually reading bytes.
* Match \!encoding in llvm-mc output (Sparc has this).
* Add Sparc LE and and make v9 a feature to enable.
* Update test files for Sparc
* Fix tests.
* Add assembly tests
* AS: Add settings to use assembly tests.
* Test fixes
* Fix typos
* Add reg and imm details.
* Add mem details and instruction formats.
* Handle condition codes.
* Formatting
* Add hints.
* Add membar and asi tags
* Update Python bindings
* Add asi and membar to cstest
* Restructure test file
* Capstone fix for llvm-project/#139284.
* Fix branch detail tests
* Handle faulty mem operand defintions.
* Add membar and asi tests
* Add one more branch instruction test.
* Add missing call alias
* Fix tests.
Updated after fixing branch disponents.
Issues with the generated assembly tests. The assembly tests don't check the feature flags enabled. And hence V9 tests are added to the none V9 test file.
* Fix alias lookup with , in the asm_text
* Fix common detail tests.
* Fix issue.yaml
* Add Sparc changelog
* Add changelog for Sparc to v6 guide
* Fix incorrect translated array size check.
* Reading the ISA and thinking would help...
This is not how alignment is calculated -.-
* Fix call targets
* Remove 'real' BA instruction (which is only an alias).
* Add missing property getters.
* Add missing format details
* Set correct detail struct
* Support access detail testing for Sparc.
* Add hard-coded special registers tbr, wim, psr
* Add alias tests for call and ba.
* Fix copy paste mistake.
* Add note about big/little endian into guide.
* Add implied flag for SparcV9
* Format
* Store CC field consistently in an extra field.
The CC field used was sometimes stored as register,
sometimes as not at all.
Now it is consistently stored in a separated field.
* Add an invalid ASI tag.
* Fix LDSTUB/A memory access and incorrect operand details.
* Handle condition codes more elegantly.
Also fixes bugs with wrong cc fields, or missing fields.
* Add separation ; character for assembly tests.
* Apply fix from llvm-project/#143232
* Use enum types for memory operands
* Update Pythyon constants
* Make assertion hit warnings optional in release builds.
* Fix build error
* Add line and file information to assert error messages.
* Clarify CAPSTONE_ASSERTION_WARNINGS.
* Add release build tests to the CI
* Clarify Capstone hit an assert.
* Xtensa: use cs_xtensa_op_type for operand type, and use cs_ac_type for operand access mode
To explicitly tell the user the possible values of the operand
type/access mode.
Also drop the unused XTENSA_OP_MEM_REG and XTENSA_OP_MEM_IMM.
* Use cs_ac_type for operand access mode in all arches
Currently, some arches use uint8_t for operand access mode, while others
use cs_ac_type. Use cs_ac_type uniformly.
* M680X: use cs_ac_type directly, instead of adding another e_access type
* Change access type to c_uint to follow c-side changes to cs_ac_type
* Document operand access type change to enum
* Add arm64.py and sysz_const.py compatibility layer to the Python bindings
When importing `capstone.arm64` before doing other capstone imports the ARM64 constants get monkey patched into the exports.
Same with `capstone.sysz_const` for the SYSZ constants.
* Add SPDX-License comments
* Access an instruction detail in compatibility test
* Fail python tests on error instead of just ERROR output
Include the test_iter.py in the test_all.py too.
* Improve python compatibility docs
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
* Test for ARM_CC_* constants presence
---------
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
* Fix Pn was printed as register, not predicate.
* Fix: is_alias must be an int to allow for -1 as false.
* Fix, shift immediate was casted to incorrect width.
* Store theexact float also in fp field for convenience.
* Fix: MRS has no implicit write of NCVZ
* Fix signs of Imm8 shifted operands.
* Fix another MRS test
* Fix: Src operand of CASAL had write flag set.
* Fix sysop access in Python data structures.
* Fix#2381
* Fix#2382
* Fix post-index correction only for pop with single register
* Fix missing memory index register scale
* Remove faulty and duplicated lshift field.
* Add shift information to shift alias instructions and add several tests.
* Fix scale tests
---------
Co-authored-by: Wu ChenXu <kabeor00@gmail.com>
* Remove Windows msvc project files and move build instructions to single BUILDING.md file.
* Move HACK.txt to Contributing and update it.
* Add refactoring guide.
* Add known bugs
* Remove compatibility headers.
* Fix smaller issues.
* Remove 'possible revert' column. People always can do manual changes.
* Move instruction alias description to the top
* Add table to general breaking changes.
* Update general release guide with the newest information.
* Highlight NanoMips and be more precise in writing.
* Add note about archs without alias.
* Add sentence about what is planned.
* Small corrections for Windows build instructions and debug macros.
* Fix rebase issues.
* Bring back make.sh for the CI
* Fix CID 508418 - Uninitialized struct
* Fix CID 509089 - Fix OOB read and write
* Fix CID 509088 - OOB.
Also adds tests and to ensure no OOB access.
* Fix CID 509085 - Resource leak.
* Fix CID 508414 and companions - Using undefined values.
* Fix CID 508405 - Use of uninitialized value
* Remove unnecessary and badly implemented dev fuzz code.
* Fix CID 508396 - Uninitialzied variable.
* Fix CID 508393, 508365 -- OOB read.
* Fix CID 432207 - OVerlapping memory access.
* Remove unused functions
* Fix CID 432170 - Overlapping memory access.
* Fix CID 166022 - Check for negative index
* Let strncat not depend n src operand.
* Fix 509083 and 509084 - NULL dereference
* Remove duplicated code.
* Initialize sysop
* Fix resource leak
* Remove unreachable code.
* Remove duplicate code.
* Add assert to check return value of cmoack
* Fixed: d should be a signed value, since it is checked against < 0
* Add missing break.
* Add NULL check
* Fix signs of binary search comparisons.
* Add explicit cast of or result
* Fix correct scope of case.
* Handle invalid integer type.
* Return UINT_MAX instead of implicitly casted -1
* Remove dead code
* Fix type of im
* Fix type of d
* Remove duplicated code.
* Add returns after CS_ASSERTS
* Check for len == 0 case.
* Ensure shift operates on uint64
* Replace strcpy with strncpy.
* Handle edge cases for 32bit rotate
* Fix some out of enum warnings
* Replace a strcpy with strncpy.
* Fix increment of address
* Skip some linting
* Fix: set instruction id
* Remove unused enum
* Replace the last usages of strcpy with SStream functions.
* Increase number of allowed AArch64 operands.
* Check safety of incrementing t the next operand.
* Fix naming of operand
* Update python constants
* Fix option setup of CS_OPT_DETAIL_REAL
* Document DETAIL_REAL has to be used with CS_OPT_ON.
* Run Coverity scan every Monday.
* Remove dead code
* Fix OOB read
* Rename macro to reflect it is only used with sstreams
* Fix rebase issues
* Add test with ASAN enabled.
* Fix leaks in cstool and cs.c
* Add work around so ASAN binaries don't DEADSIGNAL due to too many randomized address bits.
* Add ASAN build arguments to cstest
* Fix leaks in cstest
* Use cstest binary build by the main build.
* Add clonging step for cmocka when cstest is build
* Skip Python tests for ASAN
* Remove make build from CI
* Fix leaks in cstest.
- Rewrite split to remove leaks and improve runtime by 6%
- Add free()
* Fix cmocka external project to stable branch.
* Revert "Fix leaks in cstest."
This reverts commit bf8ee125b0c58f9c794eb081a69c80f8a71825cd.
* Fix memleaks in cstest
* Document adding of ASAN job to release guide
* Add CAPSTONE_BUILD_CSTEST to build docs
* Fix double free
* Add more detail tests to CI and fix them
* Initialize variables
* Fix typo
* Update cstest build docs
* Revert "Remove make build from CI"
This reverts commit 84f7360c6da6183cd41bec0fef3e1d0a2ee49ddf.
* Make cstest only run for cmake builds.
* Add cstest job for make build.
* Add CAPSTONE_DIET build test.
* Compile the compatibility header test with ASAN if enabled.
* Fix DIET build by excluding not used code.
* Missing "
* Build static library with ASAN and DIET if enabled.
* Revert "Add CAPSTONE_DIET build test."
This reverts commit 71e1469dee.
* Restructure auto-sync docs to have them more contained in suite/auto-sync
* Enhance Differ documentation
* Fix link and emphasize importance of ARCHITECTURE.md
* Add auto-syc intro.md document, based on @moste00 work
* Be consistent with Auto-Sync naming and use python3
* Add a Capstone v6 release guide with a general explanation,
breaking changes and new feature descriptions.
* Add note about Rizin sponsorship
* Fix spelling and grammar mistakes.
* Add auto-sync updater.
* Update Capstone core with auto-sync changes.
* Update ARM via auto-sync.
* Make changes to arch modules which are introduced by auto-sync.
* Update tests for ARM.
* Fix build warnings for make
* Remove meson.build
* Print shift amount in decimal
* Patch non LLVM register alias.
* Change type of immediate operand to unsiged (due to: #771)
* Replace all occurances of a register with its alias.
* Fix printing of signed imms
* Print rotate amount in decimal
* CHange imm type to int64_t to match LLVM imm type.
* Fix search for register names, by completing string first.
* Print ModImm operands always in decimal
* Use number format of previous capstone version.
* Correct implicit writes and update_flags according to SBit.
* Add missing test for RegImmShift
* Reverse incorrect comparision.
* Set shift information for move instructions.
* Set mem access for all memory operands
* Set subtracted flag if offset is negative.
* Add flag for post-index memory operands.
* Add detail op for BX_RET and MOVPCLR
* Use instruction post_index operand.
* Add VPOP and VPUSH as unique CS IDs.
* Add shifting info for MOVsr.
* Add TODOs.
* Add in LLVM hardcoded operands to detail.
* Move detail editing from InstPrinter to Mapping
* Formatting
* Add removed check.
* Add writeback register and constraints to RFEI instructions.
* Translate shift immediate
* Print negative immediates
* Remove duplicate invalid entry
* Add CS groups to instructions
* Fix write attriutes of stores.
* Add missing names of added instructions
* Fix LLVM bug
* Add more post_index flags
* http -> https
* Make generated functions static
* Remove tab prefix for alias instructions.
* Set ValidateMCOperand to NULL.
* Fix AddrMode3Operand operands
* Allow getting system and banked register name via API
* Add writeback to STC/LDC instructions.
* Fix (hopefully) last case where disp is negative and subtracted = true
* Remove accidentially introduced regressions
